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Hardware Modeling Using Verilog

Assignment- Week 4
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 X 1 = 10
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QUESTION 1:
If A, B, C and D are reg, reg, integer and wire variables respectively, each of size [7:0], which of
the following is/are allowed inside a procedural block?

a. D = A + B;
b. C = A + D;
c. D = C + 1;
d. B[3:0] = D[4:1] + 1;

Correct Answer: b, d

Detailed Solution:

In a procedural assignment statement, only register type variables or part select thereof can be
used in the left hand side. A wire type variable cannot be assigned a value within a procedural
block. Hence, the correct options are (b) and (d).

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QUESTION 2:
For the following code segment, the final value of variable “d” will be …………..
integer a, b, c, d;
initial
begin
a = 25; b = 12; c = 5; d = 17;
a = b + c;
b = a – 15;
c = a + d;
d = c + d;
end

HINT: ( Please provide numeric answer, e.g. 37, do not type thirty seven.)
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Correct Answer: 51

Detailed Solution:

In blocking assignments, statements are executed one after the other.

First assignment: a = 12 + 5 = 17
Second assignment: b = 17 – 15 = 2
Third assignment: c = 17 + 17 = 34
Fourth assignment: d = 34 + 17 = 51
Thus, final value of variable “d” will be 51.
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QUESTION 3:
For the following code segment, the final value of variable “d” will be …………..

integer a, b, c, d;
initial
begin
a = 25; b = 12; c = 5; d = 17;
end
initial
begin
a <= #10 b + c;
b <= #10 a – 15;
c <= #10 a + d;
d <= #10 c + d;
end

HINT: ( Please provide numeric answer, e.g. 53, do not type fifty three.)

Correct Answer: 22

Detailed Solution:

In non-blocking statements inside a procedural block, all right hand side expressions are
evaluated in parallel, and are assigned to the left hand side variables all together.
First assignment: a = 12 + 5 = 17
Second assignment: b = 25 – 15 = 10
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Third assignment: c = 25 + 17 = 42
Fourth assignment: d = 5 + 17 = 22
Thus, final value of variable “d” will be 22.

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QUESTION 4:
What will the following code segment do?

always @(posedge clock)

begin
y = x;
z = y;
x = z;
end
a. Shift the values stored in the three variables.
b. All the variables will get the value previously stored in “x”
c. All the variables will get the value previously stored in “y”.
d. All the variables will get the value previously stored in “z”.

Correct Answer: b

Detailed Solution:

Because the assignments are blocking, first, the value of “x” will be assigned to “y”, and then
the new value of “y” will be assigned to “z”, and then the new value of “z” will be assigned to
“x”. Thus all the three variables will get the previous value stored in “x”. Hence, the correct
option is (b).

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QUESTION 5:
If the 8-bit variable “data” declared as “reg [7:0] data” is initialized to 8’b01100101,
what will be its value after execution of the following code segment?

always @(posedge clock)

begin
data[6:0] <= data[6:0] >> 1;
data[7] <= data[0];
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end
a. 8’b10110010
b. 8’b00110010
c. 8’b01110010
d. None of these.

Correct Answer: a

Detailed Solution:

The RHS of the first assignment will be data[6:0] >> 1 = 0110010

The RHS of the second assignment will be data[0] = 1
For non-blocking assignment, both the assignments will happen together. Hence, final value of
data = 10110010.
Thus, the correct option is (a).

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QUESTION 6:
What will the following code segment generate on synthesis, assuming that the four variables
data0, data1, data2 and data3 map into four latches / flip-flops?

always @(posedge clock)

begin
data3 = din;
data2 = data3;
data1 = data2;
data0 = data1;
end
a. Four D flip-flops all fed with the data “din”.
b. A 4-bit shift register.
c. A 4-bit parallel-in parallel-out register.
d. None of these.

Correct Answer: a

Detailed Solution:
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Since blocking assignment statements are executed sequentially one after another, the value of
“din” will be first assigned to “data3”, then to “data2”, then to “data1”, and finally to “data0”.
Thus, the same input will feed all the four D flip-flops in the synthesized circuit. The correct
option is (a).

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QUESTION 7:
What will the following code segment generate on synthesis?

always @(posedge clock)

begin
data3 <= din;
data2 <= data3;
data1 <= data2;
data0 <= data1;
end
a. Four D flip-flops all fed with the data “din”.
b. A 4-bit shift register.
c. A 4-bit parallel-in parallel-out register.
d. None of these.

Correct Answer: b

Detailed Solution:

Since we use non-blocking assignments, the values on the RHS are assigned to the variables on
the LHS in synchronism with the clock. This will generate a 4-bit shift register. Thus, the correct
option is (b).

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QUESTION 8:
What does the following Verilog module do?

module xor_bitwise (f, a, b);

parameter N = 16;
input [N-1:0] a, b;
output [N-1:0] f;
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genvar p;
generate for (p=0; p<N; p=p+1)
begin xorlp
xor XG (f[p], a[p], b[p]);
end
endgenerate
endmodule
a. Generates the sum of the two N-bit numbers “a” and “b”, and stores it in “f”
b. Performs the bitwise XOR of “a” and “b”, and stores it in “f”
c. Computes whether the number of bits in “a” and “b” are odd
d. None of these.

Correct Answer: b

Detailed Solution:

As discussed in Example 1 of Lecture 19, this Verilog module will generate N XOR gates, and will
compute the bitwise XOR of the two numbers “a” and “b”. Thus, the correct option is (b).

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QUESTION 9:
Which of the following is/are not true for “generate” blocks?

a. Multiple copies of code blocks are generated dynamically before simulation or

synthesis.
b. Can be used to instantiate multiple copies of some module.
c. Must be used along with a variable of type “genvar”.
d. None of these.

Correct Answer: d

Detailed Solution:

All of (a), (b) and (c) are true for “generate” blocks. Hence, the correct option is (d).
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QUESTION 10:
Which of the following is/are true for user defined primitives in Verilog?
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a. Can be used to specify a combinational circuit with any number of outputs.

b. Can be used to specify a combinational circuit with a single output.
c. Can be used to specify a finite state machine with one or two state variables.
d. Can be used to specify a finite state machine with only one state variable.

Correct Answer: b, d

Detailed Solution:

We can specify a combinational circuit with only one output.

We can specify a FSM with only one state variable.
Hence, the correct options are (b) and (d).
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