a 8-Bit, High Speed, Multiplying D/A Converter

(Universal Digital Logic Interface)

DAC08
FEATURES ence and full-scale currents eliminates the need for full-scale
Fast Settling Output Current: 85 ns trimming in most applications. Direct interface to all popular
Full-Scale Current Prematched to 61 LSB logic families with full noise immunity is provided by the high
Direct Interface to TTL, CMOS, ECL, HTL, PMOS swing, adjustable threshold logic input.
Nonlinearity to 0.1% Maximum Over High voltage compliance complementary current outputs are
Temperature Range provided, increasing versatility and enabling differential opera-
High Output Impedance and Compliance: tion to effectively double the peak-to-peak output swing. In
–10 V to +18 V many applications, the outputs can be directly converted to volt-
Complementary Current Outputs age without the need for an external op amp.
Wide Range Multiplying Capability: 1 MHz Bandwidth
Low FS Current Drift: 610 ppm/8C All DAC08 series models guarantee full 8-bit monotonicity, and
Wide Power Supply Range: 64.5 V to 618 V nonlinearities as tight as ± 0.1% over the entire operating tem-
Low Power Consumption: 33 mW @ 65 V perature range are available. Device performance is essentially
Low Cost unchanged over the ± 4.5 V to ± 18 V power supply range, with
Available in Die Form 33 mW power consumption attainable at ± 5 V supplies.
The compact size and low power consumption make the
DAC08 attractive for portable and military/aerospace appli-
GENERAL DESCRIPTION
cations; devices processed to MIL-STD-883, Level B are
available.
The DAC08 series of 8-bit monolithic digital-to-analog convert-
ers provide very high-speed performance coupled with low cost DAC08 applications include 8-bit, 1 µs A/D converters, servo
and outstanding applications flexibility. motor and pen drivers, waveform generators, audio encoders
Advanced circuit design achieves 85 ns settling times with very and attenuators, analog meter drivers, programmable power
supplies, CRT display drivers, high-speed modems and other
low “glitch” energy and at low power consumption. Monotonic
applications where low cost, high speed and complete input/out-
multiplying performance is attained over a wide 20 to 1 refer-
ence current range. Matching to within 1 LSB between refer- put versatility are required.

FUNCTIONAL BLOCK DIAGRAM

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
DAC08–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 615 V, I S REF = 2.0 mA, –558C ≤ TA ≤ +1258C for DAC08/08A, 08C ≤ TA ≤ +708C for
DAC08C, E & H unless otherwise noted. Output characteristics refer to both IOUT and IOUT .)
DAC08A/H DAC08E DAC08C
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units

Resolution 8 8 8 Bits
Monotonicity 8 8 8 Bits
Nonlinearity NL ± 0.1 ± 0.19 ± 0.39 % FS
Settling Time tS To ± 1/2 LSB, 85 135 85 150 85 150 ns
All Bits Switched ON
or OFF, TA = 25°C1
Propagation Delay
Each Bit tPLH TA = 25°C1 35 60 35 60 35 60 ns
All Bits Switched tPHL 35 60 35 60 35 60 ns
Full-Scale Tempco1 TCIFS ± 10 ± 50 ± 10 ± 80 ± 10 ± 80 ppm/°C
DAC08E ± 50
Output Voltage
Compliance VOC Full-Scale Current
(True Compliance) Change <1/2 LSB, –10 +18 –10 +18 –10 +18 V
ROUT > 20 MΩ typ
Full Range Current IFR4 VREF = 10.000 V 1.984 1.992 2.000 1.94 1.99 2.04 1.94 1.99 2.04 mA
R14, R15 = 5.000 kΩ
TA = +25°C
Full Range Symmetry IFRS IFR4 – IFR2 ± 0.5 ±4 ±1 ±8 ±2 ± 16 µA
Zero-Scale Current IZS 0.1 1 0.2 2 0.2 4 µA
Output Current Range IOR1 R14, R15 = 5.000 kΩ 2.1 2.1 2.1 mA
IOR2 VREF = +15.0 V,
V– = –10 V
VREF = +25.0 V, 4.2 4.2 4.2 mA
V– = –12 V
Output Current Noise IREF = 2 mA 25 25 25 nA
Logic Input Levels
Logic “0” VIL VLC = 0 V 0.8 0.8 0.8 V
Logic Input “1” VIL 2 2 2 V
Logic Input Current VLC = 0 V
Logic “0” IIL VIN = –10 V to +0.8 V –2 –10 –2 –10 –2 –10 µA
Logic Input “1” IIH VIN = 2.0 V to 18 V 0.002 10 0.002 10 0.002 10 µA
Logic Input Swing VIS V– = –15 V –10 +18 –10 +18 –10 +18 V
Logic Threshold Range VTHR VS = ± 15 V1 –10 +13.5 –10 +13.5 –10 +13.5 V
Reference Bias Current I15 –1 –3 –1 –3 –1 –3 µA
Reference Input dI/dt REQ = 200 Ω 4 8 4 8 4 8 mA/µs
Slew Rate RL = 100 Ω
CC = 0 pF See Fast Pulsed Ref. Info Following.1
Power Supply Sensitivity PSSIFS+ V+ = 4.5 V to 18 V ± 0.0003 ± 0.01 ± 0.0003 ± 0.01 ± 0.0003 ± 0.01 %∆IO/%∆V+
PSSIFS– V– = –4.5 V to –18 V ± 0.002 ± 0.01 ± 0.002 ± 0.01 ± 0.002 ± 0.01 %∆IO/%∆V–
IREF = 1.0 mA

Power Supply Current I+ VS = ± 5 V, IREF = 1.0 mA 2.3 3.8 2.3 3.8 2.3 3.8 mA
I– –4.3 –5.8 –4.3 –5.8 –4.3 –5.8 mA
I+ VS = +5 V, –15 V, 2.4 3.8 2.4 3.8 2.4 3.8 mA
I– IREF = 2.0 mA –6.4 –7.8 –6.4 –7.8 –6.4 –7.8 mA
I+ VS = ± 15 V, IREF = 2.5 3.8 2.5 3.8 2.5 3.8 mA
I– 2.0 mA –6.5 –7.8 –6.5 –7.8 –6.5 –7.8 mA

Power Dissipation Pd ± 5 V, IREF = 1.0 mA 33 48 33 48 33 48 mW

+5 V, –15 V, IREF =
2.0 mA 108 136 103 136 108 136 mW
± 15 V, IREF = 2.0 mA 135 174 135 174 135 174 mW

NOTES
1
Guaranteed by design.
Specifications subject to change without notice.

–2– REV. A
 DAC08
TYPICAL ELECTRICAL CHARACTERISTICS (@ VS = 615 V, and IREF = 2.0 mA, unless otherwise noted. Output
characteristics apply to both IOUT and IOUT .)
All Grades
Parameter Symbol Conditions Typical Units
Reference Input Slew Rate dI/dt 8 mA/µs
Propagation Delay tPLH, tPHL TA = 25°C, Any Bit 35 ns
Settling Time tS To +1/2 LSB, All Bits
Switched ON or OFF, 85 ns
TA = 25°C
NOTES
For DAC08NT & GT 25°C characteristics, see DAC08N & G characteristics respectively.
Specifications subject to change without notice

ABSOLUTE MAXIMUM RATINGS 1 PIN CONNECTIONS

Operating Temperature
DAC08AQ, Q . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C 16-Pin Dual-In-Line Package
DAC08HQ, EQ, CQ, HP, EP, CP, CS . . . . . 0°C to +70°C (Q Suffix)
Junction Temperature (TJ) . . . . . . . . . . . . . . –65°C to +150°C
Storage Temperature Q Package . . . . . . . . . . –65°C to +150°C
Storage Temperature P Package . . . . . . . . . . –65°C to +125°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . . 300°C
V+ Supply to V– Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . V– to V– plus 36 V
VLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V– to V+
Analog Current Outputs (at VS– = 15 V) . . . . . . . . . . 4.25 mA
Reference Input (V14 to V15) . . . . . . . . . . . . . . . . . . . V– to V+
Reference Input Differential Voltage
(V14 to V15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V 16-Lead SO
Reference Input Current (I14) . . . . . . . . . . . . . . . . . . . 5.0 mA (S Suffix)

Package Type uJA2 uJC Units

16-Pin Hermetic DIP (Q) 100 16 °C/W
16-Pin Plastic DIP (P) 82 39 °C/W
20-Contact LCC (RC) 76 36 °C/W
16-Pin SO (S) 111 35 °C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for cerdip, P-DIP, and LCC packages; θJA is specified for device soldered DAC08RC/883 20-Lead LCC
to printed circuit board for SO package. (RC Suffix)

ORDERING GUIDE1

16-Pin Dual-In-Line Package Operating

Temperature
NL Hermetic Plastic LCC Range

0.1% DAC08AQ2 MIL

DAC08HQ DAC08HP COM
0.19% DAC08Q2 DAC08RC/883 MIL
DAC08EQ DAC08EP COM
0.39% DAC08CQ DAC08CP COM
DAC08CS3 COM NC = NO CONNECT

NOTES
1
Burn-in is available on commercial and industrial temperature range parts in
cerdip, plastic DIP, and TO-can packages.
2
For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
3
For availability and burn-in information on SO and PLCC packages, contact
your local sales office.

REV. A –3–
DAC08
WAFER TEST LIMITS (@ V = 615 V, I S REF = 2.0 mA, TA = 1258C for DAC08NT, DAC08GT devices; TA = 258C for DAC08N,
DAC08G and DAC08GR devices, unless otherwise noted. Output characteristics apply to both IOUT and IOUT .)
DAC08NT DAC08N DAC08GT DAC08G DAC08GR
Parameter Symbol Conditions Limit Limit Limit Limit Limit Units

Resolution 8 8 8 8 8 Bits min

Monotonicity 8 8 8 8 8 Bits min
Nonlinearity NL ± 0.1 ± 0.1 ± 0.19 ± 0.19 ± 0.39 % FS max
Output Voltage VOC Full-Scale Current +18 +18 +18 +18 +18 V max
Compliance Change < 1/2 LSB –10 –10 –10 –10 –10 V min
Full-Scale Current IFS4 or VREF = 10.000 V 2.04 2.04 2.04 2.04 2.04 mA max
IFS2 R14, R15 = 5.000 kΩ 1.94 1.94 1.94 1.94 1.94 mA min
Full-Scale Symmetry IFSS ±8 ±8 ±8 ±8 ± 16 µA max
Zero-Scale Current IZS 2 2 4 4 4 µA max
Output Current Range IFS1 V– = –10 V,
VREF = +15 V 2.1 2.1 2.1 2.1 2.1 mA min
V– = –12 V,
IFS2 VREF = +25 V 4.2 4.2 4.2 4.2 4.2 mA min
R14, R15 = 5.000 kΩ
Logic Input “0” VIL 0.8 0.8 0.8 0.8 0.8 V max
Logic Input “1” VIH 2 2 2 2 2 V min
Logic Input Current VLC = 0 V
Logic “0” IIL VIN = –10 V to +0.8 V ± 10 ± 10 ± 10 ± 10 ± 10 µA max
Logic “1” IIH VIN = 2.0 V to 18 V ± 10 ± 10 ± 10 ± 10 ± 10 µA max
Logic Input Swing VIS V– = –15 V +18 +18 +18 +18 +18 V max
–10 –10 –10 –10 –10 V min
Reference Bias Current I15 –3 –3 –3 –3 –3 µA max
Power Supply PSSIFS+ V+ = 4.5 V to 18 V 0.01 0.01 0.01 0.01 0.01 % FS/% V max
Sensitivity PSSIFS– V– = –4.5 V to –18 V
IREF = 1.0 mA
Power Supply Current I+ VS = ± 15 V 3.8 3.8 3.8 3.8 3.8 mA max
IREF ≤ 2.0 mA –7.8 –7.8 –7.8 –7.8 –7.8 µA max
Power Dissipation Pd VS = ± 15 V 174 174 174 174 174 mW max
IREF ≤ 2.0 mA
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

DICE CHARACTERISTICS
(+125°C Tested Dice Available)

–4– REV. A
 DAC08

Figure 1. Pulsed Reference Operation

Figure 2. Burn-in Circuit

Figure 3. Fast Pulsed Reference

Operation

Figure 4. True and Complimentary Figure 5. LSB Switching Figure 6. Full-Scale Settling Time
Output Operation

REV. A –5–
DAC08 –Typical Performance Characteristics

Figure 7. Full-Scale Current Figure 8. LSB Propagation Figure 9. Reference Input

vs. Reference Current Delay vs. IFS Frequency Response

Figure 10. Reference Amp Figure 11. Logic Input Current vs. Figure 12. VTH–VLC vs. Temperature
Common-Mode Range Input Voltage

Figure 13. Output Current vs. Figure 14. Output Voltage Figure 15. Bit Transfer Characteristics
Output Voltage (Output Compliance vs. Temperature
Voltage Compliance)

–6– REV. A
 DAC08

Figure 16. Power Supply Figure 17. Power Supply Figure 18. Power Supply
Current vs. V+ Current vs. V– Current vs. Temperature

BASIC CONNECTIONS

Figure 19. Accomodating Bipolar References Figure 20. Basic Positive Reference Operation

Figure 21. Basic Unipolar Negative Operation

REV. A –7–
DAC08

Figure 22. Basic Bipolar Output Operation

Figure 23. Recommended Full-Scale Adjustment Circuit Figure 24. Basic Negative Reference Operation

Figure 25. Offset Binary Operation

–8– REV. A
 DAC08

Figure 26. Positive Low Impedance Figure 27. Negative Low Impedance
Output Operation Output Operation

Figure 28. Interfacing With Various Logic Families

APPLICATIONS INFORMATION Bipolar references may be accommodated by offsetting VREF or

REFERENCE AMPLIFIER SET-UP pin 15. The negative common-mode range of the reference am-
The DAC08 is a multiplying D/A converter in which the output plifier is given by: VCM– = V– plus (IREF × 1 kΩ) plus 2.5 V. The
current is the product of a digital number and the input refer- positive common-mode range is V+ less 1.5 V.
ence current. The reference current may be fixed or may vary When a dc reference is used, a reference bypass capacitor is rec-
from nearly zero to +4.0 mA. The full-scale output current is a ommended. A 5.0 V TTL logic supply is not recommended as a
linear function of the reference current and is given by: reference. If a regulated power supply is used as a reference, R14
should be split into two resistors with the junction bypassed to
255
IFR = × IREF, where IREF = I14. ground with a 0.1 µF capacitor.
256
For most applications the tight relationship between IREF and
In positive reference applications, an external positive reference
IFS will eliminate the need for trimming IREF. If required,
voltage forces current through R14 into the VREF(+) terminal
full-scale trimming may be accomplished by adjusting the value
(pin 14) of the reference amplifier. Alternatively, a negative ref-
of R14, or by using a potentiometer for R14. An improved
erence may be applied to VREF(–) at pin 15; reference current
method of full-scale trimming which eliminates potentiometer
flows from ground through R14 into VREF(+) as in the positive
T.C. effects is shown in the recommended full-scale adjustment
reference case. This negative reference connection has the ad-
circuit.
vantage of a very high impedance presented at pin 15. The volt-
age at pin 14 is equal to and tracks the voltage at pin 15 due to Using lower values of reference current reduces negative power
the high gain of the internal reference amplifier. R15 (nominally supply current and increases reference amplifier negative common-
equal to R14) is used to cancel bias current errors; R15 may be mode range. The recommended range for operation with a dc
eliminated with only a minor increase in error. reference current is +0.2 mA to +4.0 mA.

REV. A –9–
DAC08
REFERENCE AMPLIFIER COMPENSATION FOR in a negative or inverted logic D/A converter. Both outputs may
MULTIPLYING APPLICATIONS be used simultaneously. If one of the outputs is not required it
AC reference applications will require the reference amplifier to must be connected to ground or to a point capable of sourcing
be compensated using a capacitor from pin 16 to V–. The value IFS; do not leave an unused output pin open.
of this capacitor depends on the impedance presented to pin 14: Both outputs have an extremely wide voltage compliance en-
for R14 values of 1.0, 2.5 and 5.0 kΩ, minimum values of CC abling fast direct current-to-voltage conversion through a resis-
are 15, 37, and 75 pF. Larger values of R14 require proportion- tor tied to ground or other voltage source. Positive compliance
ately increased values of CC for proper phase margin, such that is 36 V above V– and is independent of the positive supply.
the ratio of CC (pF) to R14 (kΩ) = 15. Negative compliance is given by V– plus (IREF × 1 kΩ) plus 2.5 V.
For fastest response to a pulse, low values of R14 enabling small The dual outputs enable double the usual peak-to-peak load
CC values should be used. If pin 14 is driven by a high imped- swing when driving loads in quasi-differential fashion. This fea-
ance such as a transistor current source, none of the above val- ture is especially useful in cable driving, CRT deflection and in
ues will suffice and the amplifier must be heavily compensated other balanced applications such as driving center-tapped coils
which will decrease overall bandwidth and slew rate. For R14 = and transformers.
1 kΩ and CC = 15 pF, the reference amplifier slews at 4 mA/µs
enabling a transition from IREF = 0 to IREF = 2 mA in 500 ns. POWER SUPPLIES
Operation with pulse inputs to the reference amplifier may be The DAC08 operates over a wide range of power supply volt-
accommodated by an alternate compensation scheme. This ages from a total supply of 9 V to 36 V. When operating at sup-
technique provides lowest full-scale transition times. An internal plies of ± 5 V or less, IREF ≤ 1 mA is recommended. Low
clamp allows quick recovery of the reference amplifier from a reference current operation decreases power consumption and
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA) increases negative compliance, reference amplifier negative
occurs in 120 ns when the equivalent impedance at pin 14 is common-mode range, negative logic input range, and negative
200 Ω and CC = 0. This yields a reference slew rate of 16 mA/µs logic threshold range; consult the various figures for guidance.
which is relatively independent of RIN and VIN values. For example, operation at –4.5 V with IREF = 2 mA is not rec-
ommended because negative output compliance would be re-
LOGIC INPUTS duced to near zero. Operation from lower supplies is possible,
The DAC08 design incorporates a unique logic input circuit however at least 8 V total must be applied to insure turn-on of
which enables direct interface to all popular logic families and the internal bias network.
provides maximum noise immunity. This feature is made pos- Symmetrical supplies are not required, as the DAC08 is quite
sible by the large input swing capability, 2 µA logic input cur- insensitive to variations in supply voltage. Battery operation is
rent and completely adjustable logic threshold voltage. For V– = feasible as no ground connection is required: however, an artifi-
–15 V, the logic inputs may swing between –10 V and +18 V. cial ground may be used to insure logic swings, etc. remain be-
This enables direct interface with +15 V CMOS logic, even tween acceptable limits.
when the DAC08 is powered from a +5 V supply. Minimum in-
put logic swing and minimum logic threshold voltage are given Power consumption may be calculated as follows:
by: V– plus ( IREF × 1 kΩ) plus 2.5 V. The logic threshold may Pd = (I+) (V+) + (I–) (V–). A useful feature of the DAC08 design
be adjusted over a wide range by placing an appropriate voltage is that supply current is constant and independent of input logic
at the logic threshold control pin (pin 1, VLC). The appropriate states; this is useful in cryptographic applications and further
graph shows the relationship between VLC and VTH over the serves to reduce the size of the power supply bypass capacitors.
temperature range, with VTH nominally 1.4 above VLC. For
TTL and DTL interface, simply ground pin 1. When interfacing TEMPERATURE PERFORMANCE
ECL, an IREF = 1 mA is recommended. For interfacing other The nonlinearity and monotonicity specifications of the DAC08
logic families, see preceding page. For general set-up of the logic are guaranteed to apply over the entire rated operating tempera-
control circuit, it should be noted that pin 1 will source 100 µA ture range. Full-scale output current drift is low, typically
typical; external circuitry should be designed to accommodate ± 10 ppm/°C, with zero-scale output current and drift essentially
this current. negligible compared to 1/2 LSB.
Fastest settling times are obtained when pin 1 sees a low imped- The temperature coefficient of the reference resistor R14 should
ance. If pin 1 is connected to a 1 kΩ divider, for example, it match and track that of the output resistor for minimum overall
should be bypassed to ground by a 0.01 µF capacitor. full-scale drift. Settling times of the DAC08 decrease approxi-
mately 10% at –55°C; at +125°C an increase of about 15%
ANALOG OUTPUT CURRENTS is typical.
Both true and complemented output sink currents are provided
The reference amplifier must be compensated by using a capaci-
where IO + IO = IFS. Current appears at the “true” (IO) output tor from pin 16 to V–. For fixed reference operation, a 0.01 µF
when a “1” (logic high) is applied to each logic input. As the bi- capacitor is recommended. For variable reference applications,
nary count increases, the sink current at pin 4 increases propor- see previous section entitled “Reference Amplifier Compensa-
tionally, in the fashion of a “positive logic” D/A converter. When a tion for Multiplying Applications”.
“0” is applied to any input bit, that current is turned off at pin 4
and turned on at pin 2. A decreasing logic count increases IO as

–10– REV. A
 DAC08
MULTIPLYING OPERATION Measurement of settling time requires the ability to accurately
The DAC08 provides excellent multiplying performance with an resolve ± 4 µA, therefore a 1 kΩ load is needed to provide ad-
extremely linear relationship between IFS and IREF over a range equate drive for most oscilloscopes. The settling time fixture
of 4 mA to 4 mA. Monotonic operation is maintained over a shown in schematic labelled “Settling Time Measurement” uses
typical range of IREF from 100 µA to 4.0 mA. a cascode design to permit driving a 1 kΩ load with less than
5 pF of parasitic capacitance at the measurement node. At IREF
SETTLING TIME values of less than 1.0 mA, excessive RC damping of the output
The DAC08 is capable of extremely fast settling times, typically is difficult to prevent while maintaining adequate sensitivity.
85 ns at IREF = 2.0 mA. Judicious circuit design and careful However, the major carry from 01111111 to 10000000 provides
board layout must be employed to obtain full performance po- an accurate indicator of settling time. This code change does
tential during testing and application. The logic switch design not require the normal 6.2 time constants to settle to within
enables propagation delays of only 35 ns for each of the 8 bits. ± 0.2% of the final value, and thus settling times may be ob-
Settling time to within 1/2 LSB of the LSB is therefore 35 ns, served at lower values of IREF.
with each progressively larger bit taking successively longer. The
DAC08 switching transients or “glitches” are very low and may
MSB settles in 85 ns, thus determining the overall settling time
be further reduced by small capacitive loads at the output at a
of 85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.
minor sacrifice in settling time.
The output capacitance of the DAC08 including the package is
approximately 15 pF, therefore the output RC time constant Fastest operation can be obtained by using short leads, minimiz-
dominates settling time if RL > 500 Ω. ing output capacitance and load resistor values, and by adequate
bypassing at the supply, reference and VLC terminals. Supplies
Settling time and propagation delay are relatively insensitive to
do not require large electrolytic bypass capacitors as the supply
logic input amplitude and rise and fall times, due to the high
current drain is independent of input logic states; 0.1 µF capaci-
gain of the logic switches. Settling time also remains essentially
tors at the supply pins provide full transient protection.
constant for IREF values. The principal advantage of higher IREF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.

Figure 30. Settling Time Measurement

REV. A –11–
DAC08
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
N-16

0.840 (21.33)
0.745 (18.93)

16 9
0.280 (7.11)

000000000
0.240 (6.10)
1 8 0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
PIN 1 0.060 (1.52) 0.115 (2.93)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381)
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204)
0.014 (0.356) (2.54) 0.045 (1.15) PLANE
BSC

Q-16

0.005 (0.13) MIN 0.080 (2.03) MAX

16 9
0.310 (7.87)
0.220 (5.59)
1 8
0.320 (8.13)
PIN 1
0.290 (7.37)
0.840 (21.34) MAX 0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX 0.150
0.200 (5.08) (3.81)
MIN
0.125 (3.18) 0.015 (0.38)
0.023 (0.58) 0.100 SEATING
0.070 (1.78) PLANE 15° 0.008 (0.20)
0.014 (0.36) (2.54) 0.030 (0.76) 0°
BSC

SO-16

0.3937 (10.00)
0.3859 (9.80)

16 9
0.1574 (4.00) 0.2550 (6.20)
0.1497 (5.80) 1 8 0.2284 (5.80)

PIN 1 0.0688 (1.75) 0.0196 (0.50)

x 45°
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
0.0040 (0.10)

8°
0.0500 0.0192 (0.49) 0°
SEATING (1.27) 0.0099 (0.25) 0.0500 (1.27)
PLANE 0.0138 (0.35)
BSC 0.0075 (0.19) 0.0160 (0.41)

E-20 PRINTED IN U.S.A.

0.200 (5.08)
0.075 BSC
0.358 (9.09) 0.100 (2.54)
(1.91)
0.342 (8.69) 0.064 (1.63) REF 0.100 (2.54) BSC
SQ 0.015 (0.38)
0.095 (2.41) 19 3 MIN
0.075 (1.90) 18 20 4
0.358 0.028 (0.71)
1
TOP (9.09) 0.011 (0.28) 0.022 (0.56)
BOTTOM
VIEW MAX 0.007 (0.18) VIEW
SQ R TYP 0.050 (1.27)
14 8 BSC
0.075 (1.91)
13 9
REF
45° TYP
0.088 (2.24) 0.055 (1.40) 0.150 (3.81)
0.054 (1.37) 0.045 (1.14) BSC

–12– REV. A