Collins C-System C-8561-A2 Processor Notes

The Collins C-8561A-2 Processor is a medium-scale digital computer used in the

C-8500 Computer System.

The C-8561A-2 Processor consists of five major functional sections: arithmetic and
control, communications service, main core storage, processor service, and transfer
links.

The arithmetic and control section consists of the transfer link converter, the
arithmetic logic and control unit, and the algorithm unit (optional). The transfer link
converter transforms the 32-bit data path used by the transfer link into the 16-bit
data paths used by the arithmetic logic and control unit and the algorithm unit.

The computer operates with a clock rate of 8 megahertz; a typical instruction

execution time is 2.9 or 5.6 microseconds, including memory access.

The arithmetic logic and control unit operates into a 32-bit hardware accumulator
called the A accumulator, a 32-bit accumulator in the memory called the B
accumulator, or the combination of both, called the D accumulator.

Three 8724C-1 Transfer Links interconnect the main core storage with the
arithmetic logic and control unit and the communication control group. All
transactions with main core storage take place through the transfer links. To
speed processor operations, the transfer links interleave successive accesses to
memory among the memory units. This is accomplished by storing odd
addresses in one memory unit and even addresses in another. If four memory
units are installed, each transfer link addresses all four units in an odd-even-odd-
even end-around sequence.

The 8712A-3 memory has a 2-μs. cycle time and an access time of 510 ns. It is
expandable from one to four modules. Each module has a capacity of 65,536 bytes,
giving a maximum capacity of 262,144 bytes for one processor. In addition to load
or unload memory cycles, the 8712A-3 has the capability of performing an
unload-modify-Ioad function in one memory cycle.

Each module in the memory has its own address and data buffers. Because of
this, and because each transfer link has the capability of servicing two memory
accesses simultaneously, it is possible for all four modules to operate
concurrently. The ALCU, data channels, processor service unit, and multiplex
service unit may all request the use of the memory independently. If four units
request the access of different memory modules, the entire memory can be in
operation at the same time. The transfer links can perform the four transfers of 32
bits in 2 microseconds.

Communications control group is a general term applied to the input/output and

communication section of the processor. In its simplest form, the
communications control group consists of a data channel or a multiplex service

2017-05-07 – Rev 0 1 of 8
404775729.doc
 Collins C-System C-8561-A2 Processor Notes

unit. In its maximum configuration, the communications control group consists of

five data channels, one multiplex service unit, and an orderwire/absolute time clock unit.
The multiplex service unit controls the time division multiplex loop. This loop provides
multiplex channels far numerous relatively slow-speed devices .of various kinds.
The data channels and the orderwire/absolute time clock units interface with the
Time Division Exchange loop for higher speed communications and input/output
operations.

The time division exchange (TDX) system provides high-speed communication

channels between processors, storage devices, and input/output peripheral
equipment.

The major components .of any time division exchange system are a transmission
line for communication, a loop synchronizer, and terminal units that interface
devices to the communication path.

The loop provides serial communication between terminal units. It physically

consists .of a coaxial cable which is driven and terminated by each device on the
loop. The signal on the currently available loop is a 32-MHz bi-phase modulated
sine wave. Addressing capability exists far directly utilizing a 512 MHz loop.

The data is encoded .one bit per cycle .of carrier. Communication channels are bit
interlaced symmetrically around the group synchronization pulse. Each
channel .of a terminal unit has the capability .of interfacing with a communication
channel .of any .of the following rates: 7.8125, 15.625,31.25, 62.5, 125, 250, 2000,
4000, .or 8000 Kbps.

Because of the transfer link overlap capabilities the data channel is able to
provide communication capability with a minimum of contention with the
arithmetic logic and control unit. Each data channel operates with its own
independent memory and terminal unit interfaces. Each data channel is
capable .of communicating with one other device (storage, input/output, or
processor) on the time division exchange loop. The data rate used for each
communication performed is specified in the device control message to be any
rate in the range 7.8125 Kbps to 8 Mbps.

The 7531A-l orderwire/absolute time clock performs three communication functions;

Orderwire 1, Orderwire 2, and Absolute Time Clock.

The Orderwire 1 channel on the time division exchange loop is an assigned 125
Kbps channel used for communication between processors.

To perform the Orderwire 1 function, the 7531A-l operates in conjunction with data
channel four. Data channel four is initiated only by the Orderwire 1 function which
is in turn initiated in one of two ways. To call another processor, the Orderwire 1
function may be initiated in a manner identical to the way in which a data channel

2017-05-07 – Rev 0 2 of 8
404775729.doc
 Collins C-System C-8561-A2 Processor Notes

is initiated. To receive a call from another processor, the Orderwire 1 function

may be initiated by an incoming call from the Orderwire 1 time division exchange
loop channel. The incoming call, must contain the party line address of the called
Orderwire 1 unit. This party line address is an 8-bit identifier which can be
assigned to the Orderwire unit by software. Once the Orderwire 1 unit has been
initiated, it will initiate the data channel and remain idle until the communication
has completed.

The Orderwire 2 channel on the time division exchange loop is an assigned

7.8125 Kbps channel used for processor-to-operator communication and for the
assignment of peripheral devices to other time division exchange channels for
higher speed communication. When initialized, all peripheral units monitor the
Orderwire 2 channel and accept instructions on that channel to switch to a higher
speed channel for
communication.

To perform the Orderwire 2 function, the 7531A-l operates in conjunction with data
channel three. Data channel three has the option, under control of software, of
performing the normal data channel function and thus inhibiting the Orderwire 2
function or of enabling the Orderwire 2 function in which case it may only be
initiated by the 7531A-1. In Orderwire 2 mode, the Orderwire unit and data
channel three function in a manner essentially identical to the Orderwire 1 unit
and data channel four. The only functional difference is that the Orderwire 2 unit
accepts all incoming calls.

The absolute time clock channel on the time division exchange loop is an
assigned 7.8125 Kbps. Every 1/128 second, a word is transmitted around the loop
which contains time and date information. Each absolute time clock unit which is
on the time division exchange loop will accept this word and store it in a fixed
(strapped) location in memory.

The time division multiplex system provides for the connection of a large number of
low-speed devices to a single computer within the C-8500 C-System on a word,
time-shared basis. The time division multiplex system consists of a serial loop
interconnecting the various devices and terminating at the multiplex service unit,
which connects the loop to main core storage.

The time division multiplex system also includes the multiplex exchange table,
multiplex queues, and a multiplex service program resident in . the main storage of
the processor. The multiplex exchange table, consisting of multiplex status records
and multiplex queues, provides the operational linkage between the end devices
and controlling software in the processor. The multiplex service program
functions as a device independent software interface between time division
multiplex devices and application program subroutines within the computer.
These subroutines control and service the various devices.

2017-05-07 – Rev 0 3 of 8
404775729.doc
 Collins C-System C-8561-A2 Processor Notes

The loop provides the serial communications medium between the multiplex
service unit and all connected devices. It physically consists of a coaxial cable
which is driven by and terminated in the multiplex service unit. The signal on the
loop consists of a 1.2288 MHz bi-phase modulated square-wave where each cycle
corresponds to one bit of data. There are 256 thirty-six bit words transmitted
serially in one frame. These 256 thirty-six bit words are time division addresses and
are identified by their time position relative to a framing pulse.

Each time division address corresponds to a device channel. A working channel is a

normally unidirectional instantaneous communication connection between
hardware and software elements. The framing pulse is generated in
synchronization with the first time division address. Data is inserted into and
extracted from the channels by the multiplex service unit and devices. A device
may be assigned 1, 8, 16, or 32 time division addresses, providing effective channel
bit rates of 4.8 Kbps, 38.4 Kbps, 76.8 Kbps, or 153.6 Kbps.

The multiplex service unit is a hardware device which serves to connect the
multiplex loop to the computer core. It provides all the necessary hardware to
drive and terminate the loop and to interface with processor core storage. It
contains the logic necessary to allow the independent movement of data and
service messages between each device on the loop and data areas in processor
storage. The transactions between the multiplex service unit and each device are
completely under control of it and the multiplex device coupler during record and/or
word transfers once communication between the processor and the device has
been established.

The multiplex device coupler provides a standard interface to devices on the time
division multiplex loop. It performs the function of time division address
recognition, serial extraction and insertion of data into its assigned time division
address channel, and logical interpretation and generation of the supervision
necessary to communicate with the multiplex service unit.

The C-8561A-2 computer has a basic data format of 8-bit bytes and 32-bit words. A
byte can represent a character in some 8-bit code, or a byte can be simply one-
fourth of a 32-bit word. Two bytes make a half-word, and four bytes make a full-
word. In some instances, a double-word of 8 bytes is used.

Main core storage (MCS) is byte addressable, and certain instructions manipulate
bytes or characters. However, MCS is accessed by words, and numerous
instructions manipulate words. Word manipulations provide maximum speed for
arithmetic and data handling operations. Byte manipulations, on the other hand,
provide the ability to operate on variable length data and coded characters.

Words and half-words are referenced (addressed) by the first (leftmost) byte. The
length of the data is implied by the operation.

2017-05-07 – Rev 0 4 of 8
404775729.doc
 Collins C-System C-8561-A2 Processor Notes

Words, half-words, and bytes must be properly aligned. Even addresses are half-word
boundaries, and addresses divisible by four are word and double-word
boundaries. All addresses are byte boundaries.

Protected memory is an area in main core storage that cannot be altered unless
the processor is operating in privileged mode. The protected area includes at
least the first 512 word locations (00000 through 007FF in hexadecimal). It can be
expanded in modules of 512 words up to 16,384 words.

Collins C-System

2017-05-07 – Rev 0 5 of 8
404775729.doc
Collins C-System C-8561-A2 Processor Notes

2017-05-07 – Rev 0 6 of 8
404775729.doc
Collins C-System C-8561-A2 Processor Notes

C-8561-A2 ALCU

Communications Service Unit

2017-05-07 – Rev 0 7 of 8
404775729.doc
Collins C-System C-8561-A2 Processor Notes

Typical C-System center configuration

2017-05-07 – Rev 0 8 of 8
404775729.doc