NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM

July 1998

NM27C256
262,144-Bit (32K x 8) High Performance CMOS EPROM

General Description The NM27C256 is one member of a high density EPROM Family
which range in densities up to 4 Mb.
The NM27C256 is a 256K Electrically Programmable Read Only
Memory. It is manufactured in Fairchild’s latest CMOS split gate Features
EPROM technology which enables it to operate at speeds as fast
as 90 ns access time over the full operating range. ■ High performance CMOS
— 90 ns access time
The NM27C256 provides microprocessor-based systems exten-
■ JEDEC standard pin configuration
sive storage capacity for large portions of operating system and
— 28-pin PDIP package
application software. Its 90 ns access time provides high speed
— 32-pin chip carrier
operation with high-performance CPUs. The NM27C256 offers a
— 28-pin CERDIP package
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines ■ Drop-in replacement for 27C256 or 27256
are quickly executed from EPROM storage, greatly enhancing ■ Manufacturer’s identification code
system utility.
The NM27C256 is configured in the standard EPROM pinout
which provides an easy upgrade path for systems which are
currently using standard EPROMs.

Block Diagram Data Outputs O0 - O7

VCC
GND
VPP

OE
Output Enable
and Chip Enable Logic Output
CE/PGM
Buffers

Y Decoder
..

Y Gating
A0 - A14
Address
Inputs
.......

X Decoder

DS010833-1

© 1998 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com

 NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Connection Diagrams
27C080 27C040 27C020 27C010 27C512 27C512 27C010 27C020 27C040 27C080
A19 XX/VPP XX/VPP XX/VPP
DlP
VCC VCC VCC VCC
NM27C256
A16 A16 A16 A16 XX/PGM XX/PGM A18 A18
A15 A15 A15 A15 A15 VPP 1 28 VCC VCC XX A17 A17 A17
A12 A12 A12 A12 A12 A12 2 27 A14 A14 A14 A14 A14 A14
A7 A7 A7 A7 A7 A7 3 26 A13 A13 A13 A13 A13 A13
A6 A6 A6 A6 A6 A6 4 25 A8 A8 A8 A8 A8 A8
A5 A5 A5 A5 A5 A5 5 24 A9 A9 A9 A9 A9 A9
A4 A4 A4 A4 A4 A4 6 23 A11 A11 A11 A11 A11 A11
A3 A3 A3 A3 A3 A3 7 22 OE OE/VPP OE OE OE OE/VPP
A2 A2 A2 A2 A2 A2 8 21 A10 A10 A10 A10 A10 A10
A1 A1 A1 A1 A1 A1 9 20 CE/PGM CE/PGM CE CE CE/PGM CE/PGM
A0 A0 A0 A0 A0 A0 10 19 O7 O7 O7 O7 O7 O7
O0 O0 O0 O0 O0 O0 11 18 O6 O6 O6 O6 O6 O6
O1 O1 O1 O1 O1 O1 12 17 O5 O5 O5 O5 O5 O5
O2 O2 O2 O2 O2 O2 13 16 O4 O4 O4 O4 O4 O4
GND GND GND GND GND GND 14 15 O3 O3 O3 O3 O3 O3

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C256 pins. DS010833-2

Commercial Temp. Range (0°C to +70°C) Pin Names

VCC = 5V ±10%
Symbol Description
Parameter/Order Number Access Time (ns) A0–A14 Addresses
NM27C256 Q, N, V 90 90 CE/PGM Chip Enable/Program
NM27C256 Q, N, V 100 100 OE Output Enable
NM27C256 Q, N, V 120 120 O0–O7 Outputs
NM27C256 Q, N, V 150 150 XX Don’t Care (during Read)
NM27C256 Q, N, V 200 200
PLCC
Extended Temp. Range (-40°C to +85°C)
VCC
VPP
A12

A14
A13
VCC = 5V ±10%
XX
A7

Parameter/Order Number Access Time (ns)

4 3 2 1 32 31 30
NM27C256 QE, NE, VE 120 120
NM27C256 QE, NE, VE 150 150 A6 5 29 A8
NM27C256 QE, NE, VE 200 200 A5 6 28 A9
A4 7 27 A11
Note: Surface mount PLCC package available for commercial and extended A3 8 26 XX
temperature ranges only.
A2 9 25 OE
Package Types: NM27C256 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP A1 10 24 A10
N = Plastic OTP DIP A0 11 23 CE/PGM
V = Surface-Mount PLCC XX 12 22 O7
• All Packages conform to the JEDEC standard. O0 13 21 O6
14 15 16 17 18 19 20
• All versions are guaranteed to function for slower speeds.
O1
O2
GND
XX
O3
O4
O5

DS010833-3

Top

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 NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings (Note 1) ESD Protection > 2000V

Storage Temperature -65°C to +150°C All Output Voltages with

Respect to Ground VCC + 1.0V to GND -0.6V
All Input Voltages except A9 with
Respect to Ground -0.6V to +7V Operating Range
VPP and A9 with Respect
to Ground -0.7V to +14V
Range Temperature VCC
Comm’l 0°C to +70°C +5V ±10%
VCC Supply Voltage with
Respect to Ground -0.6V to +7V Industrial -40°C to +85°C +5V ±10%

Read Operation
DC Electrical Characteristics Over Operating Range with VPP = VCC
Symbol Parameter Test Conditions Min Max Units
VIL Input Low Level -0.5 0.8 V
VIH Input High Level 2.0 VCC +1 V
VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Output High Voltage IOH = -2.5 mA 3.5 V
ISB1 VCC Standby Current CE = VCC ±0.3V 100 µA
(Note 11) (CMOS)
ISB2 VCC Standby Current (TTL) CE = VIH 1 mA
ICC1 VCC Active Current CE = OE = VIL,f=5 MHz 35 mA
TTL Inputs Inputs = VIH or VIL, I/O = 0 mA
IPP VPP Supply Current VPP = VCC 10 µA
VPP VPP Read Voltage VCC - 0.7 VCC V
ILI Input Load Current VIN = 5.5V or GND -1 1 µA
ILO Output Leakage Current VOUT = 5.5V or GND -10 10 µA

AC Electrical Characteristics Over Operating Range with VPP = VCC

Symbol Parameter 90 100 120 150 200 Units
Min Max Min Max Min Max Min Max Min Max
tACC Address to Output Delay 90 100 120 150 200 ns
tCE CE to Output Delay 90 100 120 150 200
tOE OE to Output Delay 35 50 50 50 50
tDF Output Disable to 30 30 35 45 45
(Note 2) Output Float
tOH Output Hold from 0 0 0 0 0
(Note 2) Addresses,
CE or OE, Whichever
Occurred First

Capacitance (Note 2) TA = +25˚C, f = 1 MHz

Symbol Parameter Conditions Typ Max Units
CIN Input Capacitance VIN = 0V 6 12 pF
COUT Output Capacitance VOUT = 0V 9 12 pF

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 NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times ≤ 5 ns
Input Pulse Levels 0.45 to 2.4V
Timing Measurement Reference Level (Note 10)
Inputs 0.8V and 2.0V
Outputs 0.8V and 2.0V

AC Waveforms (Note 6) (Note 7) (Note 9)

2.0V
ADDRESSES ADDRESSES VALID
0.8V

2.0V
CE
0.8V
tCE tCE
(Notes 4, 5)

2.0V
OE
0.8V
tOE
(Note 3)
tDF
(Notes 4, 5)

OUTPUT 2.0V Hi-Z Hi-Z

VALID OUTPUT
0.8V
tACC tOH
(Note 3)
DS010833-4

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL = 100 pF includes fixture capacitance.
Note 9: VPP may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 11: CMOS inputs: VIL = GND ±0.3V, V IH = VCC ±0.3V.

Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15)
Symbol Parameter Conditions Min Typ Max Units

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 NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15) (Continued)
Symbol Parameter Conditions Min Typ Max Units
tAS Address Setup Time 1 µs
tOES OE Setup Time 1 µs
tVPS VPP Setup Time 1 µs
tVCS VCC Setup Time 1 µs
tDS Data Setup Time 1 µs
tAH Address Hold Time 0 µs
tDH Data Hold Time 1 µs
tDF Output Enable to Output CE = VIL 0 60 ns
Float Delay
tPW Program Pulse Width 45 50 105 µs
tOE Data Valid from OE CE = VIL 100 ns
IPP VPP Supply Current CE = VIL 30 mA
during Programming Pulse
ICC VCC Supply Current 50 mA
TA Temperature Ambient 20 25 30 °C
VCC Power Supply Voltage 6.25 6.5 6.75 V
VPP Programming Supply Voltage 12.5 12.75 13.0 V
tFR Input Rise, Fall Time 5 ns
VIL Input Low Voltage 0.0 0.45 V
VIH Input High Voltage 2.4 4.0 V
tIN Input Timing Reference Voltage 0.8 2.0 V
tOUT Output Timing Reference Voltage 0.8 2.0 V

Programming Waveforms (Note 14)

PROGRAM
PROGRAM VERIFY

2.0V
ADDRESSES ADDRESS N
0.8V
tAS tAH

2.0V DATA IN STABLE DATA OUT VALID

DATA 0.8V ADD N ADD N
tDS tDH
tDF

VCC 5.25V
tVCS

VPP 12.75V

tVPS

2.0V
CE 0.8V
tOES tOE
tPW

2.0V
OE 0.8V

DS010833-5

Note 12: Fairchild’s standard product warranty applies to devices programmed to specifications described herein.
Note 13: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 14: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 15: During power up the PGM pin must be brought high (≥ VIH) either coincident with or before power is applied to VPP.

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 NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V
n=0
ADDRESS = FIRST LOCATION

PROGRAM ONE 50µs PULSE

INCREMENT n

NO

DEVICE YES
n = 10? FAIL VERIFY
FAILED BYTE

PASS

LAST INCREMENT
NO
ADDRESS ADDRESS
? n=0
YES

ADDRESS = FIRST LOCATION

VERIFY FAIL
BYTE

PASS PROGRAM ONE

INCREMENT
50 µs
ADDRESS
PULSE

NO
LAST
ADDRESS
?
YES

CHECK ALL BYTES

1ST: VCC = VPP = 6.0V
2ND: VCC = VPP = 4.3V

Note: The standard National Semiconductor algorithm may also be used but it will have longer programming time.
DS010833-6

FIGURE 1.

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 NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Functional Description The EPROM is in the programming mode when the VPP power
supply is at 12.75V and OE is at VIH. It is required that at least a
DEVICE OPERATION 0.1 µF capacitor be placed across VPP, VCC to ground to suppress
spurious voltage transients which may damage the device. The
The six modes of operation of the EPROM are listed in Table 1. It
data to be programmed is applied 8 bits in parallel to the data
should be noted that all inputs for the six modes are at TTL levels.
output pins. The levels required for the address and data inputs
The power supplies required are VCC and VPP. The VPP power
are TTL.
supply must be at 12.75V during the three programming modes,
and must be at 5V in the other three modes. The VCC power supply When the address and data are stable, an active low, TTL program
must be at 6.5V during the three programming modes, and at 5V pulse is applied to the CE/PGM input. A program pulse must be
in the other three modes. applied at each address location to be programmed. The EPROM
is programmed with the Turbo Programming Algorithm shown in
Read Mode Figure 1. Each Address is programmed with a series of 50 µs
The EPROM has two control functions, both of which must be pulses until it verifies good, up to a maximum of 10 pulses. Most
logically active in order to obtain data at the outputs. Chip Enable memory cells will program with a single 50 µs pulse. (The standard
(CE/PGM) is the power control and should be used for device National Semiconductor Algorithm may also be used but it will
selection. Output Enable (OE) is the output control and should be have longer programming time.)
used to gate data to the output pins, independent of device
The EPROM must not be programmed with a DC signal applied to
selection. Assuming that addresses are stable, address access
the CE/PGM input.
time (tACC) is equal to the delay from CE to output (tCE). Data is
available at the outputs tOE after the falling edge of OE, assuming Programming multiple EPROM in parallel with the same data can
that CE/PGM has been low and addresses have been stable for be easily accomplished due to the simplicity of the programming
at least tACC –tOE. requirments. Like inputs of the parallel EPROM may be connected
together when they are programmed with the same data. A low
Standby Mode level TTL pulse applied to the CE/PGM input programs the
The EPROM has a standby mode which reduces the active power paralleled EPROM.
dissipation by over 99%, from 385 mW to 0.55 mW. The EPROM
is placed in the standby mode by applying a CMOS high signal to
Program Inhibit
the CE/PGM input. When in standby mode, the outputs are in a Programming multiple EPROMs in parallel with different data is
high impedance state, independent of the OE input. also easily accomplished. Except for CE/PGM, all like inputs
(including OE) of the parallel EPROMs may be common. A TTL
Output Disable low level program pulse applied to an EPROM’s CE/PGM input
The EPROM is placed in output disable by applying a TTL high with VPP at 12.75V will program that EPROM. A TTL high level CE/
signal to the OE input. When in output disable all circuitry is PGM input inhibits the other EPROMs from being programmed.
enabled, except the outputs are in a high impedance state (TRI-
STATE).
Program Verify
A verify should be performed on the programmed bits to determine
Output OR-Typing whether they were correctly programmed. The verify may be
Because the EPROM is usually used in larger memory arrays, performed with VPP at 12.75V. VPP must be at VCC, except during
Fairchild has provided a 2-line control function that accommo- programming and program verify.
dates this use of multiple memory connections. The 2-line control
function allows for:
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window to
1. the lowest possible memory power dissipation, and
prevent unintentional erasure. Covering the window will also
2. complete assurance that output bus contention will not prevent temporary functional failure due to the generation of photo
occur. currents.
To most efficiently use these two control lines, it is recommended
that CE/PGM be decoded and used as the primary device select- MANUFACTURER’S IDENTIFICATION CODE
ing function, while OE be made a common connection to all The EPROM has a manufacturer’s identification code to aid in
devices in the array and connected to the READ line from the programming. When the device is inserted in an EPROM pro-
system control bus. This assures that all deselected memory grammer socket, the programmer reads the code and then
devices are in their low power standby modes and that the output automatically calls up the specific programming algorithm for the
pins are active only when data is desired from a particular memory part. This automatic programming control is only possible with
device. programmers which have the capability of reading the code.

Programming The Manufacturer’s Identification code, shown in Table 2, specifi-

cally identifies the manufacturer and device type. The code for
CAUTION: Exceeding 14V on pin 1 (VPP) will damage the EPROM.
NM27C256 is “8F04”, where “8F” designates that it is made by
Initially, and after each erasure, all bits of the EPROM are in the Fairchild Semiconductor, and “04” designates a 256K part.
“1’s” state. Data is introduced by selectively programming “0’s”
The code is accessed by applying 12V ±0.5V to address pin A9.
into the desired bit locations. Although only “0’s” will be pro-
Addresses A1–A8, A10–A16, and all control pins are held at VIL.
grammed, both “1’s” and “0’s” can be presented in the data word.
Address pin A0 is held at VIL for the manufacturer’s code, and held
The only way to change a “0” to a “1” is by ultraviolet light erasure.
at VIH for the device code. The code is read on the eight data pins,
O0 –O7. Proper code access is only guaranteed at 25°C to ±5°C.

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 NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Functional Description (Continued) be checked to make certain full erasure is occurring. Incomplete
erasure will cause symptoms that can be misleading. Program-
ERASURE CHARACTERISTICS mers, components, and even system designs have been errone-
ously suspected when incomplete erasure was the problem.
The erasure characteristics of the device are such that erasure
begins to occur when exposed to light with wavelengths shorter SYSTEM CONSIDERATION
than approximately 4000 Angstroms (Å). It should be noted that
sunlight and certain types of fluorescent lamps have wavelengths The power switching characteristics of EPROMs require careful
in the 3000Å–4000Å range. decoupling of the devices. The supply current, ICC, has three
segments that are of interest to the system designer: the standby
The recommended erasure procedure for the EPROM is expo- current level, the active current level, and the transient current
sure to short wave ultraviolet light which has a wavelength of peaks that are produced by voltage transitions on input pins. The
2537Å. The integrated dose (i.e., UV intensity x exposure time) for magnitude of these transient current peaks is dependent of the
erasure should be a minimum of 15W-sec/cm2 . output capacitance loading of the device. The associated VCC
transient voltage peaks can be suppressed by properly selected
The EPROM should be placed within 1 inch of the lamp tubes
decoupling capacitors. It is recommended that at least a 0.1 µF
during erasure. Some lamps have a filter on their tubes which
ceramic capacitor be used on every device between VCC and
should be removed before erasure
GND. This should be a high frequency capacitor of low inherent
An erasure system should be calibrated periodically. The distance inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor
from lamp to device should be maintained at one inch. The erasure should be used between VCC and GND for each eight devices. The
time increases as the square of the distance from the lamp (if bulk capacitor should be located near where the power supply is
distance is doubled the erasure time increases by factor of 4). connected to the array. The purpose of the bulk capacitor is to
Lamps lose intensity as they age. When a lamp is changed, the overcome the voltage drop caused by the inductive effects of the
distance has changed, or the lamp has aged, the system should PC board traces.

Mode Selection
The modes of operation of NM27C256 listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels
except for VPP and A9 for device signature.

TABLE 1. Modes Selection

Pins CE/PGM OE VPP VCC Outputs
Mode
Read VIL VIL VCC 5.0V DOUT
Output Disable X VIH VCC 5.0V High-Z
(Note 16)
Standby VIH X VCC 5.0V High-Z
Programming VIL VIH 12.75V 6.25V DIN
Program Verify VIH VIL 12.75V 6.25V DOUT
Program Inhibit VIH VIH 12.75V 6.25V High-Z
Note 16: X can be VIL or VIH.

TABLE 2. Manufacturer’s Identification Code

Pins A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex
(10) (24) (19) (18) (17) (16) (15) (13) (12) (11) Data
Manufacturer Code VIL 12V 1 0 0 0 1 1 1 1 8F
Device Code VIH 12V 0 0 0 0 0 1 0 0 04

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 NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.450
[36.83]
MAX
28 15

R 0.025
[0.64]
0.520 ± 0.006
0.600
[13.21 ±0.15]
[15.24]
MAX
Glass

1 14
0.280 ±0.010
R 0.030-0.055 [7.11 ±0.25]
[0.76 - 1.40] UV WINDOW
TYP

0.050-0.060
TYP Glass 0.590-0.620
0.005 MIN
TYP Sealant [14.99 - 15.75]

0.175
0.225 MAX TYP MAX

0.125 MIN
0.015 -0.060 95° ±5° 0.010 ±0.002
TYP TYP
TYP TYP [0.25 ±0.05]
86°-94°
TYP 0.150 MIN
TYP
0.060-0.1000.090-0.110 0.015-0.021 +0.025
TYP 0.685
TYP TYP -0.060
+0.64
17.40
-1.52

UV Window Cavity Dual-In-Line CerDIP Package (Q)

Order Number NM27C256QXXX
Package Number J28AQ

28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.030
Max
(0.762) 0.600 - 0.620 0.062 RAD
(15.24 - 15.75) 0.510 ±0.005 (1.575)
(12.95 ±0.127)

95° ±5°
0.008-0.015 Pin #1 1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.580 (0.229-0.381) IDENT
(14.73) 1.393 - 1.420
(35.38 - 36.07)
+0.025
0.625 -0.015

(15.88 +0.635
-0.381 ( 0.050
(1.270)
Typ
0.053 - 0.069
0.125-0.165
(1.346 - 1.753)
(3.175-4.191) 0.20 Min
(0.508)

88° 94°
0.108 ±0.010 Typ 0.125-0.145
0.050 ±0.015
(2.540 ±0.254) (3.175-3.583)
(1.270 ±0.381) 0.018 ±0.003
(0.457 ±0.076)

28-Lead Plastic One-Time-Programmable Dual-In-Line Package

Order Number NM27C256NXXX
Package Number N28B

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 NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.485-0.495
[12.32-12.57]
-H-
0.106-0.112 Base
0.007[0.18] S B D-E S [2.69-2.84] Plane

0.449-0.453 0.023-0.029
[11.40-11.51] [0.58-0.74] 0.015
-A- [0.38] Min Typ
0.045 0.007[0.18] S B D-E S
[1.143]

°
60
0.000-0.010 0.002[0.05] S B
[0.00-0.25] 0.490-0530
-D- 0.400
Polished Optional ( [10.16] ) [12.45-13.46]
4 1 30
0.541-0.545 0.015[0.38] S C D-E, F-G S
[13.74-13-84]
5 29

0.549-0.553
[13.94-14.05] -G-
-B-

0.585-0.595
[14.86-15.11] 0.013-0.021
TYP
-F- [0.33-0.53]
See detail A
-J- 0.007[0.18] M C D-E, F-G S
13
21
0.078-0.095
0.123-0.140 [1.98-2.41]
14 20 0.050

,,
[3.12-3.56]
-E- -C-
0.002[0.05] S A
0.004[0.10] 0.005 Max
0.007[0.18] S A F-G S
0.020 [0.13] 0.0100
0.007[0.18] S A F-G S [0.51] [0.254]

0.118-0.129
0.045
[3.00-3.28]
[1.14]
0.010[0.25] L B A D-E, F-G S 0.025 0.030-0.040
[0.64] Min
Detail A R
[0.76-1.02]
B 0.042-0.048 Typical
45°X [1.07-1.22] 0.025
0.021-0.027 Rotated 90°
[0.64]
[0.53-0.69]
Min

B
0.065-0.071
[1.65-1.80]

0.053-0.059
[1.65-1.80]

0.031-0.037
0.006-0.012 [0.79-0.94]
[0.15-0.30]
0.027-0.033
0.026-0.032 0.019-0.025 [0.69-0.84]
Typ
[0.66-0.81] [0.48-0.64]

0.007[0.18] S H D-E, F-G S Section B-B

Typical

32-Lead Plastic Leaded Chip Carrier (PLCC)

Order Number NM27C256VXXX
Package Number VA32A

10 www.fairchildsemi.com
 Life Support Policy NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, 2. A critical component is any component of a life support device
(a) are intended for surgical implant into the body, or (b) support or system whose failure to perform can be reasonably ex-
or sustain life, and whose failure to perform, when properly pected to cause the failure of the life support device or system,
used in accordance with instructions for use provided in the or to affect its safety or effectiveness.
labeling, can be reasonably expected to result in a significant
injury to the user.

Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor

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Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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