Research Journal of Applied Sciences, Engineering and Technology 4(4): 342-349, 2012

ISSN: 2040-7467
© Maxwell Scientific Organization, 2012
Submitted: August 26, 2011 Accepted: October 07, 2011 Published: February 15, 2012

Design and Robustness Analysis of a PID Based Sliding Mode Controller

for a dc-dc Converter
1
D.M. Mary Synthia Regis Prabha, 2S. Pushpa Kumar and 1G. Glan Devadhas
1
PRIST University, Thanjavur
2
Heera College of Engineering and Technology, Nedumancadu, Trivandrum

Abstract: This study deals with the design and analysis of a dc-dc converter operating in continuous conduction
mode with Proportional-Integral-Derivative control and PID based Sliding Mode Control (SMC). A small signal
model is developed using Switching Flow Graph (SFG) from which the control coefficients for the PID
controller is selected. PID based SMC uses a control law which constrains the weighted sum of the voltage
error, its derivatives and the integral of the voltage error to zero. The equivalent control technique is used in
its design which makes the converter more suitable for fixed frequency operation. Sensitivity of these
controllers to supply voltage disturbances and load disturbances is studied and results are presented.

Key words: dc-dc converter, PID based SMC, PID control, switching flow graph

INTRODUCTION Modulation (PWM) for the controller. In this paper this

technique has been demonstrated for a Buck Converter.
Switching mode dc-dc converters are widely used PID control and PID based SMC are two different
today in a variety of applications including power control techniques considered in this paper. PID control
supplies for personal computers, mission critical space is a traditional linear control, while SMC is a type of non-
applications, laptop computers, dc motor drives, medical linear control. Linear PID controllers for dc-dc converters
electronics as well as high power transmission. These are usually designed by classical frequency response
converters are non-linear dynamical systems. The non- techniques applied to the small-signal models of
linearities arise primarily due to switching, power converters (Liping et al., 2009). A bode plot is adjusted in
devicesand passive components such as inductors and the design to obtain the desired loop gain, cross-over
capacitors. frequency and phase margin. The transient response can
A control technique suitable for dc-dc converters be tuned using root locus type approaches (Prodic and
must cope with their intrinsic non-linearity and wide input Maksimovic, 2002). The stability of the system is
voltage and load variations ensuring stability in any guaranteed by an adequate phase margin. PID control is
operating condition while providing fast transient typically designed for one nominal operating point (Perry
response. Among the various control techniques available, et al., 2007). For a buck converter, the magnitude of the
sliding mode control offers several advantages, namely frequency response depends on the duty cycle. Duty cycle
large signal stability, robustness, good dynamic response variations do not change the shape of the magnitude plot
and simple implementation. The design of a SMC does of the transfer function, but only shifts the plot upward
not require an accurate model of the system. The ideal (Siew et al., 2008). Therefore, a PID controller may not
nature of the controller is to operate at an infinite respond well to significant changes in operating points.
switching. This nature enables the controlled variable to In this study, the problem of PID based quasi sliding
track a certain reference path to achieve the desired mode control of a Buck Converter is discussed. The
dynamic response and better steady state operation (Duan design of a PID controller for a dc-dc converter is
and Jin, 1999). This extreme high frequency operation discussed in detail. Finally, comparison of these two
results in excessive switch losses and Electromagnetic methods is performed in order to verify the dynamic and
Interference (EMI) noise issues. In addition sliding mode steady state responses and their robustness to sudden line
control also exhibits steady state error for the output variations.
voltage. Hence, for sliding mode controllers to be
applicable for dc-dc power converters, it becomes SYSTEM MODELING
essential to constrict the switching frequency within a
practical range. Moreover, variable switching frequency Linear controllers for dc-dc converters are often
is undesirable for power converters. A method of ensuring designed based on mathematical models. The most
constant switching frequency is to employ Pulse Width commonly used technique for modeling linear

Corresponding Author: D.M. Mary, Synthia Regis Prabha, Associate Professor, Noor ul Islam University, Kumaracoil
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 Res. J. Appl. Sci. Eng. Technol., 4(4): 342-349, 2012

Fig. 1: Buck converter

Fig. 2: On-state switching flow graph

Fig. 3: Off-State switching flow graph

Fig. 4: SFG of buck converter

controllers is the traditional state space averaging method. A small signal model takes a circuit and based on an
The major drawback of this method is that the linearized operating point (bias) and linearizes all the components.
models obtained through averaging process, do not Nothing changes because the assumption is that the signal
predict the large-signal stability information, and are only is so small that the operating point (gain, capacitance etc.)
sufficient to predict small-signal stability. doesn't change. A large signal model on the other hand

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 Res. J. Appl. Sci. Eng. Technol., 4(4): 342-349, 2012

takes into account the fact that the large signal actually Table 1: Prototype Buck Converter circuit parameters
affects the operating point and takes into account that Parameter Value Units
Input voltage, Vi 24 V
elements are non-linear and that circuits can be limited by Desired output voltage, Vod 12 V
power supply values. A small signal model ignores supply Load resistance, Ro 6 S
values. Filter inductance, L 35 :H
Filter capacitance, C 150 :F
Graphical Analysis Method (GAM): This is a ESR of inductor, RL 0.12 S
ESR of capacitor, RC 0.03 S
non-linear modeling method. This is developed for
pulse-width modulated converters. The GAM converts the
switching converter, even the multistate converter the filter capacitance C (Perry et al., 2007). The cut-off
frequency of the second order low pass filter is TC
=1/%LC Variations of D, varies the magnitude of the
systems, into a unified dynamic model. From unified
model, it is possible to derive large, small signal and
steady state models with mathematical manipulations. transfer function. Moreover, it does not change the shape
Each system can be represented by a flow graph. The of the frequency response, but shifts the magnitude plot
switching flow graph is obtained by combining the flow upward or downward.
graphs of the subsystems through the use of switching Table 1 gives the circuit parameters of the prototype
branches (Mummadi, 2004). The switching flow graph Buck Converter selected for experimentation. The
model is easy to derive, and it provides a visual nominal operating point of the prototype Buck converter
representation of a switching converter system. is chosen as follows: Input Voltage, Vi = 24 V, Desired
Buck converter shown in Fig. 1 has two modes of Output Voltage, Vod = 12 V, Duty ratio D = 0.5.
operation: (i) Switch is on (ii) Switch is off. The circuit Small signal control to output transfer function at this
diagram of the Buck converter is shown below. nominal operating point is given as:
The switching flow graph is drawn for the on-state
sub-circuit and the off-state sub-circuit which is shown in
Fig. 2 and 3, respectively. These two sub-circuits are V$0 ( s) ⎡ 24 + 10.8e − 4 s ⎤
$ =⎢ −4 −9 2 ⎥ (3)
combined together which gives the switching flow graph d ( s) ⎢⎣ 1 + 5817
. e s + 4.243 e s ⎥⎦
of the Buck converter which is shown in Fig. 4.

Derivation of small-signal model using switching flow Small Signal Input to Output transfer function at this
graph: Small signal control to output transfer function is nominal operating point is given as:
derived as:
V$0 ( s) ⎡ 1 + 45.39 e − 4 s ⎤
V$0 ( s) V0 $ = ⎢ 2⎥ (4)
= Vin ( s) ⎢⎣ 235.65e + 137 e s + s ⎥⎦
6 3
d$( s) D
⎡ ⎤
⎢ ⎥ (1)
⎢ 1 + sRC C ⎥
⎢
Design of PID controller for a buck converter: The
⎛ RL RO L ⎞ ⎛ RO + RC ⎞ ⎥
⎢ 1 + s⎜ RC C + C+ ⎟ + s LC⎜
2
⎟⎥ open loop transfer function G(S) H(s) of the Buck
⎢⎣ ⎝ RL + RO RL + RO ⎠ ⎝ RO + RL ⎠ ⎥⎦
converter is given by Eq. (3). A PID compensator is
designed with a phase margin of 45º at a cross-over
Small Signal Input to Output transfer function is derived frequency of 125.66 kHz. The steady state error for unit
as: ramp input is considered to be 0.035%. The PID
controller has a transfer function of GC(S) = KP+ Kis
V$0 ( s) DR0 +Kds. Ki is decided by steady state requirements. Once we
=
V$in ( s) ( R0 + RL ) know KI , we can find out KP and Kd, Eq. (5) and (6).
⎡ ⎤
⎢ ⎥ (2)
⎢ 1 + sRC C ⎥ sin θ
⎢ Kp = (5)
⎛ RL R0 L ⎞ ⎛ R0 + RC ⎞ ⎥ | G( jω ) H ( jω )|
⎢ 1 + s⎜ RC C + C+ ⎟ + S LC⎜
2
⎟⎥
⎢⎣ ⎝ RL + R0 RL + R0 ⎠ ⎝ R0 + RL ⎠ ⎥⎦

Ki − ω cosθ
In this transfer function, VO is the output voltage, D Kd = (6)
ω 2 |G ( jω ) H ( jω )|
is the duty cycle, C is the output capacitance, L is the
inductance and R is the load resistance. RL and RC are the
Equivalent Series Resistance (ESR) of L and C, where, tan 2 = Kp T/Ki T2 Kd. The KP, Ki and Kd values
respectively. This transfer function is a second order low are found to be 5.80125, 119.048 and 0.0869×10G4,
pass filter, with a left-half-plane introduced by the ESR of respectively.

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 Res. J. Appl. Sci. Eng. Technol., 4(4): 342-349, 2012

Design of a sliding mode controller: has a form similar to a PID (Proportional, Integral
C Step 1: Determination of the state variables: The and Derivative) controller. Third, it contained a form
output voltage error decay is essentially the main of state-feedback which provides a more flexible way
control objective in real time. The selected state to close the feedback loop to obtain any type of
variables are output voltage error, output voltage responses at will.
error dynamics and the integral of the error of the C Step 4: Ensure existence of sliding mode operation:
output capacitor (Utkin et al., 1999): The local reachability condition lims÷0 + s.Ñ < 0,
must be satisfied. This is expressed as:
⎡V − βV ⎤
⎢ ref O ⎥
⎢d ⎥ S& = K T Ax + K T BU <0
s→ 0 + s→ 0 +
X = ⎢ (Vref − βVO ) ⎥
⎢ dt ⎥ S& = K T Ax + K T BU <0
⎢ ⎥ s→ 0 − s→ 0 −
⎢⎣ ∫
( Vref − βVO ) dt ⎥⎦
C Step 5: Derivation of existence condition:
C Step 2: Develop the state variables: B For S ÷ 0+ and Ð < 0 and âs ÷ 0+ = 0, we get:

⎡ x&1 ⎤ ⎡ 0
⎢ ⎥ ⎢
1
− ( L + CR0 RL )
0⎤
⎥
⎡ x1 ⎤
⎢ ⎥ [V ref ]
− β VO LC −
α1
α2
β Lic
⎢ x&2 ⎥ = ⎢ 0 0⎥ ⎢ x2 ⎥ (9)
⎢⎣ x&3 ⎥⎦ ⎢ ⎥
LCRO
⎢⎣ x3 ⎥⎦ ( L + CRO RL ) βV0 ( R0 − RL )
⎢⎣ 1 0 0⎥⎦ + β ic + >0
CR0 R0
⎡ 0 ⎤ ⎡ 0 ⎤
⎢ − βV ⎥ ⎢ ⎥
β V ( R − RL ) ⎥
+⎢ i⎥
u+ ⎢ 0 O B For S ÷ 0G0 and Ð > 0 and âs ÷ 0G = 1, we get:
⎢ LC ⎥ ⎢ LCR0 ⎥
⎢ 0 ⎥ ⎢ ⎥
α α
⎣ ⎦ ⎢⎣ 0 ⎥⎦
[ ]
β Vi > 3 Vref − βVo LC − 1 β LiC
α2 α2
(10)
C Step 3: Define the switching status and sliding ( L + CRO RL ) β V ( R − RL )
+ β ic + 0 0
equation: CR0 R0

⎧1, when S > 0 The simplified existence condition in Eq. (10) is

u= ⎨ obtained by combining both Eq. (8) and (9):
⎩ 0, when S < 0

α3 α
0< [V − βVO ]LC − 1 βLiC
where ‘S’ is the instantaneous state variables α 2 ref α2
trajectory. (11)
( L + CRO RL ) βV ( R − RL )
+ βiC + 0 0 < βVi
CR0 R0
d (Vref − β VO )
S = Kd + K p (Vref − β VO )
dt The condition given in Eq. (10) provides a range of
T (7) employable sliding surface coefficients such that
∫
+ Ki (Vref − Vo )dt irrespective of the circuit parameters, the system
O trajectories near the surface are directed towards the
sliding surface itself.
S = a1x1 + a2 x2 + a3 x3 = K T x (8) Considering the design parameters, the existence
condition is modified. From the left inequality of the
where "1, "2 and "3 are sliding coefficients with KT = existence condition, we get:
["1 "2 "3].
α3 ( R − RL )
This Eq. (7) has three significant implications. First, LC (V − βVo ) + βVo O
α1 α 2 ref RO
this control law states that not only the weighted sum <
of voltage error and its derivative needs to be α2 βLic (12)
constrained to be zero but also the integral of the ⎡ 1 R ⎤
+⎢ + L⎥
voltage error must be included. Secondly, the Eq. (7) ⎣ O
CR L ⎦

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From the left inequality of the existence, we get:

1.00

a3 ( R − RL ) 0.98
βVi − LC (V − βVo ) − βVo o
a1 a2 ref Ro
< 0.96
a2 βLiC (13) 0.94
⎡ 1 RL ⎤
+⎢ + ⎥ 0.92
⎣ CRO L ⎦
0.90

0.88
Dividing Eq. (11) and (12): 0 5 10 15 20 25 30 35
Load Ro (Ω)

⎧ ⎡ R ⎤ α ⎡ Vref ⎤⎫ Fig. 5: Plot between Ro and 83

⎪Vo ⎢1 − L ⎥ + 3 ⎢ − Vo ⎥ ⎪
⎪ Ro ⎦ α 2 ⎣ β ⎦⎪
Vi = 2⎨ ⎣
17.6
⎬ (14) 17.4
⎪ LC − LiC − i R ⎪ 17.2
⎪ C L ⎪
⎩ CRo ⎭ 17.0
16.8
16.6
16.4
The range of input and loading conditions is 16.2
considered and the modified existence condition is 16.0
given as: 15.8
15.6
0 5 10 15 20 25 30 35
α ⎛ Vref ⎞ ⎛ RL ⎞ Load Ro ( Ω)
LC 3 ⎜ −Vo ⎟ +Vo ⎜⎜1− ⎟
⎟
α1 α2 ⎝ β ⎠ ⎝ Ro(max) ⎠ ⎡ 1 R ⎤
< +⎢ + L⎥ Fig. 6: Plot between Ro and 81
α2 LiC
⎢⎣ CRo(max) L ⎥⎦
for U eq = − [ K T Ax ]−1 K T [ Ax + D] (17)

⎧⎪ ⎡ RL ⎤
Vi(min) ≥ 2⎨Vo ⎢1 − ⎥+ â eq is continuous and hence 0< â eq < 1.
⎩⎪ ⎢⎣
Ro(max) ⎥⎦ Comparing Eq. (9) and (10) and mapping the
(15) equivalent control function onto the duty cycle function,
α3 ⎡ Vref ⎤ Li c ⎫⎪
we get:
⎢ − Vo ⎥ LC − − iC RL ⎬
α2 ⎣ β ⎦ CRo(max) ⎪⎭
Vcon = − λ1ic + λ2 (Vref − βVo ) + λ3βVo (18)
also
α ( R − RL )
βVi − LC 3 (Vref − β Vo ) − βVo o
α1 α2 Ro Vramp = β Vi (19)
<
α2 βLic
⎡ 1 RL ⎤ where
+⎢ +
⎣ CRO L ⎥⎦ ⎛ α1 1 R ⎞ α
λ1 = βL⎜ − − L ⎟ , λ2 = 3 LC
⎝ α2 RoC L⎠ α2
for
⎛ RL ⎞
⎧ ⎡
⎪Vo ⎢1 −
RL ⎤ α3
⎥+
⎫
⎪
and λ3 = ⎜ 1 − ⎟
⎪⎪ ⎢⎣ Ro(max) ⎥⎦ α 2 ⎪⎪ ⎝ R0 ⎠
Vi(min) ≥ 2 ⎨ ⎬ (16)
⎪⎡ Vref ⎤ LiC ⎪
⎪⎢ − Vo ⎥ LC − − ic RL ⎪ Variation of 81 and 83 with variations in the load is shown
⎪⎩⎣ β ⎦ CRo(max) ⎪⎭ in Fig. 6 and 5 respectively. These figures show that the
variation of 81 and 83 for 96.77% of load is only -11.15
C Step 6: Derivation of control equations using and 11.65%, respectively. 82 remains constant irrespective
equivalent control method: In the invariance of the variations in the load. Thus, the control signal does
condition, Ö = 0, substituting â- â eq, we get: not undergo noticeable changes for variations in the load.

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26
33V 18V
20 30V 13V 24
24V
15 22

25 20

10 18

5 16
5.5 6.0 6.5 7.0
0 X10-4sec
0 0.2 0.4 0.6 0.8

Fig. 7: Output response of a PID controlled buck converter for (a)

various inputs
11.86
Inductor current 11.85
2.0 Capacitor current 1184
11.83
1.5 11.82
11.81
1.0
11.8
0.5 11.79
11.78
0.0 5.5 6.0 6.5 7.0
X10-4sec
-0.5 (b)
0 22 24 26 28
-4
Fig. 9: Dynamic response of the PID controlled buck
Fig. 8: Inductor and capacitor current waveforms converter to step input change from 24 to 18 V (a)
Input voltage (b) Output response
RESULTS AND DISCUSSION
11.94
PID controller: Figure 7-10 illustrates the results
11.92
provided by the computer simulation of a PID controlled
Buck converter using Matlab-Simulink. 11.90
Figure 7 shows the output responses of the converter 11.88
when it subjected to various input voltages. It can be
11.86
noticed that as the input voltage decreases from 33 to 13
V, the peak overshoot as well as the settling time of the 11.84
converter decreases. The inductor and capacitor current 11.82
waveforms of the converter under continuous conduction
mode are shown in Fig. 8. Figure 9 shows that when the 5.8 6.0 6.2 6.4 6.6 6.8
-5
input voltage is changed from 24 to 18V at 0.6 ms, we can
infer that the system takes 0.09 ms to settle at a new
Fig. 10: Dynamic response of the PID controlled buck
steady state value which is less than the initial steady state
converter to load step change from 6 to 25S
value by 0.04 V. Figure 10 shows the dynamic response
of the converter for a load step change from 6 to 25S. It waveforms of the converter under continuous conduction
is clear that the system takes 0.058 ms to settle at a new mode are shown in Fig. 12 which is similar to that of the
steady state point which is 0.008 V greater than its steady waveforms of a PID controlled converter. When the input
state value. voltage is changed from 24 to 18 V at 0.4 ms, (Fig. 13),
we can infer that the system takes 0.02 ms to settle at a
SMC waveforms: Figure 11-15 illustrates the results new steady state value which is less than the initial steady
provided by the computer simulation of a PID based SM state value by 0.6 :V (Fig. 13) which is a very negligible
controlled Buck converter using Matlab - Simulink. value when compared to that of the PID controller.

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33V 15V
30V 13V 12.05
20 24V
12.04
15 12.03

12.02
25
12.01
10
12.00

5 11.99

11.98
0
0 2.5 3 3.5
1 2 3 X10-4 sec
X10-4sec

Fig. 11: Output response of a PID based SMC controlled buck Fig. 14: Dynamic response of the PID based SMC controlled
converter for various inputs buck converter to load step change from 6 to 25S
Inductor current PID controller
2.5 Capacitor current 20 SM controller

2.0 15

1.5
25
1.0
10
0.5
5
0.0
0
-0.5 0 0.2 0.4 0.6 0.8
2.4 2.6 2.8 3.0
X10-4sec X10-4sec

Fig. 12: Inductor and capacitor current waveforms Fig. 15: Output response of PID based SMC versus PID
controllers
26
12.05 SMC
24 PID
22
12.00
O utput voltage (VO)

11.95
20

18
11.90

16
11.85
3.2 3.4 3.6 3.8 4.0 4.2 4.4
X10-4sec
11.80

(a) 11.75
12 14 16 18 20 22 24 26 28 30
Input voltage (Vt)
11.992
Fig. 16: Variation of output with variation of input
11.900
11.988 Table 2: Comparison between PID and PID based SMC Buck Converter
11.966 Parameters PID control PID based SMC
Settling time 4.7×10G4s 1.84×10G4s
11.964 Maximum peak overshoot 6.22 V 5.253 V
11.962 Steady state error 0.16 V 0.009 V

3.2 3.4 3.6 3.8 4.0 4.2 4.4 When there is a load step change from 6 to 25S, the
X10-1sec
system takes 0.035 ms to settle with negligible steady
(b) state error (Fig. 14).
Figure 15 shows the output response of a PID based
Fig. 13: Dynamic response of the PID controlled buck SMC versus PID controller. It can be inferred from the
converter to step input change from 24 to 18 V at 0.4 figure that the SMC response has much less settling time
ms (a) Input voltage (b) Output response than that of the PID controlled Buck converter response.

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