Received: 1 March 2019 Revised: 21 June 2019 Accepted: 26 August 2019

DOI: 10.1002/cta.2701

RESEARCH ARTICLE

P-type non-isolated boost DC-DC converter with high

voltage gain and extensibility for DC microgrid applications

Farid Mohammadi1 | Mohammad Farhadi-Kangarlu2 | Hassan Rastegar1 |

Amir Khorsandi1 | Mohammad Pichan3

1
Faculty of Electrical Engineering,
Amirkabir University of Technology, Summary
Tehran, Iran In this paper, the concept of converter design, using the least number of ele-
2
Faculty of Electrical and Computer ments and achieving high voltage gain at the low duty cycle, is proposed for
Engineering, Urmia University,
the microgrids. One of the important issues in the microgrids is boosting the
Urmia, Iran
3
Faculty of Electrical Engineering, Arak
low voltage output of sources to the utility voltage level. Therefore, the step-up
University of Technology, Arak, Iran DC-DC converters are widely used in these systems to attain the utility voltage.
The benchmarking of the converters mainly in terms of the voltage gain, effi-
Correspondence
Mohammad Farhadi-Kangarlu, Faculty of ciency, the number of active and passive components, stresses on semiconduc-
Electrical and Computer Engineering, tors, and simplicity is considered. In this paper, a new extendable non-isolated
Urmia University, Urmia, Iran.
boost DC-DC converter is presented. Comparing the conventional boost con-
Email: m.farhadi@urmia.ac.ir
verter, the basic structure of the proposed converter has a high voltage gain
and reduced stress on the switch. To increase the voltage gain, the basic struc-
ture of the proposed converter can be easily extended. The modulation tech-
nique employed is high-frequency pulse-width modulation (PWM). The
detailed analysis of the proposed converter in continuous current mode (CCM)
and discontinuous current mode (DCM) is presented. The relations between
currents and voltages and the voltage gain in CCM and DCM are obtained.
Experimental results are carried out to verify theoretical concepts by using the
hardware prototype.

KEYWORDS
continues current mode (CCM), discontinuous current mode (DCM), microgrids, non-isolated
step-up DC-DC converter, voltage gain

1 | INTRODUCTION

Today, the microgrids footprint is in the power grid more than before. Considering that the use of renewable energies
has already accelerated and so that the main focus of the microgrids is renewable resources such as biomass, photovol-
taics, and wind turbines.1,2 In the DC and AC microgrids, the output of the microgrids, which includes solar panels,
wind turbines, biomass, and so on, as shown in Figure 1, is connected to the load or utility by power electronic con-
verters. The DC-DC converter is one of the important devices in the interface circuit to match the output microgrids to
the desired value.3 The output voltages of renewable applications are extremely low. To achieve the utility voltage,
boost DC-DC converters are extensively used in microgrid applications. The boost DC-DC converters are divided into a
large number of classifications. In the isolated DC-DC converters, the high-voltage gain is obtained by increasing the

1812 © 2019 John Wiley & Sons, Ltd. wileyonlinelibrary.com/journal/cta Int J Circ Theor Appl. 2019;47:1812–1836.
MOHAMMADI ET AL. 1813

FIGURE 1 General diagram of microgrids [Colour figure can be viewed at wileyonlinelibrary.com]

turns ratio of the high-frequency transformer.4 However, high-circulating current, the high voltage stress across the out-
put diode, and low efficiency are the significant drawbacks in this method.5 In the other categories, the non-isolated
DC-DC converters can be used to attain voltage step-up or step-down that leads to the reduction of size, weight, and
volume associated to the increase of efficiency because of the lack of a high-frequency transformer.6,7 If the conven-
tional DC-DC boost converter is used to attain the high output voltage, an extremely high duty ratio is needed. In recent
years, many studies have been reported on high-step-up DC-DC converters.5-15 In converter with coupled inductor,16
the leakage inductance may cause voltage spikes on the switches. Therefore, to improve the efficiency, a technique has
been proposed in17 to clamp or recycle the energy, in which case the complexity of the topology is increased. In,7,8
coupled inductor interleaving technique and high-frequency transformer used in the structure as fly-back, SEPIC, etc.
to increase the voltage gain is used. In,10 to configure a voltage gain extension cell, a boost DC-DC converter topology
integrating switched capacitor and coupled inductor is presented. In order to extend the static gain, the coupled induc-
tor can be designed, and the switched capacitor offers additional voltage gain. In,12 a new structure of high step-up DC-
DC converters is presented. By increasing the number of active-passive inductor cells, the topology is extended, and,
hence, the high voltage gains with a lower duty cycle can be obtained. Although this technique results in higher voltage
gain, in high voltage gains, the number of elements and the voltage stress of switches increase. Moreover, the design of
the control system becomes more complex. In,15 a switched capacitor-inductor passive cell to increase the voltage gain
is used, but the input current is discontinuous.
Generally, high power density, high efficiency, low voltage stress, continuous input current, low components, simple
structure, and low output voltage ripple for high voltage values are the features of the DC-DC converters. In this paper,
a new boost DC-DC converter in categories the non-isolated topologies is presented. The proposed converter has the
high voltage gain, the continuous input current and the simple structure, the low voltage stress on the switch, and the
simple control. The efficiency is increased because of the lower number of components, because if the elements of the
current path are reduced, losses also decrease. Also, achieving a higher voltage gain is possible because the proposed
structure is extendable. As it will show, in the derivatives of the proposed converter, the voltage stress on active compo-
nents is always lower than the output voltage. The input current of the proposed converter changes with two amounts,
but it never falls to zero. The voltage stresses on the switches in more than three cells are high, which causes the
switches losses to be high. The proposed converter hasn't used the benefits of the soft switching, so working at high
1814 MOHAMMADI ET AL.

power applications is a limitation for it. This paper is therefore organized as the description of the structure and its
operation analysis in continuous current mode (CCM) and discontinuous current mode (DCM) are presented in
Section 2. In Section 3, the dynamical behavior of the system has been calculated. In Section 4, derivatives of the pro-
posed converter have been investigated. Design consideration is presented in Section 5. In Section 6, the voltage stress
across active elements and the efficiency have been studied. In Section 7, the overall comparison is presented. In
Section 8, the experimental results for verifying the theoretical concepts and analyses are illustrated. Finally, Section 9
is the conclusion of the total investigations.

2 | DETAILS AND ANALYSIS OF THE P ROPOSED C ONVERTER

2.1 | The structure of the proposed converter

The proposed structure is shown in Figure 2. The proposed topology is composed of one switch, one inductor, two
capacitors, and two diodes. The central part of the proposed topology that consists of the switched capacitor and induc-
tor is drawn similar to the P letter to simplify the structure. Compared with the converter in,18 the main difference is
that the physical position of the circuit elements has been exchanged, and one inductor and one diode have been
removed. So, in theory, the related power loss is also reduced, and thus the efficiency is improved.
The proposed structure has been developed by voltage lift (VL) technique.19,20 To simplify the analysis, the following
assumptions are considered:

• The components are ideal such as the switch and diodes.

• The capacitors are large enough. The capacitor voltages are constant in one switching period in the steady-state
operation.
• All the parasitic capacitances are neglected. EMI is neglected, and the proposed converter is at the steady state.

2.2 | Operating principle of the proposed converter in CCM

Operating principles and steady-state analysis of the proposed converter in CCM and DCM are explained in detail
through different operating modes given below.

2.2.1 | CCM
In CCM operation, there are two operating modes in one switching period. Figure 3 shows the ideal waveforms of the
proposed converter in CCM. The equivalent circuits of the proposed converter in CCM operation are also shown in
Figure 4.

FIGURE 2 The structure of the proposed converter [Colour figure can be viewed at wileyonlinelibrary.com]
MOHAMMADI ET AL. 1815

FIGURE 3 Typical waveforms of the proposed converter at CCM [Colour figure can be viewed at wileyonlinelibrary.com]

• Mode I [0, Ton]: During the time interval, as shown in Figure 4A, the switch S is turned on. The diode Do is turned
on, and the diode D1 is turned off. When the voltage across the inductor becomes positive, the input voltage (Vi)
begins to charge the inductor L. Also, the energy stored in the capacitor C1 is discharged to the load, and the capaci-
tor Co is charged. According to Figure 4A, the following equations can be written:

V i = vL,on ð1Þ

vL,on = V o −vC1 ,on ð2Þ

1816 MOHAMMADI ET AL.

F I G U R E 4 The equivalent circuit of the proposed converter: A, Mode I and B, Mode II [Colour figure can be viewed at
wileyonlinelibrary.com]

vCo ,on = V o ð3Þ

where vC1 ,on , vCo ,on , and vL,on are, respectively, the voltage of capacitor C1, capacitor Co , and inductor L in the time inter-
val Ton, and Vo is the output voltage.

• Mode II [Ton, TS]: During this time interval, as it can be seen in Figure 4B, the switch S is turned off. The diode Do is
reverse-biased, but the diode D1 is forward-biased. Therefore, the diode Do is turned off, and the diode D1 is turned
on. In this condition, the capacitor C1 is charged, the stored energy in the capacitor Co is discharged to the load, and
the inductor L is demagnetized linearly. Thus, the following equations can be achieved:

vL,off = V i −vC1 ,off ð4Þ

vCo ,off = V o ð5Þ

where VL,off, V C1 ,off and V Co ,off are the voltages of the inductor L, capacitor C1 , and capacitor Co in the time interval Toff,
respectively.
As we know, the duty ratio is achieved as

T on
=D ð6Þ
T

and the duty ratio for the time interval Toff is defined as

T off
= 1 −D ð7Þ
T

Applying the volt-second balance principle across the inductor L and because the value of the capacitor C1 is large
enough, its voltage can be computed as follows:
MOHAMMADI ET AL. 1817

Vi
V C1 = vC1 ,on = vC1 ,off = ð8Þ
1 −D

where V C1 shows the voltage of the capacitor C1 at steady-state.

Substituting Equations ((2)) and ((4)) into the volt-sec balance principle across the inductor L, the following equation
can be written as
ð DT S ðTS
vL,on dt + vL,off dt = 0
0 DT S ð9Þ
 
! DðV o − vC1 ,on Þ + ð1 −DÞ V i −vC1 ,off = 0

By replacing Equation ((8)) into Equation ((9)), the voltage gain at CCM (M(CCM)) can be obtained as follows:

   
Vi Vi
D Vo − + ð 1 − DÞ V i − =0
1−D 1−D
ð10Þ
2−D
! M ðCCMÞ =
1−D

In Mode I, the input current ii,on, inductor currents iL,on, and capacitor current iC1 ,on can be calculated by the follow-
ing equation:

ii,on = iL,on + iC1,on ð11Þ

Furthermore, the current flows through the capacitor Co (iCo ,on ) can be calculated as

iCo ,on = iC1 ,on −I o ð12Þ

Thus, the current flowing through the diode Do can be written as

iDo = iC1 ,on ð13Þ

In Mode II, the current flows through the capacitor Co can be expressed as

iCo ,off = −I o ð14Þ

Also, the input current and the currents that flow through the inductor L, capacitor C1, and diode D1, denoted as ii,
off, iL,off, iC 1 ,off , iD1 ,off ,
respectively, can be achieved by the following equation:

iL,off = ii,off = iD1 ,off = − iC1 ,off ð15Þ

Applying the current-second balance principle to the capacitor Co, the following equations can be achieved:

ð DT s ðTs 
1
iCo ,on dt + iCo ,off dt = 0
Ts 0 DT s ð16Þ
Io
! iC1 ,on =
D

Using Equations (11), (15), and (16), the following equations can be calculated:

 
Io
iC1 ,off =− ð17Þ
1 −D
1818 MOHAMMADI ET AL.

Io
ΔiC1 = ð18Þ
Dð 1 − D Þ

where ΔiC1 is the current ripple of the capacitor C1.

Applying the current-second balance principle to the capacitor C1, the following equation can be achieved:

ð DT s ðTs 
1
iC1 ,on dt + iC1 ,off dt = 0
Ts 0 DT s ð19Þ
Io
! ii,off =
1 −D

Neglecting power losses of the elements, the input and output power are equal. Therefore, the current gain of the
proposed converter is given:

I o 1 −D
= ð20Þ
I i 2 −D

Furthermore, the average input current can be defined as

ii,on + ii,off 2 −D
Ii = = Io ð21Þ
2 1 −D

Substituting Equation (19) into Equation (21), the following equation is obtained:

3 −2D
ii,on = Io ð22Þ
1−D

Using Equations (12), (14), and (16), the following equations can be calculated:

1 −D
iCo ,on = Io ð23Þ
D

Io
ΔiCo = ð24Þ
D

where ΔiCo is the current ripple of the capacitor Co.

2.2.2 | DCM
In the DCM operation, the operation of the proposed converter can be divided into three modes. The typical waveforms
of the proposed boost DC-DC converter in DCM operation are illustrated in Figure 5. The equivalent circuit of the pro-
posed converter in Mode III at DCM operation is shown in Figure 6.

• Mode I: During the time interval Ton, the switch S is turned on, and the diode Do starts to conduct. This mode in
DCM is similar to Mode I in CCM operation, and its equivalent circuit in this mode is similar to
Figure 4A. Therefore, Equations (1) to (3) are also valid here.
• Mode II: As shown in Figure 4, during the time interval (D ' TS), the switch S is turned off, and the diode Do is
reverse-biased, but the diode D1 is forward-biased. This mode of the DCM operation is the same as the second mode
(Mode II) of the CCM operation (Figure 4B). Hence, Equations (4) and (5) are also valid for this mode.
• Mode III: During the time interval, (1 - D - D')TS, as shown in Figure 5, the switch S is still off. In this mode, the
diode D1 turns off then the diode Do turns on again. The equivalent circuit of this mode is depicted in Figure 6. In
MOHAMMADI ET AL. 1819

FIGURE 5 Typical waveforms of the proposed converter at DCM [Colour figure can be viewed at wileyonlinelibrary.com]

F I G U R E 6 The equivalent circuit of the

proposed converter in Mode III of DCM [Colour
figure can be viewed at wileyonlinelibrary.com]

this phase of operation, the current value of the inductor L is zero. The energy stored in the capacitor C1 is trans-
ferred to the load.
Applying the volt-sec balance principle on the inductor L and by using Equations (1), (2), and (4), the following
equation is achieved:
V C 1 = D0 V i + V o ð 1 − D0 Þ ð25Þ

Furthermore, the voltage gain in DCM operation can be obtained by applying the volt–sec balance principle on the
inductor L and by replacing (25) into the following equation as
ð DT S ð D0 T S
vL,on dt + vL,off dt = 0
0 DT S
ð26Þ
Dð 1 + D0 Þ
! M ðDCMÞ = 0
D ð D + D0 Þ

By using Equations (15) and (20), the average current flows through the diode D1 (I D1 ) can be achieved as follows:
1820 MOHAMMADI ET AL.

 
2−D
I D1 = iL,off = ii,off = Io ð27Þ
1−D

During one period of switching, the average current of the diode D1 (I D1 ) is as follows:

1
I D1 = D0 I D PEAK ð28Þ
2

where
DV i
iL,max = I D PEAK = ð29Þ
Lf s

Using Equations (28) and (29), the time interval D' can be calculated as follows:

ð2 −DÞτV o
D0 = ð30Þ
Dð1 −DÞV i

where
2Lf s
τ= ð31Þ
Ro

Consequently, the voltage transfer gain in DCM (M(DCM)), by using Equations (26), (30), and (31), can be obtained as
follows:
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u0v ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
! !2ffi 1
u u u − ð f Þ3  f   3  3
u
M ðDCMÞ = t@t
3 f4 f2 f f f f2 f f f
2
+ 3
+ + + 2 23 − 4 − + 2 23 A − 2
9ð f 1 Þ2 3f1 2f1 3f1 6f1 2f1 3f1 6f1 3f1

  
− ð f 2 Þ3
+ 3ff3
9ð f 1 Þ2
− vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð32Þ
1

u s ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
3   3 2ffi  3
!
u
t
3 f3
− ð f 2 Þ2
+ f4
+ f2
+ f2 f3
− − f4 f2
+ f2 f3
3f1 ð3 f 1 Þ2 2f1 3f1 6 f 12 2f1 3f1 6 f 12

where
 2
2 −D
f1 = τ ð33Þ
ð1 −DÞD

 
2 −D
f2 = f3 = τ ð34Þ
1 −D

f4 =D ð35Þ

3 | DYNAMIC PERFORMANCE STUDY

One of the important steps to be considered in the design of the converter is the dynamic behavior study of the con-
verter under possible variations in different conditions. For this purpose, various methods have been proposed.21-24 In
this paper, for analyzing the stability of the proposed converter, the state-space averaging method with small signal fre-
quency response is used. By this method, the open-loop transfer function of the proposed converter can be obtained to
allow stabilization. In this method, state-space equations are separately obtained for two different modes in the CCM
operation. Then, the average of the two state-space equations obtained is calculated in one switching period. To obtain
MAHAMMADI ET AL. 1821

FIGURE 7 The circuit of the proposed converter during A, Ton and B, Toff [Colour figure can be viewed at wileyonlinelibrary.com]

the accurate model, the equivalent series resistance of the capacitors (ESRs), the inductor resistance (RL), the on-resis-
tance of the diodes (RD), and the on-resistance of the switch (RDSon) are also considered. Therefore, according to
Figure 7A, the state-space equations for Mode I can be defined as
   
diL ðt Þ 1 C1 V Co BRDSon C BC 1 RDSon RDSon C1 V Co
= − − A + ð V i −i L RDS on + V C1 Þ + + V i −i L ð RDS on + R L Þ ð36Þ
dt L ACB + A2 D Ro CB + AD Ro A

   
dV C1 ðt Þ V Co B C B V Co
= − −A + ðV i −iL RDSon + V C1 Þ + ð37Þ
dt ACB + A2 D Ro CB + AD Ro A

  
dV Co ðt Þ V Co C
= − − A + AðV i −iL RDSon + V C1 Þ ð38Þ
dt CB + AD Ro
where

Co RESRCo
A = C1 , B = Co + , C = C1 ðRDSon + RD + RESRC1 Þ, D = Co RESRCo ð39Þ
Ro

Using Equations (36), (37), and (38), the following state-space system is achieved:

•X ðt Þ = A1 x ðt Þ + B1 uðt Þ ð40Þ

V o ðt Þ = C1 x ðt Þ + D1 uðtÞ ð41Þ

where
1822 MAHAMMADI ET AL.

T
diL,on ðt Þ dV C1 ðt Þ dV Co ðt Þ
•X ðt Þ = ð42Þ
dt dt dt

x ðt Þ = ½iL ðtÞ V C1 ðt Þ VCo ðtÞT ð43Þ

2 !      3
1 − C1 BðRDSon Þ2 1 C1 BðRDSon Þ 1 C1 BðRDSon Þ C C1 RDSon
6 − ðRDSon + RL Þ − −A + 7
6L CB + AD L CB + AD L ACB + A2 D Ro Ro A 7
6 7
6 BðRDS Þ       7
6 on B B C 1 7
6 − −A + 7
6
A1 = 6 CB + AD CB + AD ACB + A2
D R R A 7 ð44Þ
0 1
o o
7
6 C 7
6    − − A 7
6 − AðRDSon Þ A B C 7
6 B Ro C 7
4 CB + AD CB + AD @ CB + AD A 5

      T
1 C 1 BðRDSon Þ B A
B1 = +1 ð45Þ
L CB + AD CB + AD CB + AD

      
−AC o RDSon RESRCo ACo RESRCo Co RESRCo C
C1 = − −A + 1 ð46Þ
CB + AD CB + AD CB + AD Ro

D1 = 0 ð47Þ

In Mode II, by Kirchhoff's voltage and current law, the following equations can be obtained according to Figure 7B.

diL ðt Þ 1
= ðV i −V C1 − iL ðRD + RESRC1 + RL ÞÞ ð48Þ
dt L
 
dV C1 ðt Þ − iL
= ð49Þ
dt C1

 
dV Co ðt Þ 1 − V Co
= ð50Þ
dt C o + Co RRESRCo
o
Ro

Using Equations (48), (49), and (50), the state-space system is obtained as follows:

•X ðt Þ = A2 x ðt Þ + B2 uðt Þ ð51Þ

V o ðt Þ = C2 x ðt Þ + D2 uðtÞ ð52Þ

where

21 1 3
ðRL + RESRC1 + RD Þ − 0
6L L 7
6 7
6 1 7
A2 = 6
6 C1
0 0 7
7 ð53Þ
6  7
4 −1 5
0 0
Ro C o + RESRCo Co
MOHAMMADI ET AL. 1823

T
1
B2 = 0 0 ð54Þ
L

− Co RESRCo
C2 = 0 0 +1 ð55Þ
Ro Co + Co RESRCo

D2 = 0 ð56Þ

The average of the above matrices (A1, B1, C1, D1, A2, B2, C2, and D2) and the duty cycle can be calculated as follows:

At = A1 dðt Þ + A2 d0 ðtÞ ð57Þ

Bt = B1 dðt Þ + B2 d0 ðt Þ ð58Þ

C t = C 1 d ðt Þ + C 2 d 0 ðt Þ ð59Þ

Dt = D1 d ð t Þ + D 2 d 0 ð t Þ ð60Þ

Therefore, the averaged state-space equations can be obtained. In order to analyze the stability of the proposed con-
verter, the bode diagram is used.
The parameters of the simulation study are listed in Table 1. As shown in Figure 8, the bode diagram is drawn for
different duty cycles. For duty cycle 50% (D = 0.5), the phase margin is 85.4 , and the magnitude is infinite, which indi-
cates that from the standpoint of stability, the system is stable. Furthermore, in duty cycles 25% and 75%, the phase

TABLE 1 The specifications of the proposed converter

Parameters Values Parameters Values

Input voltage 12.5 V The on-resistance of diodes (RD) 0.01 V
Capacitors C1, Co 100 μF, 50 V The on-resistance of the switch (RDSon) 0.04 Ω
Inductor L1 1 mH Equivalent series resistances (ESRs) 0.02 Ω
Switching frequency 33 kHz The inductor resistance (RL) 0.05 Ω
Duty cycle 0.25, 0.5, 0.75 The voltage reference 32 V

FIGURE 8 The bode diagram for different duty cycles [Colour figure can be viewed at wileyonlinelibrary.com]
1824 MOHAMMADI ET AL.

margin has varied from 82.1 to 85.9 , whereas the magnitude has not changed. As can be seen in Figure 8, due to the
variation in the duty cycle, there is no disturbance in the system stability and the system is stable in the different duty
cycles. Therefore, to achieve the proper dynamic performance, the voltage control loop is designed. In the system, there
was a steady state error problem, which the integral term compensates it. Due to the amplification of noise in the PID
controller, the derived term is deleted; therefore, the PI controller is used. The controller parameters are selected using
practical methods (trial and error method). As shown in Figure 9, for continuous variations in the input voltage, the
output voltage remains constant approximately at the reference value.

4 | DERIVATIVES OF THE P ROPOSED CONVERTER

It is evident that the voltage gain of the proposed boost DC-DC converter may not be adequate for some of the applica-
tions. In order to achieve higher voltage gains, another cell can be added to the proposed boost DC-DC converter.

4.1 | The first derivative of the proposed converter

The first derivative of the proposed converter is indicated in Figure 10A. As seen in Figure 10A, the proposed converter
is composed of two switches, two inductors, three capacitors, and three diodes, although the switches can have different
duty cycles. It is assumed that they have the same duty cycle and they are switched simultaneously. With this assump-
tion, there will be two modes in the time interval Ts, which are indicated in Figures 10B and 10C.
Mode I: During the time interval, Ton, the two switches are turned on simultaneously. As shown in Figure 10B, the
diodes D1 and D2 are turned off, but the diode Do is turned on. The voltage across L1 is the input voltage, thereby caus-
ing L1 to be magnetized. The capacitor C1 is discharged to the inductor L2, thereby causingL2 to be magnetized. Also,
the capacitor C2 is discharged to the load. Thus, the capacitor Co is charged. According to the aforementioned facts, the
following equations can be obtained as

V i = V L1 ,on ð61Þ

V L1 ,on = V L2 ,on −V C1 ,on ð62Þ

V L2 ,on = V o −V C2 ,on ð63Þ

F I G U R E 9 The closed-loop response of the proposed converter due to the continuous variation of the input voltage [Colour figure can
be viewed at wileyonlinelibrary.com]
MOHAMMADI ET AL. 1825

F I G U R E 1 0 A, The structure of the first derivative of the proposed converter and the equivalent circuit of the proposed converter in
Modes (B) I and (C) II [Colour figure can be viewed at wileyonlinelibrary.com]

where V L1 ,on , V L2 ,on , V C1 ,on and V C2 ,on are the voltages of the inductors L1, L2 and capacitors C1, C2 in Ton, respectively.
Mode II: During the time interval, Toff, the two switches S1 and S2 are off. As seen in Figure 10C, the diodes D1 and
D2 are forward-biased, but the diode Do is reverse-biased. The inductors L1 and L2 are linearly demagnetized. Con-
versely, the capacitors C1 and C2 are charged. Besides, the stored energy in the capacitor Co is discharged to the load.
Therefore, the following equations can be obtained:

V i = V L1 ,off + V C1 ,off ð64Þ

V i = V L2 ,off + V C2 ,off ð65Þ

where V L1 ,off , V L2 ,off , V C1 ,off , and V C2 ,off are the voltages of the inductors L1 and L2 and capacitors C1 and C2 in Toff,
respectively. By applying the volt-second balance principle on the inductor L1, the following equation can be calculated:

ð DT S ðTS
V L1 ,on dt + V L1 ,off dt = 0
0 DT S ð66Þ
Vi
! V C1 ,off =
1−D

Using the volt-sec principle on the inductor L2, the following equation can be calculated as:
1826 MOHAMMADI ET AL.

ð DT S ðTS
V L2 ,on dt + V L2 ,off dt = 0
0 DT S
ð67Þ
Vi
! V C2 ,off =
ð 1 − DÞ 2

Again, applying the volt-second principle across the inductor L1 and by using Equations (66) and (67), the voltage
gain can be calculated as
!
2−D
N =2
M ðCCM Þ = +1 ð68Þ
ð1 −DÞ2

Moreover, neglecting all losses, the input and output power are equal. Therefore, the relation between the average
value of the input current concerning the output current is achieved as
!
2−D
Ii = + 1 Io ð69Þ
ð1 −DÞ2

4.2 | The Nth derivative of the proposed converter

As mentioned earlier, in many applications, a very high voltage gain is required. For this purpose, more cells can be
added to the single cell of the proposed converter. The Nth derivative of the proposed converter is indicated in
Figure 11. As shown in Figure 11, there are N switches, N+1 diodes, N+1 capacitors, and N inductors in the Nth deriva-
tive structure of the proposed converter. To achieve the voltage gain, the specific pattern is used. As in the previous sec-
tion, the same pattern was used.
During the time interval Ton, all the switches (S1, S2, … , SN) is turned on. Also, the diode Do is turned on. All capaci-
tors except the capacitor Co (the output capacitor) are discharged, and all inductors (L1, L2, … , LN) are magnetized.
Besides, the output capacitor Co is charged. In the next phase of operation, during the time interval Toff, all the switches
(S1, S2, … , SN) is turned off. Also, the diode Do is turned off. The capacitors C1 to CN are charged, and all inductors (L1,
L2, … , LN) are demagnetized. Besides, the output capacitor Co is discharged to the load. Thus, the voltage gain in the
Nth derivative of the proposed converter (M NðCCM
=n
Þ ) can be calculated as

!
2−D
=n
M NðCCM Þ = + ðN −1Þ ð70Þ
ð 1 − DÞ N

5 | D E S I G N C ON S I D E R A T IO N

In the steady-state analysis, as mentioned in Section 2, the output voltage is constant. However, in practice, the capaci-
tor voltage has a small ripple because of charging and discharging. Therefore, by the amount of the ripple in the

FIGURE 11 The structure of the Nth derivative of the proposed converter [Colour figure can be viewed at wileyonlinelibrary.com]
MOHAMMADI ET AL. 1827

capacitors, the quality of the output voltage is determined. If the ripple is small, the quality of the output voltage is bet-
ter. The output voltage ripples can be reduced by increasing the capacitor Co or the switching frequency fS. But increas-
ing the capacitance increases the size of the capacitor, which increases the cost and size of the proposed boost DC-DC
converter. On the other hand, if the switching frequency to be high, the switching losses increase, and, hence, the effi-
ciency of the converter decreases. Thus, a tradeoff point is needed between the quality of the output voltage and the
capacitor size and switching frequency. In order to prevent DCM operation, the current of the inductor should be
maintained at a positive value.
Moreover, if the inductor current ripple is high, the maximum current of the switches will increase, which increases their
rating and cost of the proposed converter. However, to suppress the inductor current ripple, the inductance should be as high
as possible; however, the cost and volume of the proposed converter increase with the higher size of the inductor. As a result,
in this section, three requirements in the design and implementation of the proposed converter will be analyzed.

5.1 | Inductor design

A small inductor is utilized in order to reduce the proposed converter volume. To design the inductor L, its critical
inductance value must be calculated. Considering that the voltage across the capacitors C1 and Co is constant, the cur-
rent ripple can be obtained using Equation (1) as

Vi
iL,on = t + iL,min ð71Þ
L

Vi
iL,on jt = DT S = DT S + iL,min = iL,max
L ð72Þ
Vi
! ΔiL = DT S
L

Using Equation (4), the current of the inductor L in Toff can be achieved as

ð2V i −V o Þ
iL,off = ðt −DT S Þ + iL,max ð73Þ
L

The average current flows through the capacitor Co and the inductor L (I Co ,ave ) can be computed as follows

I i = I o + I L,ave + I Co ,ave ð74Þ

The average current flows to the capacitor Co must be zero over a switching period at steady state. Therefore,
Equation (74) can be written as follows:

I i = I o + I L,ave ð75Þ

By replacing Equation (20) in Equation (75), it can be calculated as

Io
I L,ave = ð76Þ
1 −D

To determine the critical and minimum value of the inductor L, iL,min should be considered as zero; then, by using
Equations (71) and (76), the minimum inductor value can be computed as

Ro Dð1 −DÞ2
Lmin ≥ ð77Þ
2ð2 −DÞ f S

where Lmin is the minimum value of the inductor L and fS is the switching frequency.
1828 MOHAMMADI ET AL.

5.2 | Output capacitor design

In order to limit the ripple of the output voltage (ΔV o = ΔV Co ) to the allowed range, the voltage ripple on the capacitor
Co should be computed. The voltage ripple on the capacitor Co (ΔV Co ) is the voltage ripple on the capacitor Co caused
by the current that flows through the equivalent series resistance denoted by ΔV Co ,ESR and the voltage ripple of the
capacitor Co caused by the charging and discharging of the capacitor expressed by ΔV Co ,CD . Therefore, the following
equation can be written using Equation (24):
Io
ΔV Co ,ESR = ESRCo ΔiCo = ESRCo ð78Þ
D
where
tanγ Co
ESRCo = ð79Þ
2π f S
where tanγ Co is the dissipation factor of the capacitorCo. Also, ΔV Co ,CD can be computed as follows:

ð1 −DÞI o
ΔV Co ,CD = ð80Þ
Co f S

Therefore, by using Equations (78), (79), and (80), ΔV Co can be achieved as

ΔV Co = ΔV Co ,CD + ΔV Co ,ESR
 
Co tanγ Co + 2πDð1 − DÞ ð81Þ
! ΔV Co = Io
2πDCo f S

Thus, the minimum value of the capacitor Co is calculated by

2πDð1 − DÞI o
Co,min ≥ ð82Þ
2πDΔV Co f S −I o tanγ Co

5.3 | The Capacitor design of the cell

5.3.1 | Capacitor design for the single cell of the proposed converter
Similar to the output capacitor design, the voltage ripple on the capacitor C1 (ΔV C1 ) should be calculated. As seen in
Figure 3A, the capacitor C1 is discharged to the load. Also, as seen in Figure 3B, the capacitor C1 is charged by the input
voltage. Generally, the voltage ripple across C1 is

ΔV C1 = ΔV C1 ,CD + ΔV C1 ,ESR ð83Þ

where ΔV C1 ,ESR is the voltage ripple across the capacitor C1 due to the current that flows through the equivalent series
resistance and ΔV C1 ,CD is the voltage ripple of the capacitor C1 due to the charging and discharging. Therefore, the fol-
lowing expressions can be achieved using Equations (17) and (18):

Io
ΔV C1 ,ESR = ESRC1 ΔiC1 = ESRC1 ð84Þ
Dð 1 − D Þ

tanγ C1
ESRC1 = ð85Þ
2π f S

Io
ΔV C1 ,CD = ð86Þ
C1 f S

As a result, the minimum value of the capacitor C1 (C1,min) can be achieved as

MOHAMMADI ET AL. 1829

2πDð1 − DÞI o
C 1,min ≥ ð87Þ
2πΔV C1 f S Dð1 −DÞ− I o tanγ C1

6 | VOLTAGE S TRESS A ND EFFICIENCY

6.1 | voltage stress

Voltage stresses on different components of the converters are the most important factor to select the appropriate
devices. In the proposed converter and all derivatives, the voltage stress on active elements is low and is less than the
output voltage. For the single cell of the proposed converter, the voltage stress on the switch S (VS − stress) and the volt-
age stress on diode D1 can be computed as
Vo
V S − stress = V D1 − stress = ð88Þ
2−D
Also, the voltage stress on the switch S2 and the voltage stress on diode D2 for the first derivative of the proposed
converter is achieved as follows:

Vo
V S2 − stress = V D2 − stress = ð89Þ
ð2 −DÞ + ð1 − DÞ2

Furthermore, for the general structure with N cells, the voltage stress on switches and diodes can be calculated by
the following expression:

Vo
V SN − stress = V DN − stress = ð90Þ
ð2 − DÞ + ðN − 1Þð1 − DÞN

Also, with a similar method, the voltage stress on the diode Do can be calculated using the following general
formula:

!
ð 2 − DÞ
V Do − stress = V o − V i = + N −2 V i ð91Þ
ð 1 − DÞ N

As the number of cells increases, the voltage stress on the switch also increases.

6.2 | Efficiency
To analyze the efficiency of the proposed converter, the parasitic resistances will be defined as follows: RS is the switch
on-state resistance, Cs is the parasitic switch capacitor, RFD is the diode forward resistance, VFD the diode threshold volt-
age, RL,ESR is the ESR of the inductor, and RC,ESR is the ESR of the capacitor. The voltage ripple of the capacitors and
the inductors are ignored.
The conduction loss of the switch S (PRS ) can be obtained as follows:

 2
2−D
PRS = RS ðI S,RMS Þ2 = RS D Io2 ð92Þ
1−D

The switching loss (PSW) can be expressed as follows:

 2
Vi
2
PSW = f S CS V S = f S CS ð93Þ
1−D

The diodes D1 and Do forward resistance losses (PRF,D1 , PRF,Do ) can be obtained as
1830 MOHAMMADI ET AL.

ð2 −DÞ2 2
PRF,D1 = RFD1 ðI D1 ,RMS Þ2 = RFD1 Io ð94Þ
1−D
 
2 1
PRF,Do = RFDo ðI Do ,RMS Þ = RFDo Io2 ð95Þ
D

The diodes D1 and Do forward voltage losses (PVFD1 , PVFDo ) can be obtained as

 
2−D
PVFD1 = V FD1 ðI D1 ,ave Þ = V FD1 Io ð96Þ
1−D

 
1
PVFDo = V FDo ðI Do ,ave Þ = V FDo Io ð97Þ
D

The conduction loss of the inductor L (PRL ) can be calculated as follows:

D2 −5D + 5 2
PRL = RL,ESR ðI L,RMS Þ2 = RL,ESR Io ð98Þ
ð 1 − DÞ 2

The power losses of capacitors C1 and Co (PRC1 ,ESR ) can be computed as

 
2 −D
PRC1 ,ESR = RC1 ,ESR ðI C1 ,RMS Þ2 = RC1 ,ESR Io2 ð99Þ
1 −D

The total losses and the efficiency (Ploss, η) can be defined as

PSW
Ploss = PRS + + PRF,D1 + PRF,Do + PVFD1 + PVFDo + PRL + PRC1 ,ESR + PRCo ,ESR ð101Þ
2

Po 1
η= = ð102Þ
Po + Ploss 1 + PPo

7 | C O M PA R I S O N S T U D Y

Considering the simplicity of the proposed structure and the low number of used elements, the voltage gain of the pro-
posed converter is higher than that of the conventional boost converter. As seen in Table 2, the number of components
of the second derivative of the proposed converter and the converters presented in12-14 is equal and is lower than,25,27
and is higher than.27 However, the number of inductors in12,14,25,27 is higher than the one in the other converters. Also,
in12 the used switches are higher than the other converters. As illustrated in Figure 12, from the viewpoint of the volt-
age gain, the second derivative of the proposed converter has extremely higher voltage gain with respect to the other
converters.
Furthermore, as can be seen in Figure 13, the total voltage stress on the switches in the first derivative of the pro-
posed converter is lower than the one of the other converters. However, as mentioned before, its voltage gain is lower.
On the other hand, in the second derivative of the proposed converter, which has the highest voltage gain, the total
voltage stress on switches is acceptable compared with the other converters. Also, as shown in Figure 13, in the con-
verter with two cells, the amount of stress current decreases with the increasing duty cycle that is one of the most
important features of this converter in its extended state. That makes it possible to divide the current of the switches
into two-cell converters. Therefore, the total current stress in the switches is reduced compared with the other con-
verters, but the voltage stress increases. To select the appropriate switches, a trade-off point should be considered
MOHAMMADI ET AL. 1831

TABLE 2 Overall comparison between the proposed converter and others converters

Total Switch Total voltage Total current Continuous

device voltage stress on stress on input
Converters NS ND NC NL count Voltage gain stress switches switches current
Proposed N 1 2 2 1 6 ð2 − DÞV i Vo Vo ð2 − DÞI o Yes
ð1 −DÞ ð2− DÞ ð2 − DÞ ð1 − DÞ
=1
   Vo ð2 − DÞV o Io
Proposed N 2 3 3 2 10 ð2 − DÞV i Yes
ð1 − DÞ2
+ 1 Vi 3 − 3D + D2 3 − 3D + D2 D
=2
12 ð1 + 2DÞV i Vo ð3 + DÞV o ð4 + 3DÞI o
3 3 1 3 10 Yes
ð1 − DÞ 1 + 2D 1 + 2D 4ð1 − DÞ
13 ð3 − DÞV i Vo 2V o ð1 + DÞI o
2 3 3 2 10 3−D 3−D
Yes
ð1 −DÞ ð1 − DÞ
14 ð1 + 3DÞV i Vo 2V o ð1 + DÞI o
2 2 3 3 10 Yes
ð1 − DÞ 1 + 3D 1 + 3D ð1 + 3DÞ
25
2 5 4 3 14 ð3D − D2 ÞV i Vo
1−D
2V o
1−D
ðD + D2 ÞI o No
1−D ð1 − DÞ
26 Vo 2V o
2 2 3 1 8 (1+D)Vi 1+D 1+D
(2+2D)Io No
27 ð1 + 3DÞV i ð1 + DÞV o 2ð1 + DÞV o ð2 + 2DÞ
2 7 1 4 14 Yes
ð1 − DÞ 1 + 3D 1 + 3D 1 −D I o

F I G U R E 1 2 Voltage gain versus duty cycle in the compared converters at CCM [Colour figure can be viewed at
wileyonlinelibrary.com]

F I G U R E 1 3 The normalized voltage and current stress of switches versus duty cycle [Colour figure can be viewed at
wileyonlinelibrary.com]
1832 MOHAMMADI ET AL.

TABLE 3 Specification of prototype proposed converter

Values

Parameters N=1 N=2

Input voltage 12.5 V 12.5 V
Output voltage 37.1 V 87.1 V
Output power 50 W 50 W
Capacitors C1,2, Co 100 μF, 50 V 220 μF, 100 V
Inductor L1,2 1 mH 1 mH
Switching frequency 33 kHz 33 kHz
Power switches IRFP260N IRFP260N
Diodes MUR1560G MUR1560G

between these two values: in both the first and second derivatives of the proposed converter, based on the low whole
voltage stress of active components while owing high voltage gain; therefore, the efficiency of them is higher.

8 | EXPERIMENTAL RESULTS

To verify theoretical concepts and to validate the feasibility of the proposed converter (Figure 2), an experimental proto-
type is implemented. The parameters are listed in Table 3. As mentioned in the previous section, the converter is capa-
ble of extensibility. Due to the addition of the other cell, a very high voltage with low voltage stress is obtained on the
switches. First, the converter was provided by one cell and then made with two cells. In the construction of the con-
verter, the elements listed in Table 3, plus the Arduino Mega 2560 processor, have been used.
The experimental results are presented in CCM operation with D = 0.5. Figures 14A and 14B indicate the inductor
voltage (VL) and the inductor current (iL), respectively. A 0.15-ohm resistor is used in series with inductor L to measure
the current that flows through inductor L. The voltages of capacitors C1 and Co are shown in Figures 14E and 14D,
respectively. Furthermore, the average voltage of the capacitor C1 is 27.2V, which is approximately equal to the result of
the theoretical analysis. Because the maximum and minimum currents of the inductor L are 1.4A and 1.8A, respec-
tively, the average of the inductor current iL is ’1.6A. In addition, to validate the obtained voltage gain in Equation (10),
as can be seen in Figure 14D that the average voltage of the capacitor Co is approximately 37.1V, in the event that
according to Equation (10), the average output voltage is 37.5V that is expressed as follows.

2 −D D = 0:5 Theoretical V o = 37:5

N = 1 : M CCM = ! M CCM = 3 ! ð103Þ
1 −D Experimental V o = 37:1

The diode voltage waveforms that correspond the obtained relations for the diodes are shown in Figures 14F and
14G. Also, the voltage stress across the switch S is depicted in Figure 14C. As in the analysis of the theory, the current
input is continuous and varies between two values. As shown in Figure 14H, the amount of current between two differ-
ent values is changing and will not be zero. Also, measuring the input current, a 0.1-ohm resistance is set in the input
current path. One of the most important design criteria is the control of its stable performance due to changes and
noise. For this purpose, as shown in Figure 15, a step change in the reference value is created, and the controller in a
short time responds to the changes, which are applied to achieve the desired voltage level. The essential point is the
converter's stability after the variation in the reference value, which can be a significant problem in the design of the
converter and controller.
As discussed in the comparison section, the converter with two cells (N = 2) has a high voltage gain and low voltage
stress. As shown in Figures 16A and 16B, respectively, the output voltage in half of the duty cycle is approximately
7 times the value of the input voltage, and the peak of voltage stress on the switch S2 is 51.3.
The theoretical and experimental efficiency of the proposed converter is illustrated in Figure 17. The efficiency cur-
ves are achieved by changing the output load at D = 0.5. As shown in Figure 17, the experimental efficiency for both
MOHAMMADI ET AL. 1833

F I G U R E 1 4 The experimental results at CCM operation for N = 1: A, the inductor voltage (VL); B, the inductor current (iL); C, the
voltage of across switch (VS); D, the output voltage (VCo = Vo); E, the capacitor voltage (V C1 ); F, the voltage of diode (V D1 ); G, the voltage of
the diode (VDo); H, the input current [Colour figure can be viewed at wileyonlinelibrary.com]
1834 MOHAMMADI ET AL.

F I G U R E 1 5 The transient state for change in the reference value of the output voltage [Colour figure can be viewed at
wileyonlinelibrary.com]

FIGURE 16 The experimental results at CCM operation for N = 2: A, the output voltage (VCo = Vo); B, the voltage of across switch S2
(V S2 ) [Colour figure can be viewed at wileyonlinelibrary.com]

F I G U R E 1 7 The efficiency curves of the proposed converter with N = 1 and N = 2 [Colour figure can be viewed at
wileyonlinelibrary.com]
MOHAMMADI ET AL. 1835

proposed converter (N = 1, 2) at Po ’ 50W is maximum. But its value is higher for single cells and is equal to 92.6% and
for the converter with two cells is equal to 90.5%. In the converter with two cells, this amount has decreased, and
according to theoretical calculations presented in Equations (92) to (100), it can be concluded that due to the increase
in the number of elements in the current path, this efficiency value has decreased. Considering the high voltage gain in
the two-cell converter, in the low duty cycle, and low-voltage stress, it is recommended to use this converter in low
power.

9 | C ON C L US I ON

In this paper, a new extendable non-isolated DC-DC boost converter is presented for microgrid applications. The struc-
ture of the presented boost converter is simple and modular. Also, it provides low output voltage ripple. The voltage
stress across all active components is low and always lower than the output voltage. Also, low rating switches with low
on-state resistance can be selected that can lead to a lower cost. The high voltage gain has been achieved in the low duty
cycle, yielding lower conduction loss. The proposed converter has a compact size, and it can be used in applications
with space limitations. Also, it is appropriate for low power applications because of its high efficiency in the low power.
Besides, one switching control circuit can be used because the switches can operate simultaneously. Finally, to indicate
the theoretical analysis, a 50-W hardware prototype of the proposed converter (N = 1, 2) is implemented in the labora-
tory. The experimental results verify the theoretical analysis quite well.

ORCID

Farid Mohammadi https://orcid.org/0000-0002-7377-0976

Mohammad Farhadi-Kangarlu https://orcid.org/0000-0002-3827-2058

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How to cite this article: Mohammadi F, Farhadi-Kangarlu M, Rastegar H, Khorsandi A, Pichan M. P-type
non-isolated boost DC-DC converter with high voltage gain and extensibility for DC microgrid applications. Int
J Circ Theor Appl. 2019;47:1812–1836. https://doi.org/10.1002/cta.2701