+

William Stallings
Computer Organization
and Architecture
9th Edition
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Chapter 14
Processor Structure and Function
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Processor Organization
Processor Requirements:
 Fetch instruction
 The processor reads an instruction from memory (register, cache, main memory)

 Interpret instruction
 The instruction is decoded to determine what action is required

 Fetch data
 The execution of an instruction may require reading data from memory or an I/O
module

 Process data
 The execution of an instruction may require performing some arithmetic or logical
operation on data

 Write data
 The results of an execution may require writing data to memory or an I/O module

 In order to do these things the processor needs to store some data

temporarily and therefore needs a small internal memory
CPU With the System Bus
CPU Internal Structure
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Register Organization
 Within the processor there is a set of registers that function as a
level of memory above main memory and cache in the
hierarchy

 The registers in the processor perform two roles:

User-Visible Registers Control and Status Registers

 Enable the machine or  Used by the control unit to

assembly language control the operation of the
programmer to minimize main processor and by privileged
memory references by operating system programs to
optimizing use of registers control the execution of
programs
User-Visible Registers

Categories:
Referenced by means of • General purpose
the machine language • Can be assigned to a variety of functions by
the programmer
that the processor • Data
executes • May be used only to hold data and cannot
be employed in the calculation of an
operand address
• Address
• May be somewhat general purpose or may
be devoted to a particular addressing mode
• Examples: segment pointers, index
registers, stack pointer
• Condition codes
• Also referred to as flags
• Bits set by the processor hardware as the
result of operations
 Table 14.1
Condition Codes
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Control and Status Registers
Four registers are essential to instruction execution:

 Program counter (PC)

 Contains the address of an instruction to be fetched

 Instruction register (IR)

 Contains the instruction most recently fetched

 Memory address register (MAR)

 Contains the address of a location in memory

 Memory buffer register (MBR)

 Contains a word of data to be written to memory or the word most
recently read
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Program Status Word (PSW)

Register or set of registers that

contain status information

Common fields or flags include:

• Sign
• Zero
• Carry
• Equal
• Overflow
• Interrupt Enable/Disable
• Supervisor
 Example
Microprocessor
Register
Organizations
 Includes the following Instruction
stages:
Cycle

Fetch Execute Interrupt

If interrupts are
Read the next enabled and an
Interpret the opcode
instruction from interrupt has occurred,
and perform the
memory into the save the current
indicated operation
processor process state and
service the interrupt
Instruction Cycle
Instruction Cycle State Diagram
Data Flow, Fetch Cycle
Data Flow, Indirect Cycle
Data Flow, Interrupt Cycle
Pipelining Strategy

To apply this concept

to instruction
execution we must
Similar to the use of recognize that an
an assembly line in a instruction has a
manufacturing plant number of stages

New inputs are

accepted at one end
before previously
accepted inputs
appear as outputs at
the other end
Two-Stage Instruction Pipeline
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Additional Stages
 Fetch instruction (FI)
 Fetch operands (FO)
 Read the next expected
instruction into a buffer  Fetch each operand from
memory
 Decode instruction (DI)  Operands in registers need
 Determine the opcode and not be fetched
the operand specifiers
 Execute instruction (EI)
 Calculate operands (CO)  Perform the indicated
 Calculate the effective operation and store the
address of each source result, if any, in the specified
operand destination operand location
 This may involve
 Write operand (WO)
displacement, register
indirect, indirect, or other  Store the result in memory
forms of address calculation
Timing Diagram for Instruction
Pipeline Operation
The Effect of a Conditional Branch
on Instruction Pipeline Operation
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Six Stage
Instruction Pipeline
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Alternative Pipeline
Depiction
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Speedup Factors
with Instruction
Pipelining
 Pipeline Hazards
Occur when the
pipeline, or some
portion of the There are three
pipeline, must stall types of hazards:
because conditions • Resource
do not permit • Data
continued execution • Control

Also referred to as a
pipeline bubble
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Resource
Hazards

A resource hazard occurs when two

or more instructions that are already
in the pipeline need the same
resource

The result is that the instructions must

be executed in serial rather than
parallel for a portion of the pipeline

A resource hazard is sometimes

referred to as a structural hazard
 RAW

Hazard

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Data Hazards
A data hazard occurs when there is a conflict in the
access of an operand location
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Types of Data Hazard
 Read after write (RAW), or true dependency
 An instruction modifies a register or memory location
 Succeeding instruction reads data in memory or register location
 Hazard occurs if the read takes place before write operation is
complete

 Write after read (WAR), or antidependency

 An instruction reads a register or memory location
 Succeeding instruction writes to the location
 Hazard occurs if the write operation completes before the read
operation takes place

 Write after write (WAW), or output dependency

 Two instructions both write to the same location
 Hazard occurs if the write operations take place in the reverse order
of the intended sequence
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Control Hazard

 Also known as a branch hazard

 Occurs when the pipeline makes the wrong decision on a

branch prediction

 Brings instructions into the pipeline that must subsequently

be discarded

 Dealing with Branches:

 Multiple streams
 Prefetch branch target
 Loop buffer
 Branch prediction
 Delayed branch
 Multiple Streams

A simple pipeline suffers a penalty for a

branch instruction because it must choose
one of two instructions to fetch next and may
make the wrong choice

A brute-force approach is to replicate the

initial portions of the pipeline and allow the
pipeline to fetch both instructions, making
use of two streams

Drawbacks:
• With multiple pipelines there are contention delays
for access to the registers and to memory
• Additional branch instructions may enter the pipeline
before the original branch decision is resolved
Prefetch Branch Target

 When a conditional branch is recognized, the

target of the branch is prefetched, in addition
to the instruction following the branch

 Target is then saved until the branch

instruction is executed

 If the branch is taken, the target has already

been prefetched

 IBM 360/91 uses this approach

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Loop Buffer
 Small, very-high speed memory maintained by the
instruction fetch stage of the pipeline and containing the n
most recently fetched instructions, in sequence

 Benefits:
 Instructions fetched in sequence will be available without the
usual memory access time
 If a branch occurs to a target just a few locations ahead of the
address of the branch instruction, the target will already be in the
buffer
 This strategy is particularly well suited to dealing with loops

 Similar in principle to a cache dedicated to instructions

 Differences:
 The loop buffer only retains instructions in sequence
 Is much smaller in size and hence lower in cost
Loop Buffer
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Branch Prediction

 Various techniques can be used to predict whether a branch

will be taken:

1. Predict never taken  These approaches are static

2. Predict always taken  They do not depend on the
execution history up to the time of
3. Predict by opcode the conditional branch instruction

1. Taken/not taken switch

 These approaches are dynamic
2. Branch history table
 They depend on the execution history
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Branch Prediction
Flow Chart
Branch Prediction State Diagram
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Dealing With
Branches
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Intel 80486 Pipelining
 Fetch
 Objective is to fill the prefetch buffers with new data as soon as the old data
have been consumed by the instruction decoder
 Operates independently of the other stages to keep the prefetch buffers full

 Decode stage 1
 All opcode and addressing-mode information is decoded in the D1 stage
 3 bytes of instruction are passed to the D1 stage from the prefetch buffers
 D1 decoder can then direct the D2 stage to capture the rest of the instruction

 Decode stage 2
 Expands each opcode into control signals for the ALU
 Also controls the computation of the more complex addressing modes

 Execute
 Stage includes ALU operations, cache access, and register update

 Write back
 Updates registers and status flags modified during the preceding execute
stage
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80486
Instruction
Pipeline
Examples
 Table 14.2
x86 Processor Registers
 Table 14.2
x86 Processor Registers
x86 EFLAGS Register
 Control
Registers
Mapping of MMX Registers to
Floating-Point Registers
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Interrupt Processing
Interrupts and Exceptions
 Interrupts
 Generated by a signal from hardware and it may occur at random
times during the execution of a program
 Maskable
 Nonmaskable

 Exceptions
 Generated from software and is provoked by the execution of an
instruction
 Processor detected
 Programmed

 Interrupt vector table

 Every type of interrupt is assigned a number
 Number is used to index into the interrupt vector table
 Table 14.3
x86 Exception and Interrupt Vector Table

Unshaded: exceptions Shaded: interrupts

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The ARM Processor
ARM is primarily a RISC system with the following
attributes:
 Moderate array of uniform registers

 A load/store model of data processing in which operations only perform

on operands in registers and not directly in memory

 A uniform fixed-length instruction of 32 bits for the standard set and 16

bits for the Thumb instruction set

 Separate arithmetic logic unit (ALU) and shifter units

 A small number of addressing modes with all load/store addresses

determined from registers and instruction fields

 Auto-increment and auto-decrement addressing modes are used to

improve the operation of program loops

 Conditional execution of instructions minimizes the need for conditional

branch instructions, thereby improving pipeline efficiency, because
pipeline flushing is reduced
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Simplified ARM
Organization
Processor Modes

Most application
programs execute in
ARM user mode
architecture • While the processor is in
supports seven user mode the program
being executed is unable
execution to access protected
modes system resources or to
change mode, other than
by causing an exception
to occur

Remaining six Advantages to defining

so many different
execution modes privileged modes
are referred to as •The OS can tailor the use of
privileged modes system software to a variety
of circumstances
• These modes are •Certain registers are
used to run system dedicated for use for each of
the privileged modes, allows
software swifter changes in context
Exception Modes

Have full access

to system Entered when
resources and specific
can change exceptions occur
modes freely

Exception System mode:

modes: • Not entered by any
exception and uses the
• Supervisor mode same registers available
• Abort mode in User mode
• Is used for running
• Undefined mode certain privileged
• Fast interrupt mode operating system tasks
• Interrupt mode • May be interrupted by
any of the five exception
categories
Figure 14.26

ARM
Register
Organization
Format of ARM CPSR and SPSR
Table 14.4

ARM
Interrupt
Vector
+ Summary Processor Structure
and Function
Chapter 14
 Instruction pipelining
 Processor organization
 Pipelining strategy
 Register organization  Pipeline performance
 User-visible registers  Pipeline hazards
 Control and status registers  Dealing with branches
 Intel 80486 pipelining
 Instruction cycle
 The indirect cycle  The Arm processor
 Data flow  Processor organization
 Processor modes
 The x86 processor family
 Register organization
 Register organization
 Interrupt processing
 Interrupt processing