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CS 225 - Fundamentals of Computer Systems - Junaid H Siddiqui

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Lahore University of Management Sciences

CS 225 – Fundamentals of Computer Systems


Fall 2017

Instructor Junaid Haroon Siddiqui
Room No. SSE 9-G20A
Office Hours TBD
Email junaid.siddiqui@lums.edu.pk
Telephone 8197
Secretary/TA TBD
TA Office Hours TBD
Course URL (if any)

Course Basics
Credit Hours 4
Lecture(s) Nbr of Lec(s) Per Week 2 Duration 100 mins
Recitation/Lab (per week) Nbr of Lec(s) Per Week Duration
Tutorial (per week) Nbr of Lec(s) Per Week Duration

Course Distribution
Core Computer Science (Equivalent to CS320+CS320L)
Elective
Open for Student Category All
Close for Student Category

COURSE DESCRIPTION
We discuss how computers operate at fairly low level of abstraction and then discuss how computer systems build as layers and layers of
abstraction. Our focus will be to introduce computer systems from the perspective of a programmer, rather from the more traditional perspective
of a system implementer.

After taking this course, you will know the components of a computer and how do they fit together. How computers do arithmetic and how does
the code you write actually execute? How does a program in a high level language like C get translated into a form the machine can execute? How
can you write code likely to execute efficiently? How is information stored and accessed? How does your program access existing "libraries"?


COURSE PREREQUISITE(S)

• CS 100


Learning Outcomes

Ref: Learning Outcomes of ACM Curriculum Guidelines 2013
• SF/Computational Paradigms (Core Tier 1, 3 hours)
• SF/Cross-Layer Communications (Core Tier 1, 3 hours)
• SF/State and State Machines (Core Tier 1, 6 hours)
• AR/Digital Logic and Digital Systems (Core Tier 2, 3 hours)
• AR/Machine level representation of data (Core Tier 2, 3 hours)
• AR/Assembly level machine organization (Core Tier 2, 6 hours)
• AR/Memory system organization and Architecture (Core Tier 2, 3 hours)
• AR/Interfacing and Communication (Core Tier 2, 1 hour)
• PD/Parallel Architecture (Core Tier 1+2, 3 hours)
SF/Parallelism (Core Tier 1, 1 hour)

SF/Evaluation (Core Tier 1, 3 hours)



Lahore University of Management Sciences
Grading Breakup and Policy

Attendance: 10% (Excluding first two classes and both exams, 10 marks for attending all 24 classes, 8 for 23, 6 for 22, 4 for 21, 2 for 20, and 0 for
attending less than 20 classes. Coming after 5 minutes of class start or leaving before the end of the class counts as absence. For genuine reasons,
you may check with me before missing a class, but in most cases, I’ll refer you to OSA for verification.)
Assignments: 20% (Tentatively 7 assignments of 4 marks each but maximum marks in assignments category cannot be more than 20. Thus, you
can get full assignment marks by finishing 5 assignments perfectly or by doing a good part of all 7 assignments. Getting perfect score is hard so do
not skip assignments. Plagiarism cases are forwarded to DC without warning. Late submissions even by a second are not accepted.)
Mid-term: 20% + 20%
Final: 30% (Comprehensive)


Examination Detail
Midterm Yes/No: Yes (Two)
Exams Duration: 100 minutes (In class timings)
Yes/No: Yes
Final Exam Duration: 3 hours

Tentative Schedule
Session Topics
1 Introduction (Ch 1)
2 Information Storage (Ch 2.1-2.2)
3 Integer operations (Ch 2.3)
4 Floating point operations (Ch 2.4)
5 Program encodings (Ch 3.1-3.3)
6 Data movement and arithmetic (Ch 3.4-3.5)
7 Control flow (Ch 3.6)
8 Procedures (Ch 3.7)
9 Arrays and structures (Ch 3.8-3.9)
10 Buffer overflow (Ch 3.10)
11 Exam 1
12 Instruction set architecture (Ch 4.1)
13 Logic Design (Ch 4.2)
14 Logic Design & Verilog (Ch 4.2)
15 Sequential processor design (Ch 4.3)
16 Sequential processor details (Ch 4.3)
17 Pipelining (Ch 4.4)
18 Pipelined processor design (Ch 4.5)
19 Stalls and Bubbles (Ch 4.5)
20 Exam 2
21 Memory Hierarchy and locality of reference (Ch 6.1-6.3)
22 Introduction to cache design (Ch 6.4)
23 Cache friendly code (Ch 6.5-6.6)
24 Linking and loading programs (Ch 7.1-7.9)
25 Interrupts and hardware interfacing (Ch 8.1)
26 Processes (Ch 8.2-8.4)
27 Dynamic memory allocation and garbage collection (Ch 9.9-9.10)
28 Memory related bugs (Ch 9.11)

Textbook(s)/Supplementary Readings

Computer Systems, A Programmer's Perspective by Randal E. Bryant and David O'Hallaron, Prentice Hall, 2016 (Third Edition)

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