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Vlsi Testing Workshop

This document provides information about an upcoming short course on VLSI Testing. The course will cover topics related to VLSI design flow and testing, including silicon defects in integrated circuits, design-for-test pattern generation, static timing analysis, and digital design-for-test. The objective is to analyze real silicon defects using scanning electron microscope images and understand techniques for modeling defects into faults. The course aims to help participants understand challenges with defects in modern FinFET and emerging GAA technologies. It will provide both lectures and hands-on sessions, with certificates awarded by the Electronics and ICT Academy at IIT Roorkee.

Uploaded by

Pankaj Naik
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
22 views

Vlsi Testing Workshop

This document provides information about an upcoming short course on VLSI Testing. The course will cover topics related to VLSI design flow and testing, including silicon defects in integrated circuits, design-for-test pattern generation, static timing analysis, and digital design-for-test. The objective is to analyze real silicon defects using scanning electron microscope images and understand techniques for modeling defects into faults. The course aims to help participants understand challenges with defects in modern FinFET and emerging GAA technologies. It will provide both lectures and hands-on sessions, with certificates awarded by the Electronics and ICT Academy at IIT Roorkee.

Uploaded by

Pankaj Naik
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Why VLSI Testing?

Focus Areas
 Short Course/FDP Today’s IC design involves dealing with complex Introduction to VLSI design flow and testing
on VLSI systems and increasingly large number of
design constraints. Modern technology demands
philosophy.
Silicon defects in commercial integrated
" VLSI Testing " techniques for efficiently designing high- circuits.
performance low-power integrated circuits Translating silicon physical defects into fault
Under the aegis of while requirements for shorter time-to-market models.
push down the design time. Apart from design Design-for-test pattern generation and
Electronics & ICT Academy cycle time reduction, these circuits demand verification.
technology scaling from planar to 3D FinFETs
IIT Roorkee structure to improve transistor propagation
Small delay defects and timing critical paths.
Static timing analysis and its fundamentals.
delay and associated static/dynamic power.
Pits and falls in state-of-art STA techniques
Technology scaling beyond 28nm node comes
and proposed solution.
with a penalty of more number of localized
physical defects in the silicon during Digital design-for-test (DFT) and Scan design.
manufacturing. Typically, such defects originate Basic of memory testing.
from spatial and temporal statistical variations Save energy by allow errors in computing.
in the circuit. This course will help the
participants to understand, why such defects Benefits and Outcomes of the Course
are growing concern in current FinFET and
The course will help students to get acquaint
emerging gate all around (GAA) technologies. We
to industry’s state-of-the-art VLSI design
Recognized by AICTE at par with will discuss and analyze the real silicon defects
QIP for recognitions/credits using scanning electron microscope (SEM) flow, help researchers to foresee various
images, taken from commercial ICs. research problems that can be pursued to fix
practical testing problems and help faculty to
April 26-28, 2019 Objective of the Course adopt new techniques that must be included
To discuss and analyze the real silicon defects in their respective courses of basic
Experts from Academia/Industry using scanning electron microscope (SEM)
electronics, VLSI design, CAD tools and digital
images, taken from commercial ICs.
Dr. Ankush Srivastava Dr. Anand Bulusu Understand the  techniques of modelling a integrated circuit design. 
Qualcomm India Pvt. IIT Roorkee defect into fault that can be used to generate
test patterns.
Ltd, Bengaluru Introduction of static timing analysis (STA)
Supported by fundamentals like setup, hold, slack, arrival
time, slack merging etc, with an aim to root-
Ministry of Electronics & Information cause the underneath problem during circuit
Technology timing.
Government  of India Program Features
The program is split into lectures and labs/hands-
Certificates to participants by on sessions.
E&ICT Academy IIT Roorkee Hands-on experience on basic and advanced-level
topics. Coordinator
Interaction & learning with experts from academia Dr. Sanjeev Manhas, Principal Investigator
Venue
& industry. E&ICT Academy IIT Roorkee
E&ICT Smart Classroom(N-316), ECE Certificates to participants by E&ICT Academy IIT Dr. Anand Bulusu, Co-PI, Local
Department IIT Roorkee Roorkee. Coordinator, E&ICT Academy IIT Roorkee
Who Can Attend ? EICT Academy IITR Short Course/FDP
Program is open to faculty members/research on
Electronics and ICT Academy (E&ICT) at IIT
scholars/PG students from colleges/universities,
Roorkee (funded by Ministry of Electronics and VLSI Testing
and industry personnel working in the
Information Technology) aims to enrich and
concerned/allied discipline.
upgrade teaching and research competences of
Registration Fee engineering faculties of institutes/colleges by
 Faculty members: ₹ 1,000/- conducting courses and workshops in REGISTRATION FORM

Research scholars: ₹ 1,000/- fundaments as well as emerging areas of E&ICT


Persons from Industry: ₹ 1,500/- Applicant Name ______________________________
and enabled areas. The programs are
Gender:__________________________________________
How to make payment conducted by well-known industry partners,
Category (GEN/OBC/SC/ST): _____________
resource persons from leading academia and
Offline: DD in favor of "Dean SRIC IIT Roorkee" Designation: __________________________________
experts from renowned R&D organizations.
payable at Roorkee Name and Address of the
"OR" Organizatio/Institute: _____________________
Online: ( https://www.onlinesbi.com/prelogin
/icollecthome.htm?corpID=365641 ) ____________________________________________________
Read the instruction for payment before filling ____________________________________________________
the online registration form. City/Town: ____________________________________
Email: __________________________________________
How to Apply Phone Number: ______________________________
Step 1: Participants may fill the registration form  Do you need Accommodation?
   available on the link "Register Online" for the (Yes/No):______________________________________
relevant course on eict.iitr.ac.in DD Number:__________________________________
Step 2: Make Payment                                               Activities of the Academy Date: __________________________________________
OR Issuing  Bank:_______________________________
Step 3: Send a duly filled-in registration form Specialized training on basic and advanced Payable at: __________________________________
along with Demand Draft to Academy address. level topics with hands-on experience in the                 
Mr. Prateek Sharma, EICT Academy, ECE emerging areas of Electronics & ICT. Signature of the Applicant
Department, IIT Roorkee-247667
Setup the activity centers to conduct short
Important Dates Contact Us
courses/FDPs locally at institutes/colleges.
Curriculum development for the industry.
Electronics and ICT Academy, IIT Roorkee
Last Date For Online Continuing Education Programme for
Roorkee - 247667, (Uttarakhand) INDIA
students/working professionals.
Registration : Design, develop and delivery of specialized
Ph. +91-1332-28 6457, +91-7078627392
April 15, 2019 Email: eict@iitr.ac.in, eictiitr@gmail.com
modules for specific research areas in
Website: http://eict.iitr.ac.in
industry.

/eict.iitr /eictiitr

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