Vlsi Testing Workshop
Vlsi Testing Workshop
Focus Areas
Short Course/FDP Today’s IC design involves dealing with complex Introduction to VLSI design flow and testing
on VLSI systems and increasingly large number of
design constraints. Modern technology demands
philosophy.
Silicon defects in commercial integrated
" VLSI Testing " techniques for efficiently designing high- circuits.
performance low-power integrated circuits Translating silicon physical defects into fault
Under the aegis of while requirements for shorter time-to-market models.
push down the design time. Apart from design Design-for-test pattern generation and
Electronics & ICT Academy cycle time reduction, these circuits demand verification.
technology scaling from planar to 3D FinFETs
IIT Roorkee structure to improve transistor propagation
Small delay defects and timing critical paths.
Static timing analysis and its fundamentals.
delay and associated static/dynamic power.
Pits and falls in state-of-art STA techniques
Technology scaling beyond 28nm node comes
and proposed solution.
with a penalty of more number of localized
physical defects in the silicon during Digital design-for-test (DFT) and Scan design.
manufacturing. Typically, such defects originate Basic of memory testing.
from spatial and temporal statistical variations Save energy by allow errors in computing.
in the circuit. This course will help the
participants to understand, why such defects Benefits and Outcomes of the Course
are growing concern in current FinFET and
The course will help students to get acquaint
emerging gate all around (GAA) technologies. We
to industry’s state-of-the-art VLSI design
Recognized by AICTE at par with will discuss and analyze the real silicon defects
QIP for recognitions/credits using scanning electron microscope (SEM) flow, help researchers to foresee various
images, taken from commercial ICs. research problems that can be pursued to fix
practical testing problems and help faculty to
April 26-28, 2019 Objective of the Course adopt new techniques that must be included
To discuss and analyze the real silicon defects in their respective courses of basic
Experts from Academia/Industry using scanning electron microscope (SEM)
electronics, VLSI design, CAD tools and digital
images, taken from commercial ICs.
Dr. Ankush Srivastava Dr. Anand Bulusu Understand the techniques of modelling a integrated circuit design.
Qualcomm India Pvt. IIT Roorkee defect into fault that can be used to generate
test patterns.
Ltd, Bengaluru Introduction of static timing analysis (STA)
Supported by fundamentals like setup, hold, slack, arrival
time, slack merging etc, with an aim to root-
Ministry of Electronics & Information cause the underneath problem during circuit
Technology timing.
Government of India Program Features
The program is split into lectures and labs/hands-
Certificates to participants by on sessions.
E&ICT Academy IIT Roorkee Hands-on experience on basic and advanced-level
topics. Coordinator
Interaction & learning with experts from academia Dr. Sanjeev Manhas, Principal Investigator
Venue
& industry. E&ICT Academy IIT Roorkee
E&ICT Smart Classroom(N-316), ECE Certificates to participants by E&ICT Academy IIT Dr. Anand Bulusu, Co-PI, Local
Department IIT Roorkee Roorkee. Coordinator, E&ICT Academy IIT Roorkee
Who Can Attend ? EICT Academy IITR Short Course/FDP
Program is open to faculty members/research on
Electronics and ICT Academy (E&ICT) at IIT
scholars/PG students from colleges/universities,
Roorkee (funded by Ministry of Electronics and VLSI Testing
and industry personnel working in the
Information Technology) aims to enrich and
concerned/allied discipline.
upgrade teaching and research competences of
Registration Fee engineering faculties of institutes/colleges by
Faculty members: ₹ 1,000/- conducting courses and workshops in REGISTRATION FORM
/eict.iitr /eictiitr