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    BCD Adder

    Uploaded by

    Novel Patel
    This document describes Novel Patel's experiment on designing and implementing a 4-bit binary adder and subtractor as well as a BCD adder using VHDL. It includes the VHDL code for a BCD adder module and a test bench module to test the BCD adder. The test bench applies inputs to the BCD adder unit under test and observes the output.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    BCD Adder

    Uploaded by

    Novel Patel
    331 views4 pages
    This document describes Novel Patel's experiment on designing and implementing a 4-bit binary adder and subtractor as well as a BCD adder using VHDL. It includes the VHDL code for a BCD adder module and a test bench module to test the BCD adder. The test bench applies inputs to the BCD adder unit under test and observes the output.

    Original Title

    BCD ADDER.docx

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    This document describes Novel Patel's experiment on designing and implementing a 4-bit binary adder and subtractor as well as a BCD adder using VHDL. It includes the VHDL code for a BCD adder module and a test bench module to test the BCD adder. The test bench applies inputs to the BCD adder unit under test and observes the output.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    331 views4 pages

    BCD Adder

    Uploaded by

    Novel Patel
    This document describes Novel Patel's experiment on designing and implementing a 4-bit binary adder and subtractor as well as a BCD adder using VHDL. It includes the VHDL code for a BCD adder module and a test bench module to test the BCD adder. The test bench applies inputs to the BCD adder unit under test and observes the output.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 4

    EXPERIMENT NO: 4 NAME:NOVEL PATEL

    DATE:29\8\2018 ROLL NO:1704094

    DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDER AND SUBTRACTOR AND


    BCD ADDER

    VHDL MODULE:

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    use IEEE.STD_LOGIC_arith.ALL;

    use IEEE.STD_LOGIC_unsigned.ALL;

    use IEEE.NUMERIC_STD.ALL;

    entity bcdadd is

    Port ( x : in STD_LOGIC_VECTOR (3 downto 0);

    y : in STD_LOGIC_VECTOR (3 downto 0);

    s : out STD_LOGIC_VECTOR (4 downto 0));

    end bcdadd;

    architecture Behavioral of bcdadd is

    signal z : std_logic_vector(4 downto 0);

    signal adjust : std_logic;

    begin

    z<=('0'& x)+y;

    adjust<= '0' when z<9 else '1';

    s<= z when (adjust ='0') else z+6;

    end Behavioral;
    EXPERIMENT NO: 4 NAME:NOVEL PATEL
    DATE:29\8\2018 ROLL NO:1704094

    DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDER AND SUBTRACTOR AND


    BCD ADDER

    VHDL TEST BENCH:


    LIBRARY ieee;

    USE ieee.std_logic_1164.ALL;

    -- Uncomment the following library declaration if using

    -- arithmetic functions with Signed or Unsigned values

    --USE ieee.numeric_std.ALL;

    ENTITY bcd_tb IS

    END bcd_tb;

    ARCHITECTURE behavior OF bcd_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT bcdadd

    PORT(

    x : IN std_logic_vector(3 downto 0);

    y : IN std_logic_vector(3 downto 0);

    s : OUT std_logic_vector(4 downto 0)

    );

    END COMPONENT;

    --Inputs

    signal x : std_logic_vector(3 downto 0) := (others => '0');

    signal y : std_logic_vector(3 downto 0) := (others => '0');

    --Outputs

    signal s : std_logic_vector(4 downto 0);

    -- No clocks detected in port list. Replace <clock> below with

    -- appropriate port name

    BEGIN

    -- Instantiate the Unit Under Test (UUT)

    uut: bcdadd PORT MAP (


    EXPERIMENT NO: 4 NAME:NOVEL PATEL
    DATE:29\8\2018 ROLL NO:1704094

    DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDER AND SUBTRACTOR AND


    BCD ADDER

    x => x,

    y => y,

    s => s

    );

    -- Clock process definitions

    -- <clock>_process :process

    -- begin

    --<clock> <= '0';

    --wait for <clock>_period/2;

    --<clock> <= '1';

    --wait for <clock>_period/2;

    -- end process;

    x(3)<= not x(3) after 3200 ns;

    x(2)<= not x(2) after 1600 ns;

    x(1)<= not x(1) after 800 ns;

    x(0)<= not x(0) after 400 ns;

    y(3)<= not y(3) after 200 ns;

    y(2)<= not y(2) after 100 ns;

    y(1)<= not y(1) after 50 ns;

    y(0)<= not y(0) after 20 ns;

    -- Stimulus process

    -- stim_proc: process

    -- begin

    -- -- hold reset state for 100 ns.

    -- wait for 100 ns;

    -- wait for <clock>_period*10;

    -- -- insert stimulus here -- wait; -- end process; END;


    EXPERIMENT NO: 4 NAME:NOVEL PATEL
    DATE:29\8\2018 ROLL NO:1704094

    DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDER AND SUBTRACTOR AND


    BCD ADDER

    OUTPUT WAVEFORM:

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