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    Nand

    Uploaded by

    rakeshkamasani123
    The document describes the design and implementation of a 3-input NAND gate using Xilinx ISE software and VHDL. It provides steps to create a new project in ISE, develop the VHDL code for the NAND gate, synthesize and view the schematic, and develop a test bench program to simulate and verify the output waveforms.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Nand

    Uploaded by

    rakeshkamasani123
    8 views5 pages
    The document describes the design and implementation of a 3-input NAND gate using Xilinx ISE software and VHDL. It provides steps to create a new project in ISE, develop the VHDL code for the NAND gate, synthesize and view the schematic, and develop a test bench program to simulate and verify the output waveforms.

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    Nand program

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    nand

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    The document describes the design and implementation of a 3-input NAND gate using Xilinx ISE software and VHDL. It provides steps to create a new project in ISE, develop the VHDL code for the NAND gate, synthesize and view the schematic, and develop a test bench program to simulate and verify the output waveforms.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    8 views5 pages

    Nand

    Uploaded by

    rakeshkamasani123
    The document describes the design and implementation of a 3-input NAND gate using Xilinx ISE software and VHDL. It provides steps to create a new project in ISE, develop the VHDL code for the NAND gate, synthesize and view the schematic, and develop a test bench program to simulate and verify the output waveforms.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 5

    AIM: Design and Implementation of an universal gates by using Xilinx ISE.

    APPARATUS: Personal Computer

    Xilinx ISE software

    VHDL

    1. Open Xilinx ISE software.


    2. Click on file and go to new project.
    3. Enter file name (nand3) and click on next button.
    4. Select the preferred language as VHDL and click on next and finish.
    5. Right Click on project folder and go to new source and select VHDL module, enter file
    name and click on next.
    6. Give input and output variables and click on finish.
    7. Enter the program and save it.
    8. Go to synthesize XST folder and double click on check syntax.
    9. Once the syntax is completed successfully then click on RTL schematic and click on OK
    button.
    10. Check the schematic diagram of logic gate.

    Library IEEE;

    Use IEEE.STD_LOGIC_1164.ALL;

    -- Uncomment the following library declaration if using

    -- arithmetic functions with Signed or Unsigned values

    --use IEEE.NUMERIC_STD.ALL;

    -- Uncomment the following library declaration if instantiating

    -- any Xilinx primitives in this code.

    --library UNISIM;

    --use UNISIM.VComponents.all;

    entity nand3 is

    Port ( a : in STD_LOGIC;

    b : in STD_LOGIC;

    c : out STD_LOGIC);

    end nand3;
    architecture Behavioral of nand3 is

    begin

    c<= a nand b;

    end Behavioral;

    DIAGRAM

    TEST BENCH PROCEDURE

    1. Click on simulation and right click behaviour model source and select new source.
    2. Select VHDL test bench, enter the file name with tbw extension (nand3_tbw) and click on
    next, finish.
    3. Enter the program with input conditions by taking 100 ns as the time period.
    4. Comment the clock instructions in the whole program and save it.
    5. Click on behavioural model and click check syntax.
    6. Click Simulate the behavioural model and verify the output waveforms.

    TEST BENCH PROGRAM


    LIBRARY ieee;

    USE ieee.std_logic_1164.ALL;

    -- Uncomment the following library declaration if using

    -- arithmetic functions with Signed or Unsigned values

    --USE ieee.numeric_std.ALL;

    ENTITY nand3_tbw IS

    END nand3_tbw;

    ARCHITECTURE behavior OF nand3_tbw IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT nand3

    PORT(

    a : IN std_logic;

    b : IN std_logic;

    c : OUT std_logic

    );

    END COMPONENT;

    --Inputs

    signal a : std_logic := '0';

    signal b : std_logic := '0';

    --Outputs

    signal c : std_logic;

    -- No clocks detected in port list. Replace <clock> below with

    -- appropriate port name


    -- constant <clock>_period : time := 10 ns;

    BEGIN

    -- Instantiate the Unit Under Test (UUT)

    uut: nand3 PORT MAP (

    a => a,

    b => b,

    c => c

    );

    -- Clock process definitions

    -- <clock>_process :process

    -- begin

    -- <clock> <= '0';

    -- wait for <clock>_period/2;

    -- <clock> <= '1';

    -- wait for <clock>_period/2;

    -- end process;

    --

    -- Stimulus process

    stim_proc: process

    begin

    a<='0';

    b<='0';

    -- hold reset state for 100 ns.

    wait for 100 ns;

    a<='0';

    b<='1';
    -- hold reset state for 100 ns.

    wait for 100 ns;

    a<='1';

    b<='0';

    -- hold reset state for 100 ns.

    wait for 100 ns;

    a<='1';

    b<='1';

    -- hold reset state for 100 ns.

    wait for 100 ns;

    -- wait for <clock>_period*10;

    -- insert stimulus here

    wait;

    end process;

    END;

    RESULT

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