NAME : A.

VINEELA REDDY DATE:

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EXPERIMENT NO: 1
HDL CODE TO REALIZE ALL THE LOGIC GATES

AIM:
To realize all the logic gates (NOT, AND, OR, NOR, NAND, EXOR, EXNOR) using Verilog HDL code
and also verify the outputs

REQUIREMENTS:
Software required: Vivado
Hardware required: PC, Zed Board

THEORY:
A Logic Gate is an idealized or physical device implementing a Boolean function, that is, it performs
logical operations on one or more logical inputs and produces a single logical output. Basic gates include
logic gates and universal gates. Basic Logic gates are of three types: NOT Gate, AND Gate, and OR Gate.
Universal gates are: NAND Gate, and NOR Gate. And there are other gates like EXOR and EXNOR
Gates. In most logic gates, the low state is approximately zero volts (0 V), while the high state is
approximately five volts positive (+5 V). Logic circuits are found in several devices including
multiplexers, arithmetic logic units, computer memory, registers, microprocessors, which can contain over
100 million gates.

PROGRAM:
module gates( //initializing the variable list to be used in the program
input a, //initializing the input variable ‘a’
input b, //initializing the input variable ‘b’
output c, //initializing the output variable ‘c’
output d, //initializing the output variable ‘d’
output e, //initializing the output variable ‘e’
output f, //initializing the output variable ‘f’
output g, //initializing the output variable ‘g’
output h, //initializing the output variable ‘h’
output i ); //initializing the output variable ‘i’
assign c=~a; //assigning ‘c’ value (NOT)
assign d=a|b; //assigning ‘d’ value (OR)
assign e=a&b; //assigning ‘e’ value (AND)
assign f=~(a|b); //assigning ‘f’ value (NOR)
assign g=~(a&b); //assigning ‘g’ value (NAND)
assign h=a^b; //assigning ‘h’ value (EX-OR)
assign i=~(a^b); //assigning ‘i’ value (EX-NOR)
endmodule //end of the verilog HDL program

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TEST BENCH:
module gates_sim;
reg a,b;
wire c,d,e,f,g,h,i;
gates uut(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.i(i));
initial
begin
a=1'b0;b=1'b0;#100
a=1'b0;b=1'b1;#100
a=1'b1;b=1'b0;#100
a=1'b1;b=1'b1;
end
endmodule

RTL SCHEMATIC:

SIMULATION RESULT:

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CONSTRAINTS:
set_property PACKAGE_PIN F22 [get_ports a]
set_property PACKAGE_PIN G22 [get_ports b]
set_property PACKAGE_PIN T22 [get_ports c]
set_property PACKAGE_PIN T21 [get_ports d]
set_property PACKAGE_PIN U22 [get_ports e]
set_property PACKAGE_PIN U21 [get_ports f]
set_property PACKAGE_PIN V22 [get_ports g]
set_property PACKAGE_PIN W22 [get_ports h]
set_property PACKAGE_PIN V19 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports a]
set_property IOSTANDARD LVCMOS33 [get_ports b]
set_property IOSTANDARD LVCMOS33 [get_ports c]
set_property IOSTANDARD LVCMOS33 [get_ports e]
set_property IOSTANDARD LVCMOS33 [get_ports d]
set_property IOSTANDARD LVCMOS33 [get_ports f]
set_property IOSTANDARD LVCMOS33 [get_ports g]
set_property IOSTANDARD LVCMOS33 [get_ports h]
set_property IOSTANDARD LVCMOS33 [get_ports i]

PROCEDURE:
1. Open Xilinx Vivado software tool and click on the New Project.
2. Now select the Language i.e. Verilog HDL and proceed to next.
3. Now add the constraints, inputs & outputs for the design level.
4. Next, give a name for the program and save the file.
5. Now select a board from the Zed Board family.
6. A file will be created, then write the required program and save the file.
7. If no errors are present then, go to system file and add a new source for test bench.
8. In the test bench file save it’s with extension _sim. Now write the test bench program and
9. save it.
10. Now run the synthesis, if no errors are present, output is obtained on RTL schematic.
11. Now run the behavioral simulation for output waveform.
12. Now run the implementation and generate bit stream .
13. Connect the hardware and select the target device. Now add the constraints file with _con
14. extension.
15. Now dump the bit stream into the hardware using program option.

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PROJECT SUMMARY:

ZED BOARD IMPLEMENTATION:

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HT N0.: 16H61A04C6 PAGE NO.:

RESULT:
Implementation of all logic gates is performed in Zed Board using HDL in Data Flow Model and the
outputs are verified. Here, we used two input pins and seven output pins and the IOS standard
LVCMOS33.

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EXPERIMENT NO: 2
DESIGN OF 3-8 DECODER USING 2-4 DECODER

AIM:
To design 3-8 Decoder using two 2-4 decoders using Verilog HDL code and also verify the outputs

REQUIREMENTS:
Software required: Vivado
Hardware required: PC, Zed Board

THEORY:
In digital electronics, a binary decoder is a combinational logic circuit that converts binary information
from the n coded inputs to a maximum of 2n unique outputs. They are used in a wide variety of
applications, including data demultiplexing, seven segment displays, and memory address decoding. There
are several types of binary decoders, but in all cases a decoder is an electronic circuit with multiple input
and multiple output signals, which converts every unique combination of input states to a specific
combination of output states. In addition to integer data inputs, some decoders also have one or more
"enable" inputs. When the enable input is negated (disabled), all decoder outputs are forced to their
inactive states.
Depending on its function, a binary decoder will convert binary information from n input signals to as
many as 2n unique output signals. Some decoders have less than 2n output lines; in such cases, at least one
output pattern may be repeated for different input values. Widely used decoders are often available in the
form of standardized ICs.

PROGRAM:
module decoders24( //initializing the variable list to be used in the program
input [1:0]i, //initializing the input variable ‘i’
input en, //initializing the input variable ‘en’
output [3:0]o ); //initializing the output variable ‘o’
assign o[0]=(~i[0])&(~i[1]); //assigning o[0] value
assign o[1]=(i[0])&(~i[1]); //assigning o[1] value
assign o[2]=(~i[0])&(i[1]); //assigning o[2] value
assign o[3]=(i[0])&(i[1]); //assigning o[3] value
endmodule //end of the verilog HDL program

module decoders38(i,o); //initializing the variable list to be used in the program

input [2:0]i; //initializing the input variable ‘i’
output [7:0]o; //initializing the output variable ‘o’
wire x; //initializing wire variable
not n1(x,i[2]); //assigning ‘x’ value

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TEST BENCH:
module decoders_sim;
reg [2:0]i;
wire [7:0]o;
decoders38 uut(.i(i),.o(o));
initial
begin
i=3'b000;#100
i=3'b001;#100
i=3'b010;#100
i=3'b100;#100
i=3'b101;#100
i=3'b110;#100
i=3'b111;
end
endmodule

RTL SCHEMATIC:

SIMULATION RESULT:

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decoders24 d1(i[1:0],x,o[3:0]); //calling decoders24 module

decoders24 d2(i[1:0],i[2],o[7:4]); //calling decoders24 module
endmodule //end of the verilog HDL program

CONSTRAINTS:
set_property PACKAGE_PIN F22 [get_ports {i[2]}]
set_property PACKAGE_PIN G22 [get_ports {i[1]}]
set_property PACKAGE_PIN F21 [get_ports {i[0]}]
set_property PACKAGE_PIN T22 [get_ports {o[7]}]
set_property PACKAGE_PIN U22 [get_ports {o[6]}]
set_property PACKAGE_PIN U21 [get_ports {o[5]}]
set_property PACKAGE_PIN V22 [get_ports {o[4]}]
set_property PACKAGE_PIN W22 [get_ports {o[3]}]
set_property PACKAGE_PIN V19 [get_ports {o[2]}]
set_property PACKAGE_PIN V14 [get_ports {o[1]}]
set_property PACKAGE_PIN T21 [get_ports {o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[0]}]

PROCEDURE:
1. Open Xilinx Vivado software tool and click on the New Project.
2. Now select the Language i.e. Verilog HDL and proceed to next.
3. Now add the constraints, inputs & outputs for the design level.
4. Next, give a name for the program and save the file.
5. Now select a board from the Zed Board family.
6. A file will be created, then write the required program and save the file.
7. If no errors are present then, go to system file and add a new source for test bench.
8. In the test bench file save it’s with extension _sim. Now write the test bench program and
9. save it.
10. Now run the synthesis, if no errors are present, output is obtained on RTL schematic.
11. Now run the behavioral simulation for output waveform.
12. Now run the implementation and generate bit stream .
13. Connect the hardware and select the target device. Now add the constraints file with _con
14. extension.
15. Now dump the bit stream into the hardware using program option.

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NAME : A.VINEELA REDDY DATE:
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PROJECT SUMMARY:

ZED BOARD IMPLEMENTATION:

ANURAG GROUP OF INSTITUTIONS DEPARTMENT OF ECE VLSI LAB

NAME : A.VINEELA REDDY DATE:
HT N0.: 16H61A04C6 PAGE NO.:

RESULT:
The Design of 3-8 Decoder using 2-4 decoder is performed in Zed Board using HDL in Gate
Level and the outputs are verified. Here, we used three input pins and eight output pins with IOS
standard LVCMOS33.

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EXPERIMENT NO: 3
DESIGN OF 8-3 ENCODER (WITHOUT AND WITH PARITY)

AIM:
To design 8-3 encoder for without and with parity using Verilog HDL code and also verify the outputs

REQUIREMENTS:
Software required: Vivado
Hardware required: PC, Zed Board

THEORY:
An Encoder is a combinational circuit that performs the reverse operation of Decoder.It has maximum
of 2^n input lines and ‘n’ output lines, hence it encodes the information from 2^n inputs into an n-bit code.
It will produce a binary code equivalent to the input, which is active High. Therefore, the encoder encodes
2^n input lines with ‘n’ bits.
If the input circuit can guarantee at most a single-active input, a simple encoder is a better choice than
a priority encoder, since it requires less logic to implement but if not this become the major disadvantage
of simple encoder that is they can generate the wrong output when there is more than one input present in
a high state (logic state “1”). To rectify this problem a Priority encoder is used. They act on the request of
higher priority and the rest cases go in "don't care condition".
Types of encoders:
4:2 encoder,
8:3 encoder,
16:4 encoders etc.
8 : 3 Encoder (Octal to Binary):
The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs: Y7 to Y0 and 3 outputs: A2, A1 & A0.
Each input line corresponds to each octal digit and three outputs generate corresponding binary code.

PROGRAM: (without parity):

module encoders( //initializing the variable list to be used in the program
input [7:0]i, //initializing the input variable ‘i’
input en, //initializing the input variable ‘en’
output [2:0]o ); //initializing the output variable ‘o’
reg [2:0]o; //register variables
always@(i,en) //always inputs
begin //beginning of block
if(en==1) //if condition

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TEST BENCH:
Without Parity:
module encoders_sim;
reg [7:0]i;
reg en;
wire [2:0]o;
encoders uut(.i(i),.en(en),.o(o));
initial
begin
i=8'b00011001;en=1'b0;#100
i=8'b00000001;en=1'b1;#100
i=8'b00000010;en=1'b1;#100
i=8'b00000100;en=1'b1;#100
i=8'b00001000;en=1'b1;#100
i=8'b00010000;en=1'b1;#100
i=8'b00100000;en=1'b1;#100
i=8'b01000000;en=1'b1;#100
i=8'b10000000;en=1'b1;
end
endmodule

With Parity:
module enparity_sim();
reg[7:0]i;
wire[2:0]y;
parity uut(.i(i),.y(y));
initial
begin
i=8'b10000011;#10
i=8'b01000011;#10
i=8'b00100011;#10
i=8'b00010011;#10
i=8'b00001011;#10
i=8'b00000111;#10
i=8'b00000010;#10
i=8'b00000001;
end
endmodule

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begin //beginning of if condition

case(i) //case begin
8'b00000001 : o=3'b000; //condition and output
8'b00000010 : o=3'b001; //condition and output
8'b00000100 : o=3'b010; //condition and output
8'b00001000 : o=3'b011; //condition and output
8'b00010000 : o=3'b100; //condition and output
8'b00100000 : o=3'b101; //condition and output
8'b01000000 : o=3'b110; //condition and output
8'b10000000 : o=3'b111; //condition and output
endcase //case end
end //end of if condition
else //else condition
o=3'b000; //output value
end //end of block
endmodule //end of the verilog HDL program

With Parity:
module parity( //initializing the variable list to be used in the program
input [7:0]i, //initializing the input variable ‘i’
output reg [2:0]y ); //initializing the output variable ‘o’
always@(i) //always inputs
begin //beginning of block
if(en==1) //if condition
begin //beginning of if condition
case(i) //case begin
8'b1xxxxxxx : o=3'b111; //condition and output
8'b01xxxxxx : o=3'b110; //condition and output
8'b001xxxxx : o=3'b101; //condition and output
8'b0001xxxx : o=3'b100; //condition and output
8'b00001xxx : o=3'b011; //condition and output
8'b000001xx : o=3'b010; //condition and output
8'b0000001x : o=3'b001; //condition and output
8'b00000001 : o=3'b000; //condition and output
default y=3'bxxxxxxxx; //default value
endcase //case end
end //end of block
endmodule //end of the verilog HDL program

CONSTRAINTS (without parity):

set_property PACKAGE_PIN P16 [get_ports {i[0]}]
set_property PACKAGE_PIN G22 [get_ports {i[1]}]
set_property PACKAGE_PIN H22 [get_ports {i[2]}]
set_property PACKAGE_PIN F21 [get_ports {i[3]}]
set_property PACKAGE_PIN H19 [get_ports {i[4]}]
set_property PACKAGE_PIN H18 [get_ports {i[5]}]

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RTL SCHEMATIC (without parity):

SIMULATION RESULT(without parity):

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set_property PACKAGE_PIN H17 [get_ports {i[6]}]

set_property PACKAGE_PIN M15 [get_ports {i[7]}]
set_property PACKAGE_PIN T22 [get_ports {o[0]}]
set_property PACKAGE_PIN T21 [get_ports {o[1]}]
set_property PACKAGE_PIN U22 [get_ports {o[2]}]
set_property PACKAGE_PIN F22 [get_ports en]
set_property IOSTANDARD LVCMOS33 [get_ports {i[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports en]

CONSTRAINTS (with parity):

set_property PACKAGE_PIN F22 [get_ports {i[7]}]
set_property PACKAGE_PIN G22 [get_ports {i[6]}]
set_property PACKAGE_PIN H22 [get_ports {i[5]}]
set_property PACKAGE_PIN F21 [get_ports {i[4]}]
set_property PACKAGE_PIN H19 [get_ports {i[3]}]
set_property PACKAGE_PIN H18 [get_ports {i[2]}]
set_property PACKAGE_PIN H17 [get_ports {i[1]}]
set_property PACKAGE_PIN H15 [get_ports {i[0]}]
set_property PACKAGE_PIN T22 [get_ports {y[2]}]
set_property PACKAGE_PIN T21 [get_ports {y[1]}]
set_property PACKAGE_PIN V22 [get_ports {y[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[0]}]

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RTL SCHEMATIC (with parity):

SIMULATION RESULT(with parity):

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NAME : A.VINEELA REDDY DATE:
HT N0.: 16H61A04C6 PAGE NO.:

PROCEDURE:
1. Open Xilinx Vivado software tool and click on the New Project.
2. Now select the Language i.e. Verilog HDL and proceed to next.
3. Now add the constraints, inputs & outputs for the design level.
4. Next, give a name for the program and save the file.
5. Now select a board from the Zed Board family.
6. A file will be created, then write the required program and save the file.
7. If no errors are present then, go to system file and add a new source for test bench.
8. In the test bench file save it’s with extension _sim. Now write the test bench program and
9. save it.
10. Now run the synthesis, if no errors are present, output is obtained on RTL schematic.
11. Now run the behavioral simulation for output waveform.
12. Now run the implementation and generate bit stream .
13. Connect the hardware and select the target device. Now add the constraints file with _con
14. extension.
15. Now dump the bit stream into the hardware using program option.

RESULT:
Implementation of 8-3 Encoder (with and without parity) is performed in Zed Board using HDL in
Behavioral Model and the outputs are verified. Here, we used eight input pins and three output pins
and the IOS standard LVCMOS33.

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PROJECT SUMMARY (without parity):

ZED BOARD IMPLEMENTATION (without parity):

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PROJECT SUMMARY (with parity):

ZED BOARD IMPLEMENTATION (with parity):

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EXPERIMENT NO: 4
DESIGN OF FULL ADDER USING 4 MODELING STYLES

AIM:
To design a Full Adder using 4 Modeling styles using Verilog HDL code and also verify the outputs and compare
them in different models.

REQUIREMENTS:
Software required: Vivado
Hardware required: PC, Zed Board

THEORY:
A full adder is a digital circuit that performs addition. Full adders are implemented with logic gates in
hardware. A full adder adds three one-bit binary numbers, two operands and a carry bit. The adder outputs
two numbers, a sum and a carry bit. The term is contrasted with a half adder, which adds two binary
digits.
A full adder takes two binary numbers plus a carry or overflow bit. The output is a sum and another carry
bit. Full adders are made from XOR, AND and OR gates in hardware. Full adders are commonly
connected to each other to add bits to an arbitrary length of bits, such as 32 or 64 bits. A full adder is
effectively two half adders, an XOR and an AND gate, connected by an OR gate.
We can also express it with (A ⊕ B) ⊕ Carry in.
Now, for the Carry out, it is A AND B OR Carry in (A XOR B), which is further represented by A.B +
(A ⊕ B).

PROGRAM:
a) Data Flow:
module fulladderd( //initializing the variable list to be used in the program
input a, //initializing the input variable ‘a’
input b, //initializing the input variable ‘b’
input c, //initializing the input variable ‘c’
output sum, //initializing the output variable ‘sum’
output cout ); //initializing the output variable ‘cout’
assign sum=a^b^c; //assigning ‘sum’ value
assign cout=(a&b)|(b&c)|(c&a); //assigning ‘cout’ value
endmodule //end of the verilog HDL program

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TEST BENCH:
module fulladder_sim;
reg a,b,c;
wire sum,cout;
fulladderd uut(.a(a),.b(b),.c(c),.sum(sum),.cout(cout));
initial
begin
a=1'b0;b=1'b0;c=1'b0;#100
a=1'b0;b=1'b0;c=1'b1;#100
a=1'b0;b=1'b1;c=1'b0;#100
a=1'b0;b=1'b1;c=1'b1;#100
a=1'b1;b=1'b0;c=1'b0;#100
a=1'b1;b=1'b0;c=1'b1;#100
a=1'b1;b=1'b1;c=1'b0;#100
a=1'b1;b=1'b1;c=1'b1;
end
endmodule

SIMULATION RESULT:

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b) Gate level:
module fulladderg( //initializing the variable list to be used in the program
input a, //initializing the input variable ‘a’
input b, //initializing the input variable ‘b’
input c, //initializing the input variable ‘c’
output sum, //initializing the output variable ‘sum’
output cout ); //initializing the output variable ‘cout’
wire x,y,z; //initializing the wire variables
xor x1(sum,a,b,c); //assigning ‘s’ value
and a1(x,a,b); //assigning ‘x’ value
and a2(y,b,c); //assigning ‘y’ value
and a3(z,c,a); //assigning ‘z’ value
or o1(cout,x,y,z); //assigning ‘c2’ value
endmodule //end of the verilog HDL program

c) Behavioral:
module fulladderg( //initializing the variable list to be used in the program
input a, //initializing the input variable ‘a’
input b, //initializing the input variable ‘b’
input c, //initializing the input variable ‘c’
output sum, //initializing the output variable ‘sum’
output cout ); //initializing the output variable ‘cout’
reg sum,cout; //initializing the register variables
always @(a,b,c) //initializing the always statement
begin //initializing the begin statement
case({a,b,c}) //operation of case statement
3'b000:begin sum=1’b0;cout=1’b0; end //declaring the conditions
3'b001:begin sum=1’b1;cout=1’b0; end //declaring the conditions
3'b010:begin sum=1’b1;cout=1’b0; end //declaring the conditions
3'b011:begin sum=1’b0;cout=1’b1; end //declaring the conditions
3'b100:begin sum=1’b1;cout=1’b0; end //declaring the conditions
3'b101:begin sum=1’b0;cout=1’b1; end //declaring the conditions
3'b110:begin sum=1’b0;cout=1’b1; end //declaring the conditions
3'b111:begin sum=1’b1;cout=1’b1; end //declaring the conditions
endcase //end of case statement
end //end of begin statement
endmodule //end of the verilog HDL program

d) Structural (Using MUX):

module mux( //initializing the variable list to be used in the program
output y, //initializing the output variable ‘y’
input i0, //initializing the input variable ‘i0’
input i1, //initializing the input variable ‘i1’
input i2, //initializing the input variable ‘12’

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RTL SCHEMATIC (data flow):

PROJECT SUMMARY (data flow):

RTL SCHEMATIC (gate level):

PROJECT SUMMARY (gate level):

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input i3, //initializing the input variable ‘i3’

input s0, //initializing the input variable ‘s0’
input s1, //initializing the input variable ‘s1’
wire x,y,w0,w1,w2,w3; //initializing the wire variables
assign x=~s1; //initializing the x value
assign y=~s0; //initializing the y value
assign w0=i0&x&y; //initializing the w0 value
assign w1=i1&x&s0; //initializing the w1 value
assign w2=i2&s1&y; //initializing the w2 value
assign w3=i3&s1&s0; //initializing the w3 value
assign y=w0|w1|w2|w3; //initializing the w0 value
endmodule //end of the verilog HDL program

CONSTRAINTS:
set_property PACKAGE_PIN F22 [get_ports a]
set_property PACKAGE_PIN G22 [get_ports b]
set_property PACKAGE_PIN H22 [get_ports c]
set_property PACKAGE_PIN T22 [get_ports cout]
set_property PACKAGE_PIN T21 [get_ports sum]
set_property IOSTANDARD LVCMOS33 [get_ports a]
set_property IOSTANDARD LVCMOS33 [get_ports b]
set_property IOSTANDARD LVCMOS33 [get_ports c]
set_property IOSTANDARD LVCMOS33 [get_ports cout]
set_property IOSTANDARD LVCMOS33 [get_ports sum]

PROCEDURE:
1. Open Xilinx Vivado software tool and click on the New Project.
2. Now select the Language i.e. Verilog HDL and proceed to next.
3. Now add the constraints, inputs & outputs for the design level.
4. Next, give a name for the program and save the file.
5. Now select a board from the Zed Board family.
6. A file will be created, then write the required program and save the file.
7. If no errors are present then, go to system file and add a new source for test bench.
8. In the test bench file save it’s with extension _sim. Now write the test bench program and
9. save it.
10. Now run the synthesis, if no errors are present, output is obtained on RTL schematic.
11. Now run the behavioral simulation for output waveform.
12. Now run the implementation and generate bit stream .
13. Connect the hardware and select the target device. Now add the constraints file with _con
.extension.
14. Now dump the bit stream into the hardware using program option.

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RTL SCHEMATIC (behavioral):

PROJECT SUMMARY (behavioral):

RTL SCHEMATIC (structural using MUX):

PROJECT SUMMARY (structural using MUX):

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RESULT:
Design of Full Adder is performed in Zed Board using HDL in all 4 Models and the outputs are
verified and compared. Here, we used three input pins and two output pins and the IOS standard
LVCMOS33.

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EXPERIMENT NO: 5
DESIGN OF A 4 BIT COUNTER
AIM:
To design & simulate a 4 bit counter using HDL code in vivado.

REQUIREMENTS:
Software required: Vivado
Hardware required: PC, Zed Board

THEORY:
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter.
Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied.
Counters are of two types.

 Asynchronous or ripple counters.

 Synchronous counters.

PROGRAM:
module counters(
input clk,
input m,
output reg [3:0]coun
);
initial coun=4'b0000;
always @(posedge clk)
begin
if(m==1)
coun <=coun+1'b1;
else
coun=coun-1'b1;
end
endmodule

CONSTRAINTS:

set_property IOSTANDARD LVCMOS33 [get_ports {cout[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {cout[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cout[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cout[0]}]

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TEST BENCH:
module counters_sim;
reg clk,m;
wire [3:0]coun;
counters uut(.clk(clk),.m(m),.coun(coun));
initial clk=1'b1;
always #10 clk=~clk;
initial
begin
m=1;#320
m=0;#100
m=1;
end
endmodule

RTL SCHEMATIC:

SIMULATION RESULT:

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set_property PACKAGE_PIN T22 [get_ports {cout[3]}]

set_property PACKAGE_PIN T21 [get_ports {cout[2]}]
set_property PACKAGE_PIN U22 [get_ports {cout[1]}]
set_property PACKAGE_PIN V22 [get_ports {cout[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports m]
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property PACKAGE_PIN F22[get_ports m]

PROCEDURE:
1. Open Xilinx Vivado software tool and click on the New Project.
2. Now select the Language i.e. Verilog HDL and proceed to next.
3. Now add the constraints, inputs & outputs for the design level.
4. Next, give a name for the program and save the file.
5. Now select a board from the Zed Board family.
6. A file will be created, then write the required program and save the file.
7. If no errors are present then, go to system file and add a new source for test bench.
8. In the test bench file save it’s with extension _sim. Now write the test bench program and
9. save it.
10. Now run the synthesis, if no errors are present, output is obtained on RTL schematic.
11. Now run the behavioral simulation for output waveform.
12. Now run the implementation and generate bit stream .
13. Connect the hardware and select the target device. Now add the constraints file with _con
.extension.
14. Now dump the bit stream into the hardware using program option.

RESULT:
Designed a 4 bit counter by writing a Verilog HDL code in behavioral model in Xilinx Vivado
No. of I/O ports used: 6
Input ports: 2 (Y9, F22)
Output ports: 4(T22, T21, U22, V22)
We used all the above ports to generate bit stream

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PROJECT SUMMARY:

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EXPERIMENT NO: 6
HDL CODE TO REALIZE SR, JK, T, D FLIPFLOPS
AIM:
To realize all flipflops namely, S-R, J-K, T and D by writing a HDL code in vivado.

REQUIREMENTS:
Software required: Vivado
Hardware required: PC, Zed Board

THEORY:
In electronics, a flipflop or a latch is a circuit that has two stable states and can be used to store state
information. The circuit can be made to change state by signals applied to one or more control inputs and
will have one or two outputs. It is the basic storage element in the sequential logic. Flip-flops and latches
are fundamental building blocks of digital electronic systems used in computers ,communications, and
many other type of systems . Flipflops and latches are used as data storage elements. There are 4 types of
flipflops:
1. S-R flipflop
2. J-k Flipflop
3. T-Flipflop
4. D-Flipflop

PROGRAM:
Program for S-R Flip flop (behavioral level)
module flip(q,qc,s,r,clk);
output reg q,qc;
input s;
input r;
input clk;
always@(posedge clk)
begin
case({s,r})
2'b00:begin q=q;qc=qc;end
2'b01:begin q=1'b0;qc=1'b1;end
2'b10:begin q=1'b1;qc=1'b0;end
2'b11:begin q=1'bz;qc=1'bz;end
endcase
end
endmodule

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TEST BENCH:
1) S-R FLIPFLOP:
module flip_tb;
reg s,r,clk;
wire q,qc;
flip uut(.q(q),.qc(qc),.s(s),.r(r),.clk(clk));
initial clk=1'b1;
always #10 clk=~clk;
initial
begin
s=0;r=1;#50
s=0;r=0;#50
s=1;r=0;#50
s=1;r=1;
end
endmodule

2) J-K FLIPFLOP:
module flip_tb;
reg j,k,clk;
wire q,qc;
jkflip uut(.q(q),.qc(qc),.j(j),.k(k),.clk(clk));
initial clk=1'b1;
always #10 clk=~clk;
initial
begin
j=0;k=1;#50
j=0;k=0;#50
j=1;k=0;#50
j=1;k=1;
end
endmodule

3) T-FLIPFLOP:
module flip_tb;
reg t,clk;
wire q,qc;
tflip uut(.q(q),.qc(qc),.t(t),.clk(clk));
initial clk=1'b1;
always #10 clk=~clk;
initial
begin
t=0;#50
t=1;

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Program for J-K Flip flop (behavioral level):

module jkflip(q,qc,j,k,clk);
output reg q,qc;
input j;
input k;
input clk;
always@(posedge clk)
begin
case({j,k})
2'b00:begin q=q;qc=qc;end
2'b01:begin q=1'b0;qc=1'b1;end
2'b10:begin q=1'b1;qc=1'b0;end
2'b11:begin q=~q;qc=~qc;end
endcase
end
endmodule

Program for T-flip flop (behavioral level):

module tflip(q,qc,t,clk);
output reg q;
output reg qc;
input t;
input clk;
initial
begin
q=1'b1;
qc=1'b0;
end
always@(posedge clk)
begin
if(clk)
begin
if(t==1'b0)begin q=q;qc=qc;end
else begin q=~q;qc=~qc;end
end
end
endmodule

Program for D flip flop (behavioral level):

module sdflip(q,qc,d,clk);
output reg q;
output reg qc;
input d;
input clk;
always@(posedge clk)
begin
case({d})
1'b0:begin q=d;qc=~d;end
1'b1:begin q=d;qc=~d;end
endcase

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end
endmodule

4) D-FLIPFLOP:
module flip_tb;
reg d,clk;
wire q,qc;
sdflip uut(.q(q),.qc(qc),.d(d),.clk(clk));
initial clk=1'b1;
always #10 clk=~clk;
initial
begin
d=0;#50
d=1;
end
endmodule

RTL SCHEMATIC:
1) S-R FLIPFLOP:

2) J-K FLIPFLOP:

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CONSTRAINT FILE:
FOR S-R:
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property PACKAGE_PIN T22 [get_ports q]
set_property PACKAGE_PIN T21 [get_ports qc]
set_property PACKAGE_PIN G22 [get_ports r]
set_property PACKAGE_PIN H22 [get_ports s]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports q]
set_property IOSTANDARD LVCMOS33 [get_ports qc]
set_property IOSTANDARD LVCMOS33 [get_ports r]
set_property IOSTANDARD LVCMOS33 [get_ports s]

FOR J-K:
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property PACKAGE_PIN T22 [get_ports q]
set_property PACKAGE_PIN T21 [get_ports qc]
set_property PACKAGE_PIN G22 [get_ports k]
set_property PACKAGE_PIN H22 [get_ports j]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports q]
set_property IOSTANDARD LVCMOS33 [get_ports qc]
set_property IOSTANDARD LVCMOS33 [get_ports k]
set_property IOSTANDARD LVCMOS33 [get_ports j]

FOR T-FLIPFLOP:

set_property PACKAGE_PIN Y9 [get_ports clk]

set_property PACKAGE_PIN T22 [get_ports q]
set_property PACKAGE_PIN T21 [get_ports qc]
set_property PACKAGE_PIN G22 [get_ports t]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports q]
set_property IOSTANDARD LVCMOS33 [get_ports qc]
set_property IOSTANDARD LVCMOS33 [get_ports t]

FOR D-FLIPFLOP:
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property PACKAGE_PIN T22 [get_ports q]
set_property PACKAGE_PIN T21 [get_ports qc]
set_property PACKAGE_PIN G22 [get_ports d]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports q]
set_property IOSTANDARD LVCMOS33 [get_ports qc]
set_property IOSTANDARD LVCMOS33 [get_ports d]

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3) T-FLIPFLOP:

4) D-FLIPFLOP:

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PROCEDURE:
1. Open the xilinx vivado software tool and click on the new project.
2. Now select the language i.e verilog HDL and proceed next
3. Now add the constraints, inputs& outputs for the design level.
4. Next, give a name for the program and save the file with extension of .v
5. Now select the board from the zed board family.
6. A file will be created, write the required program and save the file.
7. Similarly, write codes for full adder in gate, behavioral, structural, dataflow levels and select
one by one by clicking set as top and execute every file
8. If no errors are present then, go to system file and add a new source for test bench.
9. In the test bench file save it’s with extension _tb. Now write the test bench program and save
it.
10. Now run the synthesis, if n errors are present, output is obtained or RTL schematic. And
project summary.
11. Now run the behavioral simulation for op waveform.
12. Now run the implementation and generate bit stream.
13. Connect the hardware and select the target device. Now add the constraints file with _con
extension.
14. Now dump the bit stream into the hardware using program option.

RESULT:
The S-R, J-K,T,D Flipflops were designed and realized using HDL programs and vivado.
Synthesis Report:
The I/O ports we used are 5 in number for S-R and J-K flipflops and 4 in number for T and D
flipflops and they are as follows :
1. For S-R: Input ports are Y9, G22, H22 and output ports are T22,T21.
2. For J-K: Input ports are Y9, G22, H22 and output ports are T22,T21.
3. For T: Input ports are Y9, G22 and output ports are T22,T21.
4. For D: Input ports are Y9, G22 and output ports are T22,T21.
Note: Y19 is exclusively used for CLK input
LUTS:
1. Number of LUTs used for S-R flipflop: 2(post implementation) and 4(post synthesis)
2. Number of LUTs used for J-K flipflop: 1(post implementation) and 1(post synthesis)
3. Number of LUTs used for T flipflop: 1(post implementation) and 1(post synthesis)
4. Number of LUTs used for D flipflop: 1(post implementation) and 1(post synthesis)

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SIMULATION RESULT:
1) S-R FLIPFLOP:

2) J-K FLIPFLOP:

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3) T-FLIPFLOP:

4) D-FLIPFLOP:

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PROJECT SUMMARY:
S-R FLIPFLOP:

J-K FLIPFLOP:

T-FLIPFLOP:

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D-FLIPFLOP:

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EXPERIMENT NO: 7
INTRODUCTION TO LAYOUT DESIGN RULES
AIM:
To learn interactions between different layers and steps for layout designing using Lambda based rules.

REQUIREMENTS:
Software required: Mentor graphics tool
Hardware required: PC

THEORY:
The layout design rules provide a set of guidelines for constructing the various masks needed in the
fabrication of integrated circuits. Design rules are consisting of the minimum width and minimum spacing
requirements between objects on the different layers.
The most important parameter used in design rules is the minimum line width. This parameter indicates
the mask dimensions of the semiconductor material layers. Layout design rules are used to translate a
circuit concept into an actual geometry in silicon.
The design rules are the media between circuit engineer and the IC fabrication engineer. The Circuit
designers require smaller designs with high performance and high circuit density whereas the IC
fabrication engineer requires high yield process.
Minimum line width (MLW) is the minimum MASK dimension that can be safely transferred to the
semiconductor material. For the minimum dimension design rules differ from company to company and
from process to process.

LAMBDA-BASED-DESIGN-RULES:
 The Mead-Conway approach is to characterize the process with a single scalable
parameter called lambda that is process-dependent and is defined as the maximum
distance by which a geometrical feature on any one layer can stray from another feature,
due to over etching, misalignment, distortion, over or under exposure etc. with a suitable
safety factor included.
 The purpose of defining lambda properly is to make the design itself independent of both
process and fabrication and to allow the design to be rescaled at a future date when the
fabrication tolerances are shrunk.
 The layout design rules provide a set of guidelines for constructing the various masks
needed in the fabrication of integrated circuits. Design rules are consisting of the
minimum width and minimum spacing requirements between objects on the different
layers.

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 The most important parameter used in design rules is the minimum line width. This
parameter indicates the mask dimensions of the semiconductor material layers. Layout
design rules are used to translate a circuit concept into an actual geometry in silicon.
 The design rules are the media between circuit engineer and the IC fabrication engineer.
The Circuit designers require smaller designs with high performance and high circuit
density whereas the IC fabrication engineer requires high yield process.
 Minimum line width (MLW) is the minimum MASK dimension that can be safely
transferred to the semiconductor material. For the minimum dimension design rules differ
from company to company and from process to process.
 m.' equals 0.125 m process technology ' e.g. for a 0.25 ' is set to a value and the
design dimensions are converted in the form of numbers. Typically a minimum line width
of a process is set to 2'. For an IC process 'To address this issue scalable design rule
approach is used. In this approach rules are defined as a function of single parameter
called '

LAYERED REPRESENTATION OF LAYOUT:

The layer representation of layout converts the masks used in CMOS into a simple layout levels that
are easier to visualize by the designers. The CMOS design layouts are based on following
components:
(1) Substrates or Wells: These wells are p type for NMOS devices and n type for PMOS devices.
(2) Diffusion regions: At these regions the transistors are formed and also called as active layer.
These are defined by n+ for NMOS and p+ for PMOS transistors.
(3) Polysilicon layers: These are used to form the gate electrodes of the transistors.
(4) Metal interconnects layers: These are used to form the power supply and ground rails as well
as input and output rails.
(5) Contact and via layers: These are used to form the inter layer connections.

ADVANTAGES OF LAMBDA-BASED-DESIGN-RULES:
 Design rules based on single parameter, λ
 Simple for the designer
 Wide acceptance
 Provide feature size independent way of setting out mask
 Minimum feature size is defined as 2 λ
 Used to preserve topological features on a chip  Prevents shorting, opens, contacts from slipping
out of area to be contacted

RESULT :
Hence learnt and observed the importance of the Micron rules and Lambda based rules in the
designing process.

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EXPERIMENT NO: 8
LAYOUT, PHYSICAL VERIFICATION, PLACEMENT & ROUTE FOR
COMPLEX DESIGN AND STATIC TIMING ANALYSIS OF A CMOS
INVERTER

AIM:
To design and create layout, observe the delays in simulation waveforms, do physical verification,
placement & route for complex design of the CMOS inverter using Mentor Graphics tool.

REQUIREMENTS:
Software required: Mentor graphics tool
Hardware required: PC

THEORY:
In the CMOS inverter circuit, NMOS and PMOS transistors work as driver transistors. When one
transistor is ON, the other one is OFF. CMOS inverter circuit consists of two MOSFETs in series in such a
way that the P-channel device has its source connected to +VDD (a positive voltage) and the N-channel
device has its source connected to ground. The gates of the two devices are connected together as the
common input and the drains are connected together as the common output. When input is HIGH, the gate
of Qi (P-channel) is at 0V relative to the source of Qi, i.e. VGS1 =0V. Thus, Qi is OFF. On the other
hand, the gate of Q2 (N-channel) is at + VDD relative to its source i.e. VGS2 = + VDD. Thus, Q2 is ON.
This will produce Vout ≈ 0 V. When input is LOW, the gate of Qi (P-channel) is at a negative potential
relative to its source while Q2 has VGS = 0 V. Thus, Qi is ON and Q2 is OFF. This produces output
voltage approximately + VDD.
Properties of a CMOS inverter:
 Since in CMOS inverter there is existence of direct between power supply and ground, it has low
output impedance.
 As the output voltage in CMOS inverter is always either VDD or GND, the voltage swing in
CMOS inverter is VDD
 As the gate of MOS transistor does not draws any DC input current the input resistance of CMOS
inverter is extremely high.
 The CMOS inverter is an important circuit device that provides quick transition time, high buffer
margins, and low power dissipation: all three of these are desired qualities in inverters for most
circuit design. It is quite clear why this inverter has become as popular as it is.

PROCEDURE:
1) Using terminal open Mentor Graphics and go to file and select new project, then window will be
opened. Then click on project browse and press the up directory option until slash appears.

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SCHEMATIC OF CMOS INVERTER:

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2) Then create a new directory and name it. Now double click on it and again write name and
click OK. Then select library then click on browse location map, then select Generic 13 and
click on OK.
3) Now a window will be opened, in that click on Add Standard libraries and click on OK.
Now right click on the directory of file and select new library, give name and press OK.
Then right click on sub block and click on new cell then right click on new cell and select
new schematic.
4) A block schematic window will be opened, then press I, then Generic libraries then generic
symbols, then select NMOS and PMOS and place them on workspace.
5) Now again press I, then Generic 13, then Generic library then select ground and Vdd and
place these components and wire them and add inputs and output ports and edit NET as in
and out.
6) Now save then schematic and click on Add, then generic symbol, then activate symbol, then
save and edit, then choose shape, then buffer, then click OK twice. Then add circle and save
it and close it.

TEST BENCH:
1) Go to the navigator, right click on cell name , schematic, name the file as filename_tb, then
click on ok.
2) Press I, double click on the file, a symbol will be displayed. Again press I, go to Generic
library and select ground and Vdd, then go to source library and select DC voltage source
and pulse voltage source and place them in schematic.
3) Now save the schematic and click on simulation, then analysis and select new design and
setran to ‘0’.
4) Now on the left of window click on outputs, then analysis and select trans.
5) Now in window select task as plot. Now minimize this window and select input and output
wire by pressing ctrl and click on add inputs and outputs and then click on apply and
minimize the window. Now click on Run ELDO and then click on view waves and observe
the output.
6) Now Right click on cell >New layout>Ok>Pyxis layout window > New layout sub-window >
OK. Select pmos & nmos and place it on the workspace. Pick Place Ports>Place Schematic ports
>VDD,Place the rest of the ports.
7) IRoute >SDL toolbar> Once you place the cursor >Route all the ports in the layout except input
port as shown For routing poly and input port of M1, VIA has to be created.
8) PHYSICAL VERIFICATION OF LAYOUT: DRC2, LVS3, PEX .1.DRC:T ools>Calibre>Run DRC.
In Calibre Interactive – DRC->Run DRC. In Calibre RVE window see results. RUNNING LVS
(Layout versus Schematic): text the ports on the layout. In the pyxis window menu bar,
Add >Text on Ports. >OK. LVS: Tools > Calibre > Run LVS.
9) Inputs : layout browse for GDS file.Check “Export from layout viewer” & “Export from schematic viewer”
format. Select Run LVS in the Calibre Interactive window to get Calibre RVE window.

ANURAG GROUP OF INSTITUTIONS DEPARTMENT OF ECE VLSI LAB

NAME : A.VINEELA REDDY DATE:
HT N0.: 16H61A04C6 PAGE NO.:

SIMULATION RESULT:

LAYOUT:

ANURAG GROUP OF INSTITUTIONS DEPARTMENT OF ECE VLSI LAB

NAME : A.VINEELA REDDY DATE:
HT N0.: 16H61A04C6 PAGE NO.:

RESULT:
Hence designed and implemented the schematic of CMOS INVERTER in pyxis area and simulation
waveforms are observed in EZ wave window, developed the layout using Mentor Graphics tool

ANURAG GROUP OF INSTITUTIONS DEPARTMENT OF ECE VLSI LAB