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Computer Architecture

The document describes the fetch-decode-execute cycle of a computer using the von Neumann architecture. It involves the following steps: 1. The program counter loads the memory address register with the address of the next instruction. 2. The program counter is then incremented to point to the next instruction. 3. The instruction at the address in the memory address register is loaded into the memory data register. 4. The instruction is then loaded into the current instruction register to be decoded and executed. If the instruction is a jump, the program counter is updated before repeating the cycle. The document then contrasts the von Neumann architecture with the Harvard architecture. The key differences are that the Harvard architecture has

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adonis
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32 views

Computer Architecture

The document describes the fetch-decode-execute cycle of a computer using the von Neumann architecture. It involves the following steps: 1. The program counter loads the memory address register with the address of the next instruction. 2. The program counter is then incremented to point to the next instruction. 3. The instruction at the address in the memory address register is loaded into the memory data register. 4. The instruction is then loaded into the current instruction register to be decoded and executed. If the instruction is a jump, the program counter is updated before repeating the cycle. The document then contrasts the von Neumann architecture with the Harvard architecture. The key differences are that the Harvard architecture has

Uploaded by

adonis
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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The Fetch-Decode-Execute-Reset Cycle

The following is an algorithm that shows the steps in the cycle. At the end the cycle is reset and
the algorithm repeated.
1. Load the address that is in the program counter (PC) into the memory address register (MAR).
2. Increment the PC by 1.
3. Load the instruction that is in the memory address given by the MAR into the memory data
register (MDR).
4. Load the instruction that is now in the MDR into the current instruction register (CIR).
5. Decode the instruction that is in the CIR.
6. If the instruction is a jump instruction then
a. Load the address part of the instruction into the PC
b. Reset by going to step 1.
7. Execute the instruction.
8. Reset by going to step 1.

Steps 1 to 4 are the fetch part of the cycle. Steps 5, 6a and 7 are the execute part of the cycle and
steps 6b and 8 are the reset part.
Step 1 simply places the address of the next instruction into the memory address register so
that the control unit can fetch the instruction from the right part of the memory. The program
counter is then incremented by 1 so that it contains the address of the next instruction,
assuming that the instructions are in consecutive locations

Computer Architecture
Von Neumann Architecture
Von Neumann architecture by John von Neumann 1945 describes a design architecture for an
electronic digital computer Von Neumann realised that data and programs are indistinguishable
and can, therefore, use the same memory. The Von Neumann architecture uses a single processor
which follows a linear sequence of fetch-decode-execute using registers

Limitations of the Von Neumann Architecture.


 'Von Neumann bottleneck' every piece of data and instruction has to pass across one
data bus in order to move from main memory into the CPU (and back again). This is a
problem because the data bus is a lot slower than the rate at which the CPU can carry
out instructions. The CPU would spends most of its time waiting around for instructions.
 Both data and programs share the same memory space.
 the rate at which data needs to be fetched and the rate at which instructions need to be
fetched are often very different. And yet they share the same bottlenecked data bus.

Harvard Architecture
Consideres splitting the memory into two parts. One part for data and another part for
programs. Each part is accessed with a different bus. This means the CPU can be fetching both
data and instructions at the same time. There is also less chance of program corruption.

The Harvard architecture is a computer architecture with physically separate storage and signal
pathways for instructions and data. Today, most processors implement such separate signal
pathways for performance reasons.

Contrast with von Neumann architecture

Under pure von Neumann architecture the CPU can be either reading an instruction or
reading/writing data from/to the memory. Both cannot occur at the same time since the
instructions and data use the same bus system. In a computer using the Harvard architecture, the
CPU can both read an instruction and perform a data memory access at the same time, even
without a cache. A Harvard architecture computer can thus be faster for a given circuit
complexity because instruction fetches and data access do not contend for a single memory
pathway.

Also, a Harvard architecture machine has distinct code and data address spaces: instruction
address zero is not the same as data address zero. Instruction address zero might identify a
twenty-four bit value, while data address zero might indicate an eight-bit byte that is not part of
that twenty-four bit value.

1 Two types of computer architectures


There are 2 computer architectures, which are different in the way of accessing memories: von
Neumann Architecture and Harvard Architecture.
The von Neumann Architecture has following specialties :
1. Instructions and Data are stored in the same memory.
2. Instructions and Data share one memory system. (The Length of bit, the same form of address)
And the Harvard Architecture has following factors :
1. Physically separates storage and signal pathway for instructions and data.
2. Generally, the bit of Instructions is wider than Data.
3. For some computers, the Instruction memory is read-only.
4. In cases without caches, the Harvard Architecture is more efficient than von-Neumann.
Bus structures of the two are also different: Harvard architecture has separate data and
instruction busses, allowing transfers simultaneously on both busses. Von Neumann architecture
has only one bus which is used for both data transfers and instruction fetches, and therefore data
transfers and instruction fetches must be scheduled – they can not be performed at the same time.

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