Computer Architecture
Computer Architecture
Control bus
The control bus is also bidirectional. It carries signals from the control unit (CU) to all the other computer
components. It is usually 8-bits wide. There is no real need for it to be any wider since it only carries control
signals.
Von Neumann Architecture
Early computers were fed data while the machines were actually running; it
wasn’t possible to store programs or data, which meant they couldn’t
operate without considerable human intervention.
In the mid-1940s, John von Neumann developed the concept of the ‘stored
program computer’, which has been the basis of computer architecture ever
since. The von Neumann architecture had the following main features (none
of which were available in computers prior to the mid-1940s):
» the concept of a central processing unit (CPU)
» the CPU was able to access the memory directly
» computer memories could store programs as well as data
» stored programs were made up of instructions which could be executed in
sequential order.
Von Neumann Architecture
Registers
Registers are high speed storage areas in the CPU.
MDR Memory Data Register Holds data that is being transferred to or from memory
ACC Accumulator Where intermediate arithmetic and logic results are stored
CIR Current Instruction Register Contains the current instruction during processing
Fetch Execute Cycle
Step Fetch execute cycle steps
The PC contains the address of the memory location
1
that has the next instruction which has to be fetched
This address is then copied from the PC to the MAR
2 via the address bus
The contents (instruction) at the memory location
3 (address) contained in MAR are then copied into the
MDR
The contents (instruction) in the MDR is then copied
4 and placed into the CIR
The value in the PC is then incremented by 1 so that
5 it now points to the next instruction which has to be
fetched
The instruction is finally decoded and then executed
6 by sending out signals (via control bus) to the
various components of the computer
7 Repeat
Fetch–Decode–Execute cycle
To carry out a set of instructions, the CPU first of all fetches some data and instructions from
memory and stores them in suitable registers. Both the address bus and data bus are used in
this process. Once this is done, each instruction needs to be decoded before finally being
executed. This is all known as the Fetch–Decode–Execute cycle.
Fetch
Both data and instruction can be stored in MDR. In the Fetch–Decode–Execute cycle, the next
instruction is fetched from the memory address currently stored in the MAR and the
instruction is stored in the MDR. The contents of the MDR are then copied to the Current
Instruction Register (CIR). The PC is then incremented (increased by 1) so that the next
instruction can be then be processed.
Decode
The instruction is then decoded so that it can be interpreted in the next part of
the cycle.
Execute
The CPU passes the decoded instruction as a set of control signals to the appropriate
components within the computer system. This allows each instruction to be carried out in its
logical sequence.
Factors that determine the performance of a CPU.
All these factors need to be taken into account when considering computer
performance.
Summarizing these points:
• Increasing bus width (data and address buses) increases the performance
and speed of a computer system
• increasing clock speed will potentially increase the speed of a computer
• A computer’s performance can be changed by altering bus width, clock
speed and use of multi-core CPUs
• Use of cache memories can also speed up a CPU’s performance.
System clock: The clock defines the clock cycle that synchronises all computer
operations. As mentioned earlier, the control bus transmits timing signals ensuring
everything is fully synchronised. By increasing clock speed, the processing speed of
the computer is also increased (a typical current value is 3.5GHz – which means 3.5
billion clock cycles a second).
For example, with a dual core the CPU communicates with both cores using
one channel to increase its performance and a Quad core will use six
channels to increase its performance.
Class Activities
• Explain how it is possible to increase the performance of a CPU/
microprocessor.
• In your explanation, include some of the risks associated
with your suggestions to improve performance.