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Coa MCQ PDF
Coa MCQ PDF
Computer System Architecture MCQ 01 11. Which are the operation that a computer
performs on data that put in register:
1. RTL stands for: a. Register transfer b. Arithmetic
a. Random transfer language c. Logical d. All of these
b. Register transfer language
c. Arithmetic transfer language 12. Which micro operations carry information
d. All of these from one register to another:
a. Register transfer b. Arithmetic
2. Which operations are used for addition, c. Logical d. All of these
subtraction, increment, decrement and complement
function: 13. Micro operation is shown as:
a. Bus a. R1R2 b. R1R2
b. Memory transfer c. Both d. None
c. Arithmetic operation
d. All of these 14. In memory transfer location address is
supplied by____ that puts this on address bus:
3. Which language is termed as the symbolic a. ALU b. CPU
depiction used for indicating the series: c. MAR d. MDR
a. Random transfer language
b. Register transfer language 15. How many types of memory transfer operation:
c. Arithmetic transfer language a. 1 b. 2 c. 3 d. 4
d. All of these
16. Operation of memory transfer are:
4. The method of writing symbol to indicate a a. Read b. Write
provided computational process is called as a: c. Both d. None
a. Programming language
b. Random transfer language 17. In memory read the operation puts memory
c. Register transfer language address on to a register known as :
d. Arithmetic transfer language a. PC b. ALU
c. MAR d. All of these
5. In which transfer the computer register are
indicated in capital letters for depicting its function: 18. Which operation puts memory address in
a. Memory transfer b. Register transfer memory address register and data in DR:
c. Bus transfer d. None of these a. Memory read b. Memory write
c. Both d. None
6. The register that includes the address of the
memory unit is termed as the ____: 19. Arithmetic operation are carried by such micro
a. MAR b. PC operation on stored numeric data available in_____:
c. IR d. None of these a. Register b. Data
c. Both d. None
7. The register for the program counter is
signified as_____: 20. In arithmetic operation numbers of register and
a. MAR b. PC the circuits for addition at _____:
c. IR d. None of these a. ALU b. MAR
c. Both d. None
8. In register transfer the instruction register as:
a. MAR b. PC 21. Which operation are implemented using a
c. IR d. None of these binary counter or combinational circuit:
a. Register transfer b. Arithmetic
9. In register transfer the processor register as: c. Logical d. All of these
a. MAR b. PC
c. IR d. RI 22. Which operation is binary type, and are
performed on bits string that is placed in register:
10. How many types of micro operations: a. Logical micro operation
a. 2 b. 4 b. Arithmetic micro operation
c. 6 d. 8 c. Both
d. None
23. A micro operation every bit of a register is a: 33. In organization of a digital system register
a. Constant b. Variable transfer of any digital system therefore it is called:
c. Both d. None a. Digital system b. Register
c. Data d. Register
24. Which operation is extremely useful in transfer level
serial transfer of data:
a. Logical micro operation 34. The binary information of source register
b. Arithmetic micro operation chosen by:
c. Shift micro operation a. Demultiplexer b. Multiplexer
d. None of these c. Both d. None
25. Which language specifies a digital system 35. Control transfer passes the function via
which uses specified notation: control______:
a. Register transfer b. Arithmetic a. Logic b. Operation
c. Logical d. All of these c. Circuit d. All of these
30. High level language C supports register 41. A three state gate defined as:
transfer technique for______ application: a. Analog circuit b. Analog fundamentals
a. Executing b. Compiling c. Both a&b d. Digital circuit
c. Both d. None
42. In 3 state gate two states act as signals equal to:
31. A counter is incremented by one and memory a. Logic 0 b. Logic 1
unit is considered as a collection of _______: c. None of these d. Both a & b
a. Transfer register b. Storage register
c. RTL d. All of these 43. In 3 state gate third position termed as high
impedance state which acts as:
32. Which is the straight forward register a. Open circuit b. Close circuit
transfer the data from register to another register c. None of these d. All of above
temporarily:
a. Digital system 44. In every transfer, selection of register by bus is
b. Register decided by:
c. Data a. Control signal b. No signal
d. Register transfer operations c. All signal d. All of above
48. Which is referred as a sequential circuit which 59. In which shift is used to divide
contains the number of register as per the protocol: a signed number by two:
a. RTL b. RAM a. Logical right-shift
c. MAR d. All of these b. Arithmetic right shift
c. Logical left shift
49. Which operation refer bitwise manipulation of d. Arithmetic left shift
contents of register:
a. Logical micro operation 60. Shift left is equal to:
b. Arithmetic micro operation a. multiply by two
c. Shift micro operation b. add by two
d. None of these c. divide by two
d. subtract by two
50. Which symbol will be used to denote an micro
operation:
a. (^) b. (v)
c. Both d. None
Computer System Architecture MCQ 02 11. As the instruction length increases ________
1. _____ is a command given to a computer to of instruction addresses in all
perform a specified operation on some given data: the instruction is_______:
a. An instruction b. Command a. Implicit inclusion
c. Code d. None of these b. Implicit and disadvantageous
c. Explicit and disadvantageous
2. An instruction is guided by_____ to perform d. Explicit and disadvantageous
work according:
a. PC b. ALU c. Both a and b d. CPU 12. ______is the sequence of operations
performed by CPU in processing an instruction:
3. Two important fields of an instruction are: a. Execute cycle
a. Opcode b. Operand b. Fetch cycle
c. Only a d. Both a & b c. Decode
d. Instruction cycle
4. Each operation has its _____ opcode:
a. Unique b. Two 13. The time required to complete
c. Three d. Four one instruction is called:
a. Fetch time
5. which are of these examples of Intel 8086 b. Execution time
opcodes: c. Control time
d. All of these
a. MOV b. ADD c. SUB
d. All of these 14. _____is the step during which a
new instruction is read from the memory:
6. _______specify where to get the source and a. Decode
destination operands for the operation specified by b. Fetch
the _______: c. Execute
a. Operand fields and opcode d. None of these
b. Opcode and operand
c. Source and destination 15. ________is the step during which the
d. CPU and memory operations specified by the instruction are executed:
a. Execute
7. The source/destination of operands can be b. Decode
the_______ or one of the general-purpose register: c. Both a& b
a. Memory b. One d. None of these
c. both d. None of these
16. Decode is the step during
8. The complete set of op-codes for a particular which instruction is______:
microprocessor defines the______ set for that a. Initialized
processor: b. Incremented
a. Code b. Function c. Decoded
c. Module d. Instruction d. Both b & c
9. Which is the method by which instructions 17. The instruction fetch operation is initiated by
are selected for execution: loading the contents of program counter into
a. Instruction selection the______ and sends_____ request to memory:
b. Selection control a. Memory register and read
c. Instruction sequencing b. Memory register and write
d. All of these c. Data register and read
d. Address register and read
10. The simplest method of controlling sequence
of instruction execution is to have 18. The contents of the program counter is the
each instruction explicitly specify: _______ of the instruction to be run:
a. The address of next instruction to be run a. Data
b. Address of previous instruction b. Address
c. Both a & b c. Counter
d. None of these d. None of these
19. The instruction read from memory is then 27. ________are the codes that
placed in the_______ and contents of program represent alphabetic characters, punctuation marks
counter is______ so that it contains the address and other special characters:
of_______ instruction in the program: a. Alphanumeric codes
a. Program counter, incremented and next b. ASCII codes
b. Instruction register, incremented and previous c. EBCDIC codes
c. Instruction register, incremented and next d. All of these
d. Address register, decremented and next
28. Abbreviation ASCII stands for:
20. Execution of instruction specified a. American standard code for information
by instruction to perform: interchange
a. Operation b. Abbreviation standard code for information
b. Operands interchange
c. Both a & b c. Both
d. None of these d. None of these
21. _______ is a symbolic representation of 29. How many bit of ASCII code:
discrete elements of information: a. 6
a. Data b. 7
b. Code c. 5
c. Address d. 8
d. Control
30. Which code used in transferring coded
22. Group of binary bits(0&1) is known as: information from keyboards and to computer
a. Binary code display and printers:
b. Digit code a. ASCII
c. Symbolic representation b. EBCDIC
d. None of these c. Both
d. None of these
23. A group of 4 binary bits is called:
a. Nibble 31. Which code used to represent numbers, letters,
b. Byte punctuation marks as well as control characters:
c. Decimal a. ASCII
d. Digit b. EBCDIC
c. Both
24. BCD uses binary number system to d. None of these
specify decimal numbers:
a. 1-10 32. abbreviation EBCDIC stand for:
b. 1-9 a. Extended binary coded decimal
c. 0-9 interchange code
d. 0-10 b. External binary coded decimal interchange
code
25. The ______ are assigned according to c. Extra binary coded decimal interchange code
the position occupied by digits: d. None of these
a. Volume
b. Weight 33. How many bit of EBCDIC code:
c. Mass a. 7
d. All of these b. 8
c. 5
26. what is the BCD for a decimal number 559: d. 9
a. [0101 0101 1001]BCD
b. [0101 0001 1010] 34. Which code the decimal digits are represented
c. [0101 1001 1001] by the 8421 BCD code preceded by 1111:
d. [1001 1010 0101] a. ASCII
b. EBCDIC
c. Both
d. None of these
35. _________ has the property that corrupting or 43. Which method is used to detect double errors
garbling a code word will likely produce a bit string and pinpoint erroneous bits:
that is not a code word: a. Even parity method
a. Error deleting codes b. Odd parity method
b. Error detecting codes c. Check sum method
c. Error string codes d. All of these
d. None of these
44. A code that is used to correct error is called an
36. Which is method used most simple and _________:
commonly: a. Error detecting code
a. Parity check method b. Error correcting code
b. Error detecting method c. Both
c. Both d. None of these
d. None of these
45. A received ___________with a bit error will be
37. Which is the method of parity: closer to the originally transmitted code word than
a. Even parity method to any other code word:
b. Odd parity method a. Code word
c. Both b. Non code word
d. None of these c. Decoding
d. All of these
38. The ability of a code to detect single errors can
be stated in term of the _________: 46. Which code word was originally transmitted to
a. Concept of distance produce a received word is called:
b. Even parity a. Non code word
c. Odd parity b. Code word
d. None of these c. Decoding
d. None of these
39. The first n bit of a code word called
__________ may be any of the 2n n- bit string 47. The hardware that does this is an ________:
minimum error bit: a. Error detecting decoder
a. Information bits b. Error correcting decoder
b. String bits c. Both
c. Error bits d. None of these
d. All of these
48. Hamming codes was developed in
40. A code in which the total number of 1s in a __________:
valid (n+1) bit code word is even, this is called an a. 1953
__________: b. 1950
a. Even parity code c. 1945
b. Odd parity code d. 1956
c. Both
d. None of these 49. ____________ between two code words is
defined as the number of bits that must be changed
41. A code in which the total number of 1s in a for one code to another:
valid (n+1)bit code word is odd and this code is a. Hamming codes
called an__________: b. Hamming distance
a. Error detecting code c. Both
b. Even parity code d. None of these
c. Odd parity code
d. None of these 50. It is actually a method for constructing codes
with a minimum distance of ____:
42. a code is simply a subset of the vertices of the a. 2
_____: b. 4
a. n bit b. n cube c. 3
c. n single d. n double d. 5
51. The bit position in a ___________ can be 59. Which unit provide status , timing and control
numbered from 1 through 2i-1: signal:
a. Hamming code word a. Timing and control unit
b. Hamming distance word b. Memory unit
c. Both c. Chace unit
d. None of these d. None of these
52. Each check bit is grouped with the information 60. Which unit acts as the brain of the computer
bits as specified by a____________: which control other peripherals and interfaces:
a. Parity check code a. Memory unit
b. Parity check matrix b. Cache unit
c. Parity check bit c. Timing and control unit
d. All of these d. None of these
53. The pattern of groups that have odd parity 61. It contains the ____________stack for PC
called the _________must match one of the of storage during subroutine calls and
columns in the parity check matrix: input/output interrupt services:
a. Syndrome a. Seven- level hardware
b. Dynodes b. Eight- level hardware
c. Both c. One- level hardware
d. None of these d. Three- level hardware
54. Which are designed to interpret a specified 62. Which unit works as an interface between the
number of instruction code: processor and all the memories on chip or off- chip:
a. Programmer a. Timing unit
b. Processors b. Control unit
c. Instruction c. Memory control unit
d. Opcode d. All of these
55. Which code is a string of binary digits: 63. The maximum clock frequency is_______:
a. Op code a. 45 MHZ
b. Instruction code b. 50 MHZ
c. Parity code c. 52 MHZ
d. Operand code d. 68 MHZ
56. The list of specific instruction supported by the 64. ________ is given an instruction in machine
CPU is termed as its ____________: language this instruction is fetched from the
a. Instruction code memory by the CPU to execute:
b. Parity set a. ALU
c. Instruction set b. CPU
d. None of these c. MU
d. All of these
57. __________is divided into a number of fields
and is represented as a sequence of bits: 65. Which cycle refers to the time period during
a. instruction which one instruction is fetched and executed by
b. instruction set the CPU:
c. instruction code a. Fetch cycle
d. parity code b. Instruction cycle
c. Decode cycle
58. Which unit is necessary for the execution d. Execute cycle
of instruction:
a. Timing 66. How many stages of instruction cycle:
b. Control a. 5
c. Both b. 6
d. None of these c. 4
d. 7
86. ____________ of information in a human 99. How many major component make up the
brain and a computer happens differently: CPU:
a. Intelligence b. Storage a. 4 b. 3 c. 6 d. 8
c. Versatility d. Diligence
100. Which register holds the current
87. Which are the basic operation for converting: instruction to be executed:
a. Inputting b. Storing c. Processing a. Instruction register
d. Outputting e. Controlling b. Program register
f. All of these c. Control register
d. None of these
88. The control unit and arithmetic logic unit are 101. Which register holds the next instruction
know as the ___________: to be executed:
a. Central program unit b. CPU a. Instruction register
c. Central primary unit d. None b. Program register
c. Program control register
89. Which unit is comparable to the central d. None of these
nervous system in the human body:
a. Output unit b. Control unit 102. Each instruction is also accompanied by
c. Input unit d. All of these a___________:
a. Microprocessor
90. ___________ of the primary memory of the b. Microcode
computer is limited: c. Both
a. Storage capacity b. Magnetic disk d. None of these
c. Both d. None of these
103. Which are microcomputers commonly
91. Information is handled in the computer by used for commercial data processing, desktop
_________: publishing and engineering application:
a. Electrical digit b. Electrical component a. Digital computer
c. Electronic bit d. None of these b. Personal computer
c. Both
92. 0 and 1 are know as ___________: d. None of these
a. Byte b. Bit c. Digits d. Component
104. Which microprocessor has the control
93. 0 and 1 abbreviation for: unit, memory unit and arithmetic and logic unit:
a. Binary digit b. Octal digit a. Pentium IV processor
c. Both d. None of these b. Pentium V processor
c. Pentium III processor
94. How many bit of nibble group: d. None of these
a. 5 b. 4 c. 7 d. 8
105. The processing speed of a computer
95. How many bit of bytes: depends on the __________of the system:
a. 3 b. 4 c. 6 d. 8 a. Clock speed
b. Motorola
96. Which is the most important component of a c. Cyrix
digit computer that interprets the instruction and d. None of these
processes the data contained in computer programs:
a. MU b. ALU c. CPU d. PC 106. Which microprocessor is available with a
clock speed of 1.6 GHZ:
97. Which part work as a the brain of the computer a. Pentium III b. Pentium II
and performs most of the calculation: c. Pentium IV d. All of these
a. MU b. PC c. ALU d. CPU
107. Which processor are used in the most
98. Which is the main function of the computer: personal computer:
a. Execute of programs a. Intel corporation’s Pentium
b. Execution of programs b. Motorola corporation’s
c. Both c. Both
d. None of these d. None of these
5. Assembler works to convert assembly 13. The assembler in first pass reads the program
language program into machine language : to collect symbols defined with offsets in a
a. Before the computer can execute it table_______:
b. After the computer can execute it a. Hash table
c. In between execution b. Symbol table
d. All of these c. Both a& b
d. None of these
6. ________generation computers use assembly
language: 14. In second pass, assembler creates _______in
a. First generation binary format for every instruction in program and
b. Third generation then refers to the symbol table to giving every
c. second generation symbol an______ relating the segment.
d. fourth generation a. Code and program
b. Program and instruction
7. Assembly language program is called: c. Code and offset
a. Object program d. All of these
b. Source program
c. Oriented program 15. which of the 2 files are created by the
d. All of these assembler:
a. List and object file
8. To invoke assembler following command are b. Link and object file
given at command line: c. Both a & b
a. $ hello.s -o hello.o d. None of these
b. $as hello.s –o o
c. $ as hello –o hello.o 16. In which code is object file is coded:
d. $ as hello.s –o hello.o a. Link code
b. Decimal code
c. Assembly code
d. Binary code
17. which type of errors are detected by the 26. Assembler is a_______:
assembler: a. Interpreter
a. syntax error b. Translator
b. logical error c. Exchanger
c. run time error d. None of these
d. none of these
27. A_______ processor controls repetitious
18. MOVE AX BX in this LINES OF CODE what writing of sequence:
type of error is declared: a. Macro
a. Undeclared identifier MOVE b. Micro
b. undeclared identifier AX c. Nano
c. Accept as a command d. All of these
d. Not look in symbol table
28. IBM-360 type language is example which
19. In given lines of code MOV AX,BL have supporting______ language:
different type of operands according to assembler a. Micro
for 8086 architecture these identifiers must be of: b. Macro
a. Different type only in byte c. Both a & b
b. Same type either in word or byte d. None of these
c. Both a & b
d. None of these 29. _________ is attached to using macro
instruction definition:
20. What type of errors are not detected a. Name
by assemblers: b. Definition
a. Syntax error c. Identifier
b. Run time error d. All of these
c. Logical error
d. All of these 30. END of macro definition by:
a. NAME
21. ______serves as the purpose of documentation b. MEND
only: c. DATA
a. List b. object d. MEMORY
c. link d. code
31. Process of replacing the sequence of lines of
22. An assembler is a utility program that codes is known as:
performs: a. Expanding die macro
a. Isometric translation b. Expanding tri macro
b. Isomorphic translation c. Tetra macro
c. Isochoric translation d. None of these
d. None of these
32. A program that links several programs is
23. Assemblers are of 2 types: called:
a. 1 pass a. Linker
b. 2 pass b. Loader
c. both a & b c. Translator
d. none of these d. None of these
24. CP/CMS assembly language was written in 33. _______address is not assigned by linker:
________assembler: a. Absolute
a. S/340 b. S-350 b. Relative
c. S/320 d. S/360 c. Both a & b
d. None of these
25. ASM-H widely used _____assembler:
a. S/370
b. S/380
c. S/390
d. S/360
38. It is the task of the ________to locate 45. After actual locations for main storage are
externally defined symbols in programs, load them known, a ______adjusts relative addresses to these
in to memory by placing their _______of symbols actual locations:
in calling program: a. Relocating loader
b. Locating loader
a. Loader and name c. Default loader
b. Linker and values d. None of these
c. Linker and name
d. Loader and values 46. If there is a module from single source-
language only that does not contain any external
39. Linker creates a link file containing binary references, it doesn’t need a linker to load it and is
codes and also produces_______ containing loaded______:
address information on linked files:
a. Indirectly
a. Link map b. Directly
b. Map table c. Extending
c. Symbol map d. None of these
d. None of these
47. Modern assemblers for RISC based
40. how many types of entities contained by architectures make optimization of instruction
assembler to handle program: scheduling to make use of CPU _______efficiently:
a. 4 a. Pipeline
b. 2 b. Without pipeline
c. 3 c. Both a & b
d. 5 d. None of these
48. which are of the following modern assemblers: 56. SPARC stands for:
a. MIPS a. Scalable programmer architecture
b. Sun SPARC b. Scalable processor architecture
c. HP PA-RISC c. Scalable point architecture
d. x86(x64) d. None of these
e. all of these 57. Full form of MIPS assembler is:
49. How many types of loop control structures in C a. Microprocessor without interlocked
language: pipeline stage
b. Microprocessor with interlocked pipeline
a. 4 stage
b. 5 c. Both a & b
c. 2 d. None of these
d. 3 58. _______ statement block is executed atleast
once for any value of the condition:
50. Types of loop control statements are: a. For statement
b. Do-while statement
a. For loop c. While statement
b. While loop d. None of these
c. Do-while loop
d. All of these 59. _______statement is an unconditional
transfer of control statement:
51. <Initial value> is_______ which initializes the a. Goto
value of variable: b. Continue
c. Switch
a. Assignment expression d. All of these
b. Condition value
c. Increment/decrement 60. In Goto statement the place to which control is
d. None of these transferred is identified by a statement______:
a. Label
52. The format “%8d” is used to print_______ b. Display
values in a line: c. Break
a. 11 d. None of these
b. 10
c. 9 61. The continue statement is used to transfer the
d. 12 control to the________ of a statement block in a
loop:
53. <Condition> is a _________expression which a. End
will have value true or false: b. Beginning
a. Relational c. Middle
b. Logical d. None of these
c. Both a & b
d. None of these 62. The__________ statement is used to transfer
the control to the end of statement block in a loop:
54. <Increment> is the________ value of variable
which will be added every time: a. Continue
a. Increment b. Break
b. Decrement c. Switch
c. Expanding d. Goto
d. None of these
63. ________function is used to transfer the
55. _______is the statement block of for loop lies control to end of a program which uses one
inside block of another for loop: argument( ) and takes value is zero for_______
a. Nested for loop termination and non-zero for _______termination:
b. Nested while loop a. Exit( ),normal, abnormal
c. Nested do-while loop b. Break, normal, abnormal
d. None of these c. Both a & b
d. None of these
64. To design a program it requires_______: 72. _______means that one of two alternative
a. Program specification sequences of instruction is chosen based on logical
b. Code specification condition:
c. Instruction specification a. Sequence
d. Problem specification b. Selection
c. Repetition
65. Testing helps to ensure _______of the program d. None of these
for use within a system:
a. Quality, accuracy and except 73. _________is sequence of instructions is
b. Quality, accuracy and acceptance executed and repeated any no. of times in loop until
c. Design, assurance and acceptance logical condition is true:
d. Quality, accuracy and development
66. An unstructured program uses a ________ a. Iteration
approach to solve problems: b. Repetition
c. Both a & b
a. Linear d. None of these
b. Top down
c. Both a & b 74. A ________is a small program tested
d. None of these separately before combining with final program:
79. ________is useful to prepare detailed program 86. After compilation of the program ,the operating
documentation: system of computer activates:
a. Flowchart a. Loader
b. Algorithm b. Linker
c. Both a & b c. Compiler
d. None of these d. None of these
80. Pseudo means: 87. The linker has utilities needed for
________within the translated program:
a. Imitation
b. Imitate a. Input
c. In imitation b. Output
d. None of these c. Processing
d. All of these
81. Preparing the pseudocode requires
_______time than drawing flowchart: 88. Flowchart is a_______ representation of an
algorithm:
a. Less
b. More a. Symbolic
c. Optimum b. Diagrammatic
d. None of these c. Both a & b
d. None of these
82. There is _____standard for preparing
pseudocode instructions: 89. In flow chart symbols the _______operation
represents the direction of flow:
a. No a. Connector
b. 4 b. Looping
c. 2 c. Arrows
d. 6 d. Decision making
83. ______are used to translate high level language 90. Which register is memory pointer:
instructions to a machine code: a. Program counter
b. Instruction register
a. Translators c. Stack pointer
b. Interpreters d. Source index
c. Compilers
d. None of these 91. How many approaches are used to design
control unit:
84. The compiler _______translate a a. 2
program code with any syntax error: b. 3
c. 4
a. Can d. 5
b. Cannot
c. Without 92. Which are the following approaches used to
d. None of these design control unit:
a. Hardwired control
85. Before checking the program for errors in b. Microprogrammed control
translating code into machine language the high c. Both a & b
level language code is loaded into_________: d. None of these
94. _______arrow represents the value obtained by 101. A subroutine called by another
evaluating right side expression/variable to the left subroutine is called:
side variable: a. Nested
b. For loop
a. Forth c. Break
b. Inbetween d. Continue
c. Back
d. None of these 102. The extent nesting in subroutine is
limited only by:
95. A ________ is written as separate unit, apart a. Number of available Stack locations
from main and called whenever necessary: b. Number of available Addressing locations
a. Subroutine c. Number of available CPU locations
b. Code d. Number of available Memory locations
c. Block 103. Which are of the following instructions
d. None of these of hardware subroutines:
a. SCAL
96. _______uses the stack to store return address b. SXIT
of subroutine: c. Both a & b
d. None of these
a. CPU
b. Microprocessor 104. Importance in local variable and index
c. register registers in subroutine does_____:
d. memory a. Alter
b. Not alter
97. A subroutine is implemented with 2 associated c. Both a & b
instructions: d. None of these
100. When subroutine is called contents of 108. subroutines are invoked by using
program counter is location address of their________ in a subroutine call statement and
_______instruction following call instruction is replacing formal parameters with________
stored on ________and program execution is parameters:
transferred to______ address: a. Identifier and formal
a. Non executable, pointer and subroutine b. Identifier and actual
b. Executable, Stack and Main program c. Expression and arguments
c. Executable, Queue and Subroutine d. None of these
d. Executable, Stack and Subroutine
123. The processed data is sent for output to 130. _________program converts machine
standard ________device which by default is instructions into control signals:
computer screen: a. Control memory program
b. Control store program
a. Input c. Both a & b
b. Output d. Only memory
c. Both a & b 131. who coined the term micro program in
d. None of these 1951:
137. The function of these microinstructions 145. A computer having writable control
is to issue the micro orders to______: memory is known as_________:
a. CPU a. Static micro programmable
b. Memory b. Dynamic micro programmable
c. Register c. Both a & b
d. Accumulator d. None of these
146. The control memory contains a set of
138. Micro-orders generate the_______ words where each word is:
address of operand and execute instruction and
prepare for fetching next instruction from the main a. Microinstruction
memory: b. Program
a. Physical c. Sets
b. Effective d. All of these
c. Logical
d. all of above 147. During program execution content of
main memory undergo changes and, but control
139. Which of the following 2 task are memory has______ microprogram:
performed to execute an instruction by MCU:
a. Microinstruction execution a. Static
b. Microinstruction sequencing b. Dynamic
c. Both a & b d. None of these c. Compile time
d. Fixed
140. What is the purpose of microinstruction
executions: 148. What happens if computer is started :
a. Generate a control signal a. It executes “CPU” microprogram which is
b. Generate a control signal to compile sequence of microinstructions stored in ROM
c. Generate a control signal to execute b. It executes “code” microprogram which is
d. All of these sequence of microinstructions stored in ROM
c. It executes “boot” microprogram which is
141. Which microinstruction provide next sequence of microinstructions stored in ROM
instruction from control memory: d. It executes “strap loader” microprogram
a. Microinstruction execution which is sequence of microinstructions stored in
b. Microinstruction Buffer ROM
c. Microinstruction decoder
d. Microinstruction Sequencing 149. Control memory is part of ______ that
has addressable storage registers and used as
142. Which are the following components of temporary storage for data:
microprogramed units to implement control
process: a. ROM
a. Instruction register b. RAM
b. Microinstruction address generation c. CPU
c. Control store microprogram memory d. Memory
d. Microinstruction Buffer
e. Microinstruction decoder 150. How many modes the address in control
f. All of these memory are divided:
144. A control memory is______ stored in 151. which of the following is interrupt mode:
some area of memory:
a. Control instruction a. Task mode
b. Memory instruction b. Executive mode
c. Register instruction c. Both a & b
d. None of these d. None of these
152. Mode of addresses in control memory 160. On what method search in cache
are: memory used by the system:
a. Executive mode
b. Task mode a. Cache directing
c. Both a & b b. Cache mapping
d. None of these c. Cache controlling
d. Cache invalidation
153. Addresses in control memory is made
by____ for each register group: 161. ______process starts when a cpu with
a. Address select logic cache refers to a memory:
b. Data select logic
c. Control select logic a. Main memory
d. All of these b. External memory
c. Cache
154. There are how many register groups in d. All of these
control memory:
a. 3 162. When cache process starts hit and miss
b. 5 rate defines in cache directory:
c. 6
d. 8 a. during search reads
b. during search writes
155. What type of circuit is used by control c. during replace writes
memory to interconnect registers: d. during finding writes
a. Data routing circuit
b. Address routing circuit 163. In cache memory hit rate indicates:
c. Control routing circuit a. Data from requested address is not available
d. None of the these b. Data from requested address is available
c. Control from requested address is available
156. Which memory is used to copy d. Address from requested address is not
instructions or data currently used by CPU: available
159. What are 2 advantages of cache memory: 167. Invalidation writes only to_____ and
a. Reduction of average access time for CPU erases previously residing address in memory:
memory a. Folders
b. Reduction of bandwidth of available memory b. Memory
of CPU c. Directory
c. Both a & b d. Files
d. None of these
168. _______machine instruction creates 176. Control ROM is the control memory that
branching to some specified location in main holds:
memory if result of last ALU operation is Zero or
Zero flag is set: a. Control words
a. Branch on One b. Memory words
b. Branch on Three c. Multiplexers
c. Branch on Nine d. Decoders
d. Branch on Zero
177. Opcode is the machine instruction
169. Full form of CAR: obtained from decoding instruction stored in:
a. Control address register
b. Content address register a. Stack pointer
c. Condition accumulator resource b. Address pointer
d. Code address register c. Instruction register
d. Incrementer
170. Two types of microinstructions are:
a. Branching 178. Branch logic determines which should be
b. Non-branching adopted to select the next______ value among
c. Both a & b possibilities:
d. None of these a. CAR
b. GAR
171. Which are 3 ways to determine address c. HAR
of next micro instruction to be executed: d. TAR
a. Next sequential address
b. Branching 179. ________ generates CAR+1 as
c. Interrupt testing possibility of next CAR value:
d. All of these a. Decrementer
b. Incrementer
172. Branching can be________: c. Postfix
a. Conditional d. Prefix
b. Unconditional
c. Both a & b 180. ________used to hold return address for
d. None of these operations of subroutine call branch:
a. TBR
173. In which branching condition is tested b. HDR
which is determined by status bit of ALU: c. SDR
a. Unconditional d. SBR
b. Conditional
c. Both a & b 181. Which of following 2 types of computer
d. None of these system considered by micro programmed unit:
a. Micro level computers
174. which branch is achieved by fixing b. Machine level computers
status bit that output of multiplexer is always one: c. Both a & b
a. Unconditional d. None of these
b. Conditional
c. Looping 182. Following are the components of micro
d. All of these programmed control unit:
a. Subroutine register
175. Which register is used to store addresses b. Control address register
of control memory from where instruction is c. Memory Of 128 words with 20 bits per words
fetched: d. All of these
a. MAR
b. BAR 183. Various machine level components are:
c. CAR a. Address register b. Program counter
d. DAR c. Data register d. Accumulator register
e. Memory of 2K,16 bits/word RAM
f. Multiplexers g. All of these
184. Data transfers are done using: 193. If _______flag is set then control unit
a. Multiplexer switching issues control signals that causes program counter
b. Demultiplexer switching to be incremented by 1:
c. Adder switching
d. Subtractor switching a. Zero
b. One
185. PC can be loaded from_____: c. Three
a. BR d. Eight
b. CR
c. AR 194. Which control unit is implemented as
d. TR combinational circuit in the hardware:
a. Microprogrammed control unit
186. Which functions are performed by CU: b. Hardwired control unit
a. Data exchange b/w CPU and memory or I/O c. Blockprogrammed control unit
modules d. Macroprogrammed control unit
b. External operations 195. Microprograms are usually stored in:
c. Internal operations inside CPU a. ROM
d. Both a & c b. RAM
c. SAM
187. Which are internal operations inside d. SAN
CPU:
a. Data transfer b/w registers 196. Among them which is the faster control
b. Instructing ALU to operate data unit:
c. Regulation of other internal operations a. Hardwired
d. All of these b. Microprogrammed
c. Both a & b
188. How many paths taken by movement of d. None of these
data in CU:
a. 3 197. For CISC architecture_______
b. 4 controllers are better:
c. 5 a. Microprogrammed
d. 2 b. Hardwired
c. Betterwired
189. 2 data paths in CU are: d. None of these
a. Internal data paths
b. External data paths 198. Full form of FSM is:
c. Both a & b a. Finite state machine
d. None of these b. Fix state machine
c. Fun source metal
190. _______is the data paths link CPU d. All of these
registers with memory or I/O modules:
a. External data paths 199. Rules of FSM are encoded in:
b. Internal data paths a. ROM
c. Boreal data paths b. Random logic
d. Exchange data paths c. Programmable logic array
d. All of these
191. ______is data paths there is movement
of data from one register to another or b/w ALU 200. In RISC architecture access to registers
and a register: is made as a block and register file in a particular
a. External b. Boreal register can be selected by using:
c. Internal d. Exchange a. Multiplexer
b. Decoder
192. Which is the input of control unit: c. Subtractor
a. Master clock signal d. Adder
b. Instruction register c. Flags
d. Control signals from bus
e. All of these
203. Following are 4 major states for ‘load’ 214. Which are tasks for execution of CU or
are: MCU:
a. Fetch b. Decode c. Memory a. Microinstruction execution
d. Write back e. All of these b. Microinstruction sequencing
c. Both a & b d. None of these
204. Jump has 3 major states are:
a. Fetch b.Decode c.Completed.All of these 215. Branching is implemented by depending
on output of:
205. ________ state keeps track of position a. CD b. RG c. CC d. CR
related to execution of an instruction:
a. Major b. Minor c. Both a & b 216. Who determine under what conditions
d. None of these the branching will occur and when:
a. By combination of CD and BT
206. An instruction always starts with b. By combination of CD and BR
state___: c. By combination of CD and CR
d. By combination of TD and BR
a. 1 b. 2 c. 3 d. 0
217. The character U is used to indicate:
207. Decoding of an instruction in RISC a. Undefined transfers
architecture means decision on working of control b. Unfair transfers
unit for: c. Unconditional transfers
a. Remainder of instructions d. All of these
b. Divisor of instructions
c. Dividend of instructions d. None 218. Which field is used to requests for
branching:
208. Which control is used during starting of a. DR b. CR
instruction cycle: c. TR d. BR
a. Write b. Read c. R/W
d. None of these 219. which field is used to determine what
type of transfer occurs:
209. ________function select takes op code in a. CR b. SR
IR translating to function of ALU and it may be c. BR d. MR
compact binary code or one line per ALU:
a. ALU b. CPU c.Memory d. Cache 220. Source statements consist of 5fields in
microinstruction source code are:
210. ________is dependent on instruction a. Lable
type in CU: b. Micro-ops
a. Jump b. Branch c. CD-spec
c. NextPC d. All of these d. BR-spec
e. Address
211. __________dependent on instruction and f. All of these
major state and also comes in starting of data fetch
state as well as write back stage in CU:
a. Register read b. Register write
c. Register R/W d. All of these
4. How many binary selection inputs in the 11. five bits of OPR select one of the operation in
control word: the ____ in control register:
a. 1
b. 7
c. 14 a. CPU
d. 28 b. RISC
c. ALU
d. MUX
5. In control word three fields contain how many
bits:
a. 1 12. The OPR field has how many bits:
b. 2
c. 3
d. 4 a. 2
b. 3
c. 4
6. Three fields contains three bits each so one d. 5
filed has how many bits in control word:
a. 2
b. 4 13. In stack organization the insertion operation is
c. 5 known as ____:
d. 6
a. Pop
7. How is selects the register that receives the b. Push
information from the output bus: c. Both
a. Decoder d. None
b. Encoder
c. MUX
d. All of these 14. In stack organization the deletion operation is
known as ____:
8. A bus organization for seven _____register: a. Pop
a. ALU b. Push
b. RISC c. Both
c. CPU d. None
d. MUX
15. A stack in a digital computer is a part of 21. In register stack items are removed from the
the_____: stack by using the ____operation:
a. ALU
b. CPU a. Push
c. Memory unit b. Pop
d. None of these c. Both
d. None
a. Control word
b. Memory word a. Reverse polish notation
c. Transfer word b. Read polish notation
d. All of these c. Random polish notation
d. None of these
27. In instruction formats instruction is represent 33. 3-Address format can be represented as :
by a________ of bits: a. dst <-[src1][src2]
b. dst ->[src1][src2]
a. Sequence c. dst <->[src1][src2]
b. Parallel d. All of these
c. Both 34. 2- Address format can be represented as:
d. None a. dst ->[dst]*[src]
b. dst<-[dst]*[src]
28. In instruction formats the information c. dst<->[dst]*[src]
required by the ______ for execution: d. All of these
46. Which addressing is an extremely influential 52. In data transfer manipulation designing
way of addressing: as instruction set for a system is a complex_____ :
a. Art
b. System
a. Displacement addressing c. Computer
b. Immediate addressing d. None of these
c. Direct addressing
d. Register addressing
56. In length instruction some programs wants a 62. Which is data manipulation types are:
complex instruction set containing a. Arithmetic instruction
more instruction, more addressing modes and b. Shift instruction
greater address rang, as in case of_____: c. Logical and bit manipulation instructions
d. All of these
a. RISC
b. CISC 63. Arithmetic instruction are used to perform
c. Both operation on:
d. None a. Numerical data
b. Non-numerical data
c. Both
57. In length instruction other programs on the d. None
other hand, want a small and fixed-
size instruction set that contains only a limited 64. How many basic arithmetic operation:
number of opcodes, as in case of_____: a. 1
b. 2
a. RISC c. 3
b. CISC d. 4
c. Both
d. None
65. which are arithmetic operation are:
67. Which operation is used to shift the content of 74. Which is always considered as short jumps:
an operand to one or more bits to provide necessary
variation: a. Conditional jump
a. Logical and bit manipulation b. Short jump
b. Shift manipulation c. Near jump
c. Circular manipulation d. Far jump
d. None of these
68. ________is just like a circular array: 75. Who change the address in the program
a. Data counter and cause the flow of control to be altered:
b. Register
c. ALU a. Shift manipulation
d. CPU b. Circular manipulation
c. Program control instruction
d. All of these
69. Which control refers to the track of the address
of instructions:
76. Which is the common program control
a. Data control instructions are:
b. Register control
c. Program control a. Branch
d. None of these b. Jump
c. Call a subroutine
d. Return
70. In program control the instruction is set for the e. All of these
statement in a: f. None of these
a. Parallel
b. Sequence 77. Which is a type of microprocessor that is
c. Both designed with limited number of instructions:
d. None a. CISC
b. RISC
c. Both
71. How many types of unconditional jumps used d. None
in program control are follows:
78. SMP Stands for:
a. 1 a. System multiprocessor
b. 2 b. Symmetric multiprocessor
c. 3 c. Both
d. 4 d. None
2. In which computers, the binary number are 10. Which are the system of arithmetic, which are
represented by a set of binary storage device such often used in digital system:
as flip flop: a. Binary digit
a. Microcomputer b. Decimal digit
b. Personal computer c. Hexadecimal digit
c. Digital computer d. Octal digit
d. All of these e. All of these
3. A binary number can be converted into 11. In any system, there is an ordered set of
_________: symbols also known as___________:
a. Binary number a. Digital
b. Octal number b. Digit
c. Decimal number c. Both
d. Hexadecimal number d. None of these
4. Which system is used to refer amount of 12. Which is general has two parts in number
things: system:
a. Number system a. Integer
b. Number words b. Fraction
c. Number symbols c. Both
d. All of these d. None of these
5. _________are made with some part of body, 13. MSD stand for:
usually the hands:
a. Most significant digit
a. Number words b. Many significant digit
b. Number symbols c. Both a and b
c. Number gestures d. None of these
d. All of these
14. LSD stand for:
6. __________are marked or written down: a. Less significant digit
a. Number system b. Least significant digit
b. Number words c. Loss significant digit
c. Number symbols d. None of these
d. Number gestures
15. The _____ and ________ of a number is
7. A number symbol is called a ___________: defined as the number of different digits which can
occur in eachposition in the system:
a. Arabic numerals a. Base
b. Numerals b. Radix
c. Both c. Both
d. None of these d. None of these
8. 0,1,2 ,3 ,4,5,6 ,7,8 and 9 numerals are called: 16. Which system has a base or radix of 10:
a. Arabic numerals a. Binary digit
b. String numerals b. Hexadecimal digit
c. Digit numerals c. Decimal digit
d. None of these d. Octal digit
52. How many main approaches to algorithm for 61. 3 bit binary numbers can be represented by
division: ____________:
a. 2 b. 3 a. Binary number b. Decimal number
c. 4 d. 5 c. Hexadecimal number
d. Octal number
53. How many algorithm based on add/subtract
and shift category: 62. A number system that uses eight
a. 2 b. 4 digits,0,1,2,3,4,5,6, and 7 is called an ________:
c. 3 d. 6 a. Binary number system
b. Decimal number system
54. Which are the algorithm based on add/subtract c. Octal number system
and shift category: d. None of these
a. Restoring division 63. Which system each digit has a weight
b. Non-restoring division corresponding to its position:
c. SRT division a. Hexadecimal number system
d. All of these b. Binary number system
c. Decimal number system
55. Several methods for converting a d. Octal number system
___________:
a. Decimal number to a binary number 64. Which odometer is a hypothetical device
b. Binary number to a decimal number similar to the odometer of a car:
c. Octal number to a decimal number a. Binary b. Decimal
d. Hexadecimal number to a binary number c. Hexadecimal d. Octal
56. A popular method knows as double-dabble 65. An __________can be easily converted to its
method also knows as _________: decimal equivalent by multiplying each octal digit
a. Divided-by-one method by positional weight:
b. Divided-by-two method a. Binary number b. Octal number
c. Both d. None of these c. Hexadecimal number
d. Decimal number
57. Which method is used to convert a large
decimal number into its binary equivalent: 66. The simple procedure is to use ___________ :
a. Double dabble method a. Binary-triplet method
b. Divided-by-two-method b. Decimal-triplet method
c. Both c. Octal-triplet method
d. None of these d. All of these
71. Counting in hex, each digit can be increment 81. The exponent contains the decimal number :
from__________: a. +05 b. +03
a. 0 to F b. 0 to G c. +04 d. +07
c. 0 to H d. 0 to J
82. The first or the integer part is known
72. Which number can be converted into binary as________:
numbers by converted each hexadecimal digit to 4 a. Exponent b. Integer
bits binary equivalent using the code: c. Binomial d. None of these
a. Binary number b. Decimal number
c. Octal number d. Hexadecimal number 83. How many bits of mantissa :
a. 4 b. 8
73. One way to convert from decimal to c. 10 d. 16
hexadecimal is the _________:
a. Double dabble method 84. How many bit of exponent:
b. Hex dabble method a. 4 b. 6
c. Binary dabble method c. 8 d. 10
d. All of these
85. Which number is said to be normalized if the
74. Binary numbers can also be expressed in this more significant position of the mantissa contains a
same notation by _________representation: non zero digit:
a. Floating point a. Binary point number
b. Binary point b. Mantissa point number
c. Decimal point c. Floating point number
d. All of these d. None of these
75. How many parts of floating point 86. Which operation with floating point numbers
representation of a number consists: are more complicated then arithmetic operation
a. 4 b. 2 c. 3 d. 5 with fixed point number :
a. Logical operation
76. The first part of floating point represents a b. Arithmetic operation
signed fixed point number called: c. Both
a. Exponent d. None of these
b. Digit
c. Number
d. Mantissa
16. Which are following pointing devices: 25. MICR stands for:
a. Light pen a. Magnetic ink character recognition
b. Joystick b. Magnetic initiate character recognition
c. Mouse c. Both a & b
d. All of these d. None of these
22. A system that enables computer to recognize 30. Output devices commonly referred as:
human voice called:
a. Voice system a. Terminals
b. Voice input system b. Host
c. Input system c. Receivers
d. None of these d. Senders
23. 2 commonly used voice input systems are: 31. Terminals classified in to 2 types are:
a. Micro
b. Microphone a. Hard copy
c. Voice recognition software b. Soft copy
d. Both b & c c. Both a & b
d. None of these
24. Optical scanner devices are:
a. MICR 32. VDU stands for:
b. OMR
c. OCR a. Video display unit
d. All of these b. Visual display unit
c. Visual data unit
d. None of these
34. LCD stands for: 43. In_______ printing, each character is printed
a. Liquid crystal display on the paper by striking a pin or hammer against an
b. Liquid catalog display inked ribbon:
c. Liquid crystal data
d. Liquid code display a. Non-impact printing
b. Impact printing
35. The size of monitor ranges from: c. Both a & b
d. None of these
a. 12-12 inch
b. 12-21 inch 44. Dot matrix printer is 2 types is:
c. 21-12 inch
d. 21-11 inch a. Daisy wheels
b. Matrix printer
36. Range of color depends on: c. High quality matrix printer
a. Number of bits code lines with each pixel d. Both a & c
b. Number of bits associated with each pixel
c. Number of instructions associated with each 45. In daisy wheel printer can print 40
pixel character/second and bold characters are achieved
d. Number of code associated with each pixel by overprinting the text:
55. IDE is a_________ controller: 63. There are 2 ways in which addressing can be
done in memory and I/O device:
a. Disk a. Isolated I/O
b. Floppy b. Memory-mapped I/O
c. Hard c. Both a & b
d. None of these d. None of these
64. Advantages of isolated I/O are: 72. All the operations in a digital system are
a. Commonly usable synchronized by a clock that is generated by:
b. Small number of I/O instructions a. Clock
c. Both a & b b. Pulse
d. None of these c. Pulse generator
d. Bus
65. In _______ addressing technique separate
address space is used for both memory and I/O 73. Asynchronous means:
device: a. Not in step with the elapse of address
a. Memory-mapped I/O b. Not in step with the elapse of control
b. Isolated I/O c. Not in step with the elapse of data
c. Both a & b d. Not in step with the elapse of time
d. None of these
74. ________is a single control line that informs
66. _______is a single address space for storing destination unit that a valid is available on the bus:
both memory and I/O devices: a. Strobe
a. Memory-mapped I/O b. Handshaking
b. Isolated I/O c. Synchronous
c. Separate I/O d. Asynchronous
d. Optimum I/O
75. What is disadvantage of strobe scheme:
67. Following are the disadvantages of memory- a. No surety that destination received data
mapped I/O are: before source removes it
a. Valuable memory address space used up b. Destination unit transfer without knowing
b. I/O module register treated as memory whether source placed data on data bus
addresses c. Can’t said
c. Same machine intersection used to access d. Both a & b
both memory and I/O device
d. All of these 76. In_______ technique has 1 or more control
signal for acknowledgement that is used for
68. Who determine the address of I/O interface: intimation:
a. Register select a. Handshaking
b. Chip select b. Strobe
c. Both a & b c. Both a & b
d. None of these d. None of these
69. 2 control lines in I/O interface is: 77. The keyboard has a__________ asynchronous
a. RD, WR transfer mode:
b. RD,DATA a. Parallel
c. WR, DATA b. Serial
d. RD, MEMORY c. Optimum
d. None
70. In I/O interface RS1 and RS0 are used for
selecting: 78. In _______transfer each bit is sent one after the
a. Memory another in a sequence of event and requires just one
b. Register line:
c. CPU a. Serial b. Parallel
d. Buffer c. Both a & b d. None of these
71. If CPU and I/O interface share a common bus 79. Modes of transfer b/w computer and I/O device
than transfer of data b/w 2 units is said to be: are:
a. Synchronous a. Programmed I/O
b. Asynchronous b. Interrupt-initiated I/O
c. Clock dependent c. DMA
d. Decoder independent d. Dedicated processor such as IOP and DCP
e. All of these
80. ______operations are the results of I/O 88. User programs interact with I/O devices
operations that are written in the computer through:
program:
a. Programmed I/O a. Operating system
b. DMA b. Hardware
c. Handshaking c. Cpu
d. Strobe d. Microprocessor
81. _______is a dedicated processor that combines 89. Which table handle store address of interrupt
interface unit and DMA as one unit: handling subroutine:
a. Input-Output Processor
b. Only input processor a. Interrupt vector table
c. Only output processor b. Vector table
d. None of these c. Symbol link table
d. None of these
82. ______is a special purpose
dedicated processor that is designed specially 90. Which technique is used that identifies the
designed for data transfer in network: highest priority resource by means of software:
a. Data Processor
b. Data Communication Processor a. Daisy chaining
c. DMA Processor b. Polling
d. Interrupt Processor c. Priority
d. Chaining
83. ______processor has to check continuously till
device becomes ready for transferring the data: 91. ________interrupt establishes a priority over
a. Interrupt-initiated I/O the various sources to determine which request
b. DMA should be entertained first:
c. IOP
d. DCP a. Priority interrupt
b. Polling
84. Interrupt-driven I/O data transfer technique is c. Daisy chaining
based on______ concept: d. None of these
a. On demand processing
b. Off demand processing 92. _____method is used to establish priority by
c. Both a & b serially connecting all devices that request an
d. None of these interrupt:
87. Which exception is also called software 94. VAD stands for:
interrupt:
a. Interrupt a. Vector address
b. System calls b. Symbol address
c. Traps c. Link address
d. All of these d. None of these
112. Multiprocessor use ________ than two 120. The memory capacity in system is
CPUs assembled in single system unit: considered because the connecting processors are
a. One or More used______:
b. Two or More
c. One or One a. Network
d. Two or Two b. Internet
c. Intranet
113. Which refers the execution of various d. None of these
software process concurrently:
a. Multiprocessor 121. Intercrosses arbitration system for
b. Serial communication multiprocessor shares a _________:
c. DCP
d. IOP a. Primary bus
b. Common bus
114. Which is used for this and known as high c. Domain bus
speed buffer exist with almost each process? d. All of these
127. Which signal on bus applies +1 to the 134. In which condition busy waiting,
priority of resolution circuits of the arbitration programmer error, deadlock or circular wait occurs
designate a new arbitration: in interprocessing:
a. BM4
b. BAL a. Synchronization problem
c. BNA b. No preemption
d. DBA c. Hold and wait
d. None of these
128. Which signal create 3 lines of bus in
which signals from the encoded number of 135. Mechanism can be referred to as adding
processors: a new facility to the system hence known as
a. BM1 to BM3 _______:
b. BAL
c. Both a. Process
d. None of these b. Arbitration
c. Both a & b
129. Which signal request the validation d. None of these
signal make active if its logic level is 0 and validate
signals from BM1 to BM3: 136. Which is a mechanism used by the OS to
ensure a systematic sharing of resources amongst
a. BAL concurrent resources:
b. BM4
c. BNA a. Process synchronous
d. All of these b. Process system
c. Process synchronization
130. Which signal represents synchronization d. All of these
signal decided by interprocess arbitration with a
certain delay or signal DMA: 137. _________ is basically sequence of
instructions with a clear indication of beginning
a. BAL and end for updating shared variables
b. BNA
c. Both a. Critical section
d. None of these b. Entry section
c. Remainder section
131. In which condition only one process d. All of these
holds a resource at a given time:
138. Which provides a direct hardware
a. Mutual exclusion support to mutual exclusion
b. Hold and wait
c. Both a. Test-and-set(TS)
d. None of these b. Swap instruction
c. Wait instruction
132. In which condition one process holds the d. Signal instruction
allocated resources and other waits for it:
139. A process waiting to enter its critical
a. No preemption section may have to wait for unduly_______:
b. Hold and wait a. Short time or may have to wait forever
c. Mutual exclusion b. Long time or may have to wait forever
d. All of these c. Short time or may have to wait for long time
d. Long time or may have to wait for short time
133. In which condition resource is not 140. Which is a modified version of the TS
removed from a process holding: instruction which is designed to remove busy-
waiting:
a. Synchronization problem a. Swap instruction
b. No preemption b. Wait instruction
c. Hold and wait c. Signal instruction
d. None of these d. Both b & c
157. Which section refer to the code segment 164. The problem of readers and writers was
where a shared resource is accessed by the process: first formulated by ________:
a. Reminder section
b. Entry section a. P.J. Courtois
c. Both b. F.Heymans
d. None of these c. D.L. Parnas
d. All of these
158. Which section is the remaining part of a
process’s code: 165. Which is a situation in which some
a. Racing section process wait for each other’s actions indefinitely:
b. Critical section
c. Entry section a. Operating system
d. Reminder section b. Deadlock
c. Mutex
159. How many conditions for controlling d. None of these
access to critical section:
166. _________system handles only
a. 2 deadlocks caused by sharing of resources in the
b. 4 system:
c. 3
d. 5 a. Operating system
b. Deadlock
160. Which instruction provides a direct c. Mutex
hardware support to mutual exclusion: d. None of these
172. How many methods for handling 181. The various file operation are:
deadlocks: a. Crating a file b. Writing a file
a. 1 b. 2 c. Reading a file
c. 3 d. 4 d. Repositioning within a file
e. Deleting a file truncating a file
173. Which are the method for handling f. All of these
deadlocks:
182. Which operations are to be performed on
a. Deadlock prevention a directory are:
b. Deadlock avoidance a. Search for a file b. Create a file
c. Deadlock detection c. Delete a file d. List a directory
d. All of these e. Rename a file
f. Traverse the file system
174. How many condition that should be met g. All of these
in order to produce a deadlock:
183. Which memory is assembled between
a. 2 b. 4 main memory and CPU:
c. 6 d. 8 a. Primary memory b. Cache memory
c. Both a & b d. None of these
175. Which are the condition that should be
met in order to produce a deadlock: 184. Which is considered as semi-conductor
memory , which is made up of static RAM:
a. Mutual exclusion b. Hold and Wait a. Primary memory b. Cache memory
c. No preemption c. Both a & b d. None of these
d. Circular wait e. All of these
185. Which is one of the important I/O
176. In protocol each process can make a devices and is most commonly used as permanent
request only in an ________: storage device in any processor:
a. Soft disk b. Hard disk
a. Increasing order b. Decreasing order c. Both a & b d. None of these
c. Both a & b d. None of these
186. ______ can read any printed character by
177. In protocol above mentioned comparing the pattern that is stored in the
________protocol are used then the circular wait- computer:
condition can not hold: a. SP b. CCR
c. RAG d. OCR
a. 1 b. 2
c. 3 d. 4 187. Which system is a typical example of the
readers and writers problem:
178. Which state refers to a state that is not a. Airline reservation system
safe not necessarily a deadlocked state: b. Airport reservation system
c. Both
a. Safe state b. Unsafe state d. None of these
c. Both a & b d. None of these 188. Which lock can arise when two
processes wait for phone calls from one another:
179. ________ a direct arrow is drawn from
the process to the resource rectangle to represent a. Spine lock b. Dead lock
each pending resource request: c. Both d. None of these
a. TS b. SP
c. CCR d. RAG 189. Which lock is more serious than
indefinite postponement or starvation because it
180. The attributes of a file are: affect more than one job:
a. Name b. Identifier
c. Types d. Location a. Deadlock b. Spinelock
e. Size f. Protection c. Both d. None of these
g. Time, date and user identification
h. All of these