Schemat Dell

5 4 3 2 1
MODEL NAME : Maple

PCB NO : DA8000WL000 LA-B012PR01
D D
C C
Dell / Compal Confidential

Schematic Document
Intel Shark Bay ULT
B
Maple 14"/15" Value B
UMA / DIS AMD 25W/S3+DDR3x4

2014-01-21 Rev: 1.0
A A
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/01/20 Deciphered Date 2015/01/19 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(1,2/19) eDP,XDP,MISC
Size Document Number Rev
http://sualaptop365.edu.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B012P
Date: Tuesday, August 05, 2014 Sheet 1 of 55
5 4 3 2 1
5 4 3 2 1
D D
VRAM 128M*16 32bit

AMD 25W
DDR 3 *2 PEG 2.0 x4
S3-64 23x23
VRAM 128M*16 32bit
Page 34~38
DDR 3 *2 Memory Bus (DDR3L) DDRIII-DIMM X2
Page 39~40 Dual Channel
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
1.35V DDR3L 1600 MHz
Page 17,18
eDP Conn. eDP 8GB Max

Page 31
USB 3.0 Port 1

HDMI Conn. DDI Intel USB 3.0 Conn. 1
Port 0
Page 20 Broadwell ULT-U Page 26
Processor USB2.0 Port 2

Port 1 USB 3.0 Conn. 2
BGA 1168 Page 26
C C
Port 2
USB 2.0 Conn. 3
PCI-E Page 24
x1 x1
Port 6 Port 3
Port 4 NGFF 2230
NGFF 2230 Ethernet WiFi/WiGi/BT4.0 Page 26
WiFi/WiGi RTL8106E
/BT4.0 Port 7 Digital Camera
Page 26 Page 21
(With Digital MIC) Page 31
Port 5
Touch Screen
Page 31
Port 6 Card Reader

RTS5179 Page 25
SATA HDD Conn. Port 0 SATA Rediver SATA3.0

Page 32
B B
Digital Mic.
HD Audio Audio Codec Headphone Jack /

ALC3234 Mic. Jack combo
Page 22
SPI ROM SPI Int. Speaker R / L

8MB Page 4~14
Page 9
LPC Bus
I2C
33MHz
ENE KBC PS/2

Int.KBD KB9012 Page 30 Touch Pad
Page 27 Page 27
A A

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B012P
5 4 3 2 1
5 4 3 2 1
Compal Confidential
File Name : LA-B012P
D D
C C
USB
FFC RJ45
16 pin
CardReader Slot HDMI
USB
CardReader/B USB
Audio Jack
B B
FFC
8 pin M/B
LED/B
A A

Size
Document Number Rev
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
Board ID Table for AD channel

Vcc 3.3V +/- 1%
Ra 100K +/- 1% HSW BOARD ID Table
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID UMA DIS(JET) DIS(Topaz)
0 0 0.000V 0.000V 0.300V 0x00 - 0x0B 0 SSI USB3.0
1 12K +/- 1% 0.347V 0.354V 0.360V 0x0C - 0x1C 1 SSI
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1D - 0x26 2 SSI Port1 USB connector 1
D D
3 20K +/- 1% 0.541V 0.550V 0.559V 0x27 - 0x30 3 PT
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3B 4 PT Port2 USB connector 2
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3C - 0x46 5 PT
6 43K +/- 1% 0.978V 0.992V 1.006V 0x47 - 0x54 6 ST Port3
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64 7 ST
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76 8 ST Port4
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87 9 1.0
10 130K +/- 1% 1.849V 1.865V 1.881V 0x88 - 0x96 10 1.0 USB2.0
11 160K +/- 1% 2.015V 2.031V 2.046V 0x97 - 0xA3 11 1.0
12 200K +/- 1% 2.185V 2.200V 2.215V 0xA4 - 0xAD Port0 USB connector 1
13 240K +/- 1% 2.316V 2.329V 2.343V 0xAE - 0xB7
14 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xC0 BDW BOARD ID Table Port1 USB connector 2
15 330K +/- 1% 2.521V 2.533V 2.544V 0xC1 - 0xC9 Board ID UMA DIS(JET) DIS(Topaz)
16 430K +/- 1% 2.667V 2.677V 2.687V 0xCA - 0xD3 0 Pre-SSI Port2 USB connector 3 (D/B)
17 560K +/- 1% 2.791V 2.800V 2.808V 0xD4 - 0xDC 1 Pre-SSI
18 750K +/- 1% 2.905V 2.912V 2.919V 0xDD - 0xE6 2 Pre-SSI Port3
C C
19 NC 3.000V 3.300V 3.300V 0xE7 - 0xFF 3 SSI
4 SSI Port4 MINI Card (WLAN)
SMBUS Control Table
5 SSI
6 PT Port5 Touch Screen Panel
SOURCE BATT Charger VGA DIMM XDP Thermal Sensor FFS 7 PT
8
ULT Port6 Card Reader
PT
EC_SMB_CK1
EC_SMB_DA1
KB9012
V V 9 ST
Port7 Camera
10 ST
EC_SMB_CK2
EC_SMB_DA2
KB9012
V V 11 ST
PCI EXPRESS
12 1.0
SMBCLK
SMBDATA
ULT
V V V 13 1.0
Lane 1
Link 14 1.0
SML0CLK ULT
SML0DATA Lane 2
SML1CLK ULT
SML1DATA Lane 3 10/100 LAN
B B
Lane 4 MINI Card (WLAN)
Lane 5 PEG (AMD JET/TOBAZ)

CLOCK SIGNAL
Lane 6
CLKOUT_PCIE0
Symbol Note : SATA
CLKOUT_PCIE1
: means Digital Ground SATA0 HDD
CLKOUT_PCIE2 10/100 LAN
SATA1
: means Analog Ground CLKOUT_PCIE3 MINI Card (WLAN)
SATA2
CLKOUT_PCIE4 dGPU
SATA3
A A
CLKOUT_PCIE5

Size
Document Number Rev
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
2.2K 10K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH 10K
+3VS
D N-MOS 202
D
AP2 MEM_SMBCLK DDR_XDP_WLAN_TP_SMBCLK DIMM1 SMBUS Address [A0]
N-MOS 200
AH1 MEM_SMBDATA DDR_XDP_WLAN_TP_SMBDAT
1K
202 DIMM2
+3.3V_ALW_PCH SMBUS Address [A4]
1K 200
AN1 SML0CLK
MCH 0 ohm
AK1 SML0DATA DDR_XDP_SMBCLK_R1 53 XDP1 SMBUS Address [TBD]
Shark bay 0 ohm 51
2.2K DDR_XDP_SMBDAT_R1
+3.3V_ALW_PCH
2.2K
N-MOS
AN1 SML1_SMBCLK EC_SMB_CK2
N-MOS
AK1 SML1_SMBDATA EC_SMB_DA2
C 2.2K C
+3VALW
2.2K
79 EC_SMB_CK2
80 EC_SMB_DA2
2.2K
+3VS_VGA
2.2K
N-MOS T4
VGA_SMB_CK2 UV28 GPU SMBUS Address [0xXX]
N-MOS VGA_SMB_DA2 T3
2.2K
2.2K
+3VALW
77 EC_SMB_CK1
0 ohm 11
SCL PU701 POWER
Charger SMBUS Address [0x12]
0 ohm
KBC
B B
78 EC_SMB_DA1 SDA 10
KB9012A4 100 ohm 3 4 3

PD1 BAT_ALERT PBATT BATT SMBUS Address [0x16]
100 ohm CONN
1 6 BATT_PRS 5
A A

1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
i3-4020U-15W-GT2-MP
UC1 I3R1@ UC2 I3R3@
UC3A HASWELL_MCP_E
CL8064701552800 QEZ5 D0 1.8G CL8064701478202 SR16Q C1 1.7G A31!
SA00007MG0L SA00006SX2L TBD
DDI1_LANE_N0 C54 C45

<20> DDI1_LANE_N0 DDI1_TXN0 EDP_TXN0 EDP_TX0# <31>
i5-4210U-15W-GT2-MP DDI1_LANE_P0 C55 B46
D <20> DDI1_LANE_P0 DDI1_TXP0 EDP_TXP0 EDP_TX0 <31>
DDI1_LANE_N1 B58 A47 D
<20> DDI1_LANE_N1 DDI1_TXN1 EDP_TXN1 EDP_TX1# <31>
DDI1_LANE_P1 C58 B47
<20> DDI1_LANE_P1 DDI1_TXP1 EDP_TXP1 EDP_TX1 <31>
UC4 I5R1@ UC5 I5R3@ DDI1_LANE_N2 B55
<20> DDI1_LANE_N2 DDI1_TXN2
DDI1_LANE_P2 A55 C47
<20> DDI1_LANE_P2 DDI1_TXP2 EDP_TXN2
DDI1_LANE_N3 A57 C46
<20>
<20>
DDI1_LANE_N3
DDI1_LANE_P3
DDI1_LANE_P3 B57 DDI1_TXN3 EDP_TXP2 A49 COMPENSATION PU FOR eDP
DDI1_TXP3 DDI EDP EDP_TXN3 B49
C51 EDP_TXP3
UC6 QG21@ C50 DDI2_TXN0 A45 +VCCIOA_OUT
CL8064701477802 QEAK D0 1.7G CL8064701477702 SR170 C1 1.6G A31! DDI2_TXP0 EDP_AUXN EDP_AUX# <31>
C53 B45
DDI2_TXN1 EDP_AUXP EDP_AUX <31>
SA00007LO0L SA00006SM3L TBD B54
C49 DDI2_TXP1 D20 EDP_COMP 2 1
B50 DDI2_TXN2 EDP_RCOMP A43 EDP_DISP_UTIL 1 2 24.9_0402_1%~D RC2
DDI2_TXP2 EDP_DISP_UTIL EDP_BIA_PWM <10,31>
i7-4510U-15W-GT2-MP A53
B53 DDI2_TXN3 @
CL8065801674128 QG21 C0 1.2G DDI2_TXP3 CAD Note:Trace width=20 mils ,Spacing=25mil,
Broadwell RC1
UC7 I7R1@ UC8 I7R3@ SA00007OS0L 0_0402_5% Max length=100 mils.
UC9 QFSY@ UC10 QG22@ 1 OF 19 Rev1p2
@
CL8064701477301 QEAF D0 2G BGA CL8064701477202 SR16Z C1 1.8G A31!
SA00007M70L SA00006SL2L TBD
CL8064701614813 QFSY C0 1.6G CL8065801675027 QG22 C0 1.2G
SA00007AM0L SA00007OT0L
+1.05VS_PCH
+3VS
+1.05VS_PCH +1.05VS_PCH
0.1U_0402_10V7K
0.1U_0402_10V7K
CC1
2 1 1 1
UC11 @ JXDP1
CC2
XDP@
CC3
XDP@
0.1U_0402_10V7K 1 2
14 XDP_PREQ# 3 GND0 GND1 4 CFG17
VCC 2 2 OBSFN_A0 OBSFN_C0 CFG17 <16>
XDP_PRDY# 5 6 CFG16
OBSFN_A1 OBSFN_C1 CFG16 <16>
PCH_JTAG_TDO 1 @ 2 TDO_XDP 2 3 XDP_TDO 7 8 PLT_RST#
C <8> PCH_JTAG_TDO 1A 1B GND2 GND3
RC3 0_0402_1% CFG0 9 10 CFG8 1
C
<16> CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 <16>
CFG1 11 12 CFG9 CC4 ESD@
<16> CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 <16>
RUNPWROK 1 13 14
1OE CFG2 15 GND4 GND5 16 CFG10 0.047U_0402_16V4Z
<16> CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 <16> 2
1 @ 2 TDI_XDP 1 @ 2 TDI_XDP_R 5 6 XDP_TDI CFG3 17 18 CFG11
<8> PCH_JTAG_TDI 2A 2B <16> CFG3 OBSDATA_A3 OBSDATA_C3 CFG11 <16>
RC4 0_0402_1% RC5 0_0402_1% 19 20
Place near JXDP1 XDP_OBS0_R 21 GND6 GND7 22 CFG19
RUNPWROK 4 XDP_OBS1_R 23 OBSFN_B0 OBSFN_D0 24 CFG18
CFG19 <16> Place CC30
2OE OBSFN_B1 OBSFN_D1 CFG18 <16> close to RC51.1
25 26
1 @ 2 TMS_XDP 9 8 XDP_TMS CFG4 27 GND8 GND9 28 CFG12
<8> PCH_JTAG_TMS 3A 3B <16> CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 <16>
RC6 0_0402_1% CFG5 29 30 CFG13
<16> CFG5 OBSDATA_B1 OBSDATA_D1 CFG13 <16>
31 32
RUNPWROK 10 CFG6 33 GND10 GND11 34 CFG14
3OE <16> CFG6 OBSDATA_B2 OBSDATA_D2 CFG14 <16>
CFG7 35 36 CFG15
<16> CFG7 OBSDATA_B3 OBSDATA_D3 CFG15 <16>
TRST#_XDP 12 11 XDP_TRST# 37 38
RUNPWROK 4A 4B H_CPUPWRGD RC7 1 XDP@ 2 1K_0402_5% H_VCCST_PWRGD_XDP 39 GND12 GND13 40 CLK_XDP RC8 1 XDP@ 2 0_0402_5%
PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_ITP <9>
1 RC9 1 XDP@ 2 0_0402_5% CFD_PWRBTN#_XDP 41 42 CLK_XDP# RC10 1 XDP@ 2 0_0402_5%
<10,30> PBTN_OUT# HOOK1 ITPCLK#/HOOK5 CLK_CPU_ITP# <9>
CC5 ESD@ RUNPWROK 13 7 43 44
<30> RUNPWROK 4OE GND VCC_OBS_AB VCC_OBS_CD
RC11 1 XDP@ 2 0_0402_5% CPU_PWR_DEBUG#_R 45 46 XDP_RST#_R 2 1 PLT_RST# PLT_RST# <10,21,26,30,34>
<13> CPU_PWR_DEBUG# HOOK2 RESET#/HOOK6
0.1U_0402_10V7K 15 SYS_PWROK RC12 1 XDP@ 2 0_0402_5% SYS_PWROK_XDP 47 48 XDP_DBRESET# 2 1
2 GND PAD <10,30> SYS_PWROK HOOK3 DBR#/HOOK7 +3VS
49 50 RC13
1 8 DDR_XDP_SMBDAT_R1 51 GND14 GND15 52 TDO_XDP 1K_0402_5% RC14
<17,18,32,9> DDR_XDP_WLAN_TP_SMBDAT SDA TD0
Place CC29 74CBTLV3126BQ_DHVQFN14_2P5X3 2 7 DDR_XDP_SMBCLK_R1 53 54 TRST#_XDP 1K_0402_1%
<17,18,32,9> DDR_XDP_WLAN_TP_SMBCLK SCL TRST# XDP@
3 6 55 56 TDI_XDP 1 2
close to UC4 PCH_JTAG_TCK 4 5 XDP_TCLK 57 TCK1 TDI 58 TMS_XDP
59 TCK0 TMS 60 CFG3_R 1 2 CFG3 CC6
RP1 GND16 GND17 RC15 1K_0402_5% 0.1U_0402_10V7K
0_8P4R_5% SAMTE_BSH-030-01-L-D-A XDP@
reference Shark Bay ULT Validation Customer Debug Port XDP@ CONN@
Implementation Requirement Rev 1.0
+3VALW_PCH
+1.05VS_PCH
2
1 2 H_CATERR#
@ RC16 49.9_0402_1% PCH_JTAG_RST# 2 @ 1 XDP_TRST# @
1 2 H_PROCHOT# 0_0402_1% RC17 RC19
RC18 62_0402_5% 1K_0402_5% XDP_DBRESET# 1 @ 2 SYS_RESET#
SYS_RESET# <10>
1 @ 2 XDP_TCLK
<8> PCH_JTAG_JTAGX
1
0_0402_1% RC21 RC20
SYS_PWROK_XDP 0_0402_1%
2 1 TDO_XDP
B 0_0402_5% XDP@ RC22 B
1
ESD@
PCH_JTAG_TDO 2 1 TDI_XDP_R CC7
0_0402_5% XDP@ RC23 0.1U_0402_10V7K
2
PCH_JTAG_TCK 2 1 XDP_TCLK
<8> PCH_JTAG_TCK
0_0402_5% XDP@ RC24
Place near JXDP1.47
H_CPUPWRGD
UC3B HASWELL_MCP_E
1
1
RC25 CC8 D61
10K_0402_5% 100P_0402_50V8J H_CATERR# K61 PROC_DETECT MISC
@EMI@ PECI_EC N62 CATERR J62 XDP_PRDY#
2 <30> PECI_EC PECI PRDY +1.05VS_PCH
K62 XDP_PREQ# PU/PD for JTAG signals
2
JTAG
PREQ E60 XDP_TCK
PROC_TCK E61 XDP_TMS
ESD solution 1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST# 1 2 PCH_JTAG_RST#
<30,44> H_PROCHOT# PROCHOT PROC_TRST PCH_JTAG_RST# <8>
RC26 56_0402_5% THERMAL F63 XDP_TDI XDP_TMS 1 8
PROC_TDI F62 XDP_TDO @ XDP_TDI 2 7
PROC_TDO R1 XDP_PREQ# 3 6
CAD Note: H_CPUPWRGD C61 0_0402_5% TDO_XDP 4 5
Avoid stub in the PWRGD path H_PROCHOT# PROCPWRGD PWR
J60 XDP_OBS0_R RC27 1 @ 2 0_0402_1%
while placing resistors RC115 BPM#0 H60 XDP_OBS1_R RP2 @
1 BPM#1
@EMI@ H61 @ T1 51_8P4R_5%
CC9 BPM#2 H62 @ T2
22P_0402_50V8J SM_RCOMP0 AU60 BPM#3 K59 @ T3 XDP_TDO 1 8
DDR3 COMPENSATION SIGNALS 2 SM_RCOMP1 AV60 SM_RCOMP0
SM_RCOMP1
DDR3 BPM#4
BPM#5
H63 @ T4 XDP_TCK 2 7
SM_RCOMP2 AU61 K60 @ T5 XDP_TRST# 3 6
AV15 SM_RCOMP2 BPM#6 J61 @ T6 4 5
<17> DDR3_DRAMRST#_CPU SM_DRAMRST BPM#7
200_0402_1% 2 1 RC28 SM_RCOMP0 AV61
<17> DDR_PG_CTRL SM_PG_CNTL1 RP3
120_0402_1% 2 1 RC29 SM_RCOMP1 51_8P4R_5%
2 OF 19 Rev1p2
100_0402_1% 2 1 RC30 SM_RCOMP2
A A
@
CAD Note:
Trace width=12~15 mil, Spcing=20 mils DDR3_DRAMRST#_CPU
Max trace length= 500 mil CC10 @ESD@
1
0.047U_0402_16V4Z
2
Place CC35
on BOT Security Classification Compal Secret Data Compal Electronics, Inc.
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
Interleaved Memory
HASWELL_MCP_E
UC3D
HASWELL_MCP_E <17> DDR_A_D[32..47]
D UC3C D
<17> DDR_A_D[0..15] AH63 AU37 AY31 AM38

DDR_A_D0 M_CLK_DDR#0 DDR_A_D32 M_CLK_DDR#2
AH62 SA_DQ0 SA_CLK#0 AV37 M_CLK_DDR#0 <17> AW31 SB_DQ0 SB_CK#0 AN38 M_CLK_DDR#2 <18>
DDR_A_D1 M_CLK_DDR0 DDR_A_D33 M_CLK_DDR2
AK63 SA_DQ1 SA_CLK0 AW36 M_CLK_DDR0 <17> AY29 SB_DQ1 SB_CK0 AK38 M_CLK_DDR2 <18>
DDR_A_D2 M_CLK_DDR#1 DDR_A_D34 M_CLK_DDR#3
AK62 SA_DQ2 SA_CLK#1 AY36 M_CLK_DDR#1 <17> AW29 SB_DQ2 SB_CK#1 AL38 M_CLK_DDR#3 <18>
DDR_A_D3 M_CLK_DDR1 DDR_A_D35 M_CLK_DDR3
AH61 SA_DQ3 SA_CLK1 M_CLK_DDR1 <17> AV31 SB_DQ3 SB_CK1 M_CLK_DDR3 <18>
DDR_A_D4 DDR_A_D36
DDR_A_D5 AH60 SA_DQ4 AU43 DDR_CKE0_DIMMA DDR_A_D37 AU31 SB_DQ4 AY49 DDR_CKE2_DIMMB
AK61 SA_DQ5 SA_CKE0 AW43 DDR_CKE0_DIMMA <17> AV29 SB_DQ5 SB_CKE0 AU50 DDR_CKE2_DIMMB <18>
DDR_A_D6 DDR_CKE1_DIMMA DDR_A_D38 DDR_CKE3_DIMMB
AK60 SA_DQ6 SA_CKE1 AY42 DDR_CKE1_DIMMA <17> AU29 SB_DQ6 SB_CKE1 AW49 DDR_CKE3_DIMMB <18>
DDR_A_D7 DDR_A_D39
DDR_A_D8 AM63 SA_DQ7 SA_CKE2 AY43 DDR_A_D40 AY27 SB_DQ7 SB_CKE2 AV50
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_A_D41 AW27 SB_DQ8 SB_CKE3
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_CS0_DIMMA# DDR_A_D42 AY25 SB_DQ9 AM32 DDR_CS2_DIMMB#
AP62 SA_DQ10 SA_CS#0 AR32 DDR_CS0_DIMMA# <17> AW25 SB_DQ10 SB_CS#0 AK32 DDR_CS2_DIMMB# <18>
DDR_A_D11 DDR_CS1_DIMMA# DDR_A_D43 DDR_CS3_DIMMB#
AM61 SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <17> AV27 SB_DQ11 SB_CS#1 DDR_CS3_DIMMB# <18>
DDR_A_D12 DDR_A_D44
DDR_A_D13 AM60 SA_DQ12 AP32 DDR_A_D45 AU27 SB_DQ12 AL32
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_A_D46 AV25 SB_DQ13 SB_ODT0
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_A_RAS# DDR_A_D47 AU25 SB_DQ14 AM35 DDR_B_RAS#
<18> DDR_B_D[0..15] AP58 SA_DQ15 SA_RAS AW34 DDR_A_RAS# <17> <18> DDR_B_D[32..47] AM29 SB_DQ15 SB_RAS AK35 DDR_B_RAS# <18>
DDR_B_D0 DDR_A_WE# DDR_B_D32 DDR_B_WE#
AR58 SA_DQ16 SA_WE AU34 DDR_A_WE# <17> AK29 SB_DQ16 SB_WE AM33 DDR_B_WE# <18>
DDR_B_D1 DDR_A_CAS# DDR_B_D33 DDR_B_CAS#
AM57 SA_DQ17 SA_CAS DDR_A_CAS# <17> AL28 SB_DQ17 SB_CAS DDR_B_CAS# <18>
DDR_B_D2 DDR_B_D34
DDR_B_D3 AK57 SA_DQ18 AU35 DDR_A_BS0 DDR_B_D35 AK28 SB_DQ18 AL35 DDR_B_BS0
AL58 SA_DQ19 SA_BA0 AV35 DDR_A_BS0 <17> AR29 SB_DQ19 SB_BA0 AM36 DDR_B_BS0 <18>
DDR_B_D4 DDR_A_BS1 DDR_B_D36 DDR_B_BS1
AK58 SA_DQ20 SA_BA1 AY41 DDR_A_BS1 <17> AN29 SB_DQ20 SB_BA1 AU49 DDR_B_BS1 <18>
DDR_B_D5 DDR_A_BS2 DDR_B_D37 DDR_B_BS2
AR57 SA_DQ21 SA_BA2 DDR_A_BS2 <17> AR28 SB_DQ21 SB_BA2 DDR_B_BS2 <18>
DDR_B_D6 DDR_B_D38
AN57 SA_DQ22 AU36 DDR_A_MA[0..15] <17> AP28 SB_DQ22 AP40 DDR_B_MA[0..15] <18>
DDR_B_D7 DDR_A_MA0 DDR_B_D39 DDR_B_MA0
DDR_B_D8 AP55 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D40 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_B_D9 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D41 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_B_D10 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D42 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_B_D11 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D43 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_B_D12 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D44 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_B_D13 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D45 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_B_D14 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D46 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_B_D15 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D47 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
<17> DDR_A_D[16..31] AY58 SA_DQ31 SA_MA8 AU40 <17> DDR_A_D[48..63] AY23 SB_DQ31 SB_MA8 AU46
DDR_A_D16 DDR_A_MA9 DDR_A_D48 DDR_B_MA9
DDR_A_D17 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_A_D49 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D18 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_A_D50 AY21 SB_DQ33 DDR CHANNEL B SB_MA10 AV47 DDR_B_MA11
C SA_DQ34 SA_MA11 SB_DQ34 SB_MA11 C
DDR_A_D19 AW56 DDR CHANNEL A AU41 DDR_A_MA12 DDR_A_D51 AW21 AU47 DDR_B_MA12
DDR_A_D20 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_A_D52 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D21 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_A_D53 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D22 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_A_D54 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D23 AU56 SA_DQ38 SA_MA15 DDR_A_D55 AU21 SB_DQ38 SB_MA15
SA_DQ39 DDR_A_DQS#[0..1] <17> SB_DQ39 DDR_A_DQS#[4..5] <17>
DDR_A_D24 AY54 AJ61 DDR_A_DQS#0 DDR_A_D56 AY19 AW30 DDR_A_DQS#4
DDR_A_D25 AW54 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_A_D57 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_A_DQS#5
SA_DQ41 SA_DQSN1 DDR_B_DQS#[0..1] <18> SB_DQ41 SB_DQSN1 DDR_B_DQS#[4..5] <18>
DDR_A_D26 AY52 AM58 DDR_B_DQS#0 DDR_A_D58 AY17 AN28 DDR_B_DQS#4
DDR_A_D27 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_B_DQS#1 DDR_A_D59 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#5
SA_DQ43 SA_DQSN3 DDR_A_DQS#[2..3] <17> SB_DQ43 SB_DQSN3 DDR_A_DQS#[6..7] <17>
DDR_A_D28 AV54 AV57 DDR_A_DQS#2 DDR_A_D60 AV19 AW22 DDR_A_DQS#6
DDR_A_D29 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#3 DDR_A_D61 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_A_DQS#7
SA_DQ45 SA_DQSN5 DDR_B_DQS#[2..3] <18> SB_DQ45 SB_DQSN5 DDR_B_DQS#[6..7] <18>
DDR_A_D30 AV52 AL43 DDR_B_DQS#2 DDR_A_D62 AV17 AN21 DDR_B_DQS#6
DDR_A_D31 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_B_DQS#3 DDR_A_D63 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
<18> DDR_B_D[16..31] AK40 SA_DQ47 SA_DQSN7 <18> DDR_B_D[48..63] AR21 SB_DQ47 SB_DQSN7
DDR_B_D16 DDR_A_DQS[0..1] <17> DDR_B_D48 DDR_A_DQS[4..5] <17>
DDR_B_D17 AK42 SA_DQ48 AJ62 DDR_A_DQS0 DDR_B_D49 AR22 SB_DQ48 AV30 DDR_A_DQS4
DDR_B_D18 AM43 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26 DDR_A_DQS5
SA_DQ50 SA_DQSP1 DDR_B_DQS[0..1] <18> SB_DQ50 SB_DQSP1 DDR_B_DQS[4..5] <18>
DDR_B_D19 AM45 AN58 DDR_B_DQS0 DDR_B_D51 AM22 AM28 DDR_B_DQS4
DDR_B_D20 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_B_DQS1 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS5
SA_DQ52 SA_DQSP3 DDR_A_DQS[2..3] <17> SB_DQ52 SB_DQSP3 DDR_A_DQS[6..7] <17>
DDR_B_D21 AK43 AW57 DDR_A_DQS2 DDR_B_D53 AP21 AV22 DDR_A_DQS6
DDR_B_D22 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS3 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_A_DQS7
SA_DQ54 SA_DQSP5 DDR_B_DQS[2..3] <18> SB_DQ54 SB_DQSP5 DDR_B_DQS[6..7] <18>
DDR_B_D23 AM42 AL42 DDR_B_DQS2 DDR_B_D55 AK22 AM21 DDR_B_DQS6
DDR_B_D24 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_B_DQS3 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_B_D25 AK46 SA_DQ56 SA_DQSP7 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
DDR_B_D26 AM49 SA_DQ57 AP49 DDR_B_D58 AK18 SB_DQ57
SA_DQ58 SM_VREF_CA +SM_VREF_CA SB_DQ58
DDR_B_D27 AK49 AR51 DDR_B_D59 AL18
SA_DQ59 SM_VREF_DQ0 +SM_VREF_DQ0 SB_DQ59
DDR_B_D28 AM48 AP51 DDR_B_D60 AK20
SA_DQ60 SM_VREF_DQ1 +SM_VREF_DQ1 SB_DQ60
DDR_B_D29 AK48 DDR_B_D61 AM20
DDR_B_D30 AM51 SA_DQ61 DDR_B_D62 AR18 SB_DQ61
DDR_B_D31 AK51 SA_DQ62 DDR_B_D63 AP18 SB_DQ62
SA_DQ63 SB_DQ63
B B
4 OF 19 Rev1p2
3 OF 19 Rev1p2
@
@
+1.35V +1.35V +1.35V

1
1
RC31 RC32 RC33
1.82K_0402_1% 1.82K_0402_1% 1.82K_0402_1%
+SM_VREF_CA_DIMM +SM_VREF_CA +SM_VREF_DQ1_DIMM2 +SM_VREF_DQ1 +SM_VREF_DQ0_DIMM1 +SM_VREF_DQ0
2
2
1 2 1 2 1 2
1 1
RC34 1 RC35 RC36
2.2_0402_1% 2.2_0402_1% CC11 2.2_0402_1% CC12
1
1
CC13 0.022U_0402_16V7K 0.022U_0402_16V7K
RC37 RC38 2 RC39 2
0.022U_0402_16V7K
1.82K_0402_1% 2 1.82K_0402_1% 1.82K_0402_1%
change 22nF change 22nF
1
1
change 22nF
1
RC41 RC42
2
2
RC40 24.9_0402_1%~D 24.9_0402_1%~D
24.9_0402_1%~D
2
2
2
A confirm by intel request PDG P141 A

MCP(3,4/19) DDR3
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
+RTCVCC
1
RTC Battery RC43
330K_0402_1%
2
+RTCBATT
D PCH_INTVRMEN D
JP1
2
2 1
+RTCVCC 2 1
1
+CHGRTC RC44
@
1K_0402_5% JUMP_43X39
RC45
330K_0402_1% +3VS
W=20mils JP2
1
2
W=20mils 2 1 1 2 PCH_AZ_SDOUT
+CHGRTC 2 1 +3VLP
3
@ RC46 1K_0402_5%
DC1 JUMP_43X39
BAT54CW_SOT323-3
INTVRMEN - INTEGRATED SUS 1.05V VRM FLASH DESCRIPTOR SECURITY OVERRIDE
ENABLE LOW = DESABLED (DEFAULT)
For GCLK
1
+RTCVCC High - Enable Internal VRs HIGH = ENABLED

1 <19> PCH_RTCX1
PCH_RTCX1 Low - Enable External VRs
CC14
W=20mils 1U_0603_10V6K
2
CC15 XTAL@
1 2 PCH_RTCX1
15P_0402_50V8J
1
XTAL@ XTAL@
RC47
HASWELL_MCP_E
YC1 10M_0402_5% UC3E
2
32.768KHZ_12.5PF_Q13FC1350000
2
CC16 XTAL@
15P_0402_50V8J AW5
1 2 PCH_RTCX2 AY5 RTCX1
1 2 INTRUDER# AU6 RTCX2 J5
AV7 INTRUDER RTC SATA_RN0/PERN6_L3 H5 SATA_PRX_DTX_N0_C <32>
RC50 1M_0402_5% PCH_INTVRMEN
1 2 AV6 INTVRMEN SATA_RP0/PERP6_L3 B15 SATA_PRX_DTX_P0_C <32>
C +RTCVCC SRTCRST# SATA HDD C
SRTCRST SATA_TN0/PETN6_L3 SATA_PTX_DRX_N0_C <32>
RC48 1 2 20K_0402_5% PCH_RTCRST# AU7 A15
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0_C <32>
RC49 20K_0402_5% 2
J8
CC17 SATA_RN1/PERN6_L2 H8
SATA_RP1/PERP6_L2 A17
1U_0402_6.3V6K SATA_TN1/PETN6_L2
1 B17
SATA_TP1/PETP6_L2
1 2 PCH_AZ_BITCLK AW8 J6
1 2 PCH_AZ_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 PCH Rx side need use strap pin to update PCIE +/-
PCH_AZ_RST# AU8 B14
PCH_AZ_CODEC_SDIN0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15 +3VS
<22> PCH_AZ_CODEC_SDIN0 AU12 HDA_SDI0/I2S0_RXD AUDIO SATA SATA_TP2/PETP6_L1
@
CMOS1 SHORT PADS~D 1 2 PCH_AZ_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
<30> ME_EN HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
2
1 2 RC51 1K_0402_5% AW10 E5
CC18 1U_0402_6.3V6K AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 RC52
I2S1_SCLK SATA_TP3/PETP6_L0 10K_0402_5%
1
V1 EC_SMI#
CMOS place near DIMM SATA0GP/GPIO34 U1 PCH_GPIO35
EC_SMI# <30>
SATA1GP/GPIO35 V6 ODD_DETECT# +1.05VS_ASATA3PLL
SATA2GP/GPIO36 AC1 ODD_DETECT#
PCH_GPIO37
PCH_JTAG_RST# AU62 SATA3GP/GPIO37
<6> PCH_JTAG_RST# AE62 PCH_TRST A12 1 2 0_0603_1%
PCH_JTAG_TCK SATA_IREF RC53 @
<6> PCH_JTAG_TCK AD61 PCH_TCK SATA_IREF L11
PCH_JTAG_TDI
<6> PCH_JTAG_TDI AE61 PCH_TDI RSVD K10
PCH_JTAG_TDO
<6> PCH_JTAG_TDO AD62 PCH_TDO JTAG RSVD C12 1 2 3.01K_0402_1%
PCH_JTAG_TMS SATA_RCOMP RC54
<6> PCH_JTAG_TMS AL11 PCH_TMS SATA_RCOMP U3 SATA_ACT# SATA Impedance Compensation
AC4 RSVD SATALED SATA_ACT# <25>
within 500 mils
RTC discharge by EC <6> PCH_JTAG_JTAGX
PCH_JTAG_JTAGX AE63
AV2
RSVD
JTAGX CAD note:
SRTCRST# RSVD Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
PCH_RTCRST# reference FFRD sch 0.5
@ 5 OF 19 Rev1p2
6
B DMN66D0LDW-7_SOT363-6 B
2
D
G
QC1B @
S
1
@
3
+3VS
<30> RTC_DIS
5 G
D
S
DMN66D0LDW-7_SOT363-6
QC1A HDA for Codec
4
1
RC55
CMOS_CLR1 CMOS setting ODD_DETECT# 1 8
@ PCH_GPIO35 2 7
100K_0402_5% Shunt Clear CMOS EMI@ R2 1 2 33_0402_5% PCH_AZ_SDOUT PCH_GPIO37 3 6
<22> PCH_AZ_CODEC_SDOUT 4 5
Open Keep CMOS
2
EMI@ R3 1 2 33_0402_5% PCH_AZ_SYNC

<22> PCH_AZ_CODEC_SYNC
RP4
EMI@ R4 1 2 33_0402_5% PCH_AZ_RST# 10K_8P4R_5%
ME_CLR1 TPM setting <22> PCH_AZ_CODEC_RST#
EMI@ R5 1 2 33_0402_5% PCH_AZ_BITCLK
Shunt Clear ME RTC Registers <22> PCH_AZ_CODEC_BITCLK
Open Keep ME RTC Registers

1 @EMI@
CC19
27P_0402_50V8J
+1.05VS_PCH
2
@
RC56
2 1 PCH_JTAG_JTAGX
1K_0402_1%
EMI depop location
@ 2 1 PCH_JTAG_TCK
RC57 51_0402_1%
A A
+1.05VS_PCH
1 8 PCH_JTAG_TDI
2 7 PCH_JTAG_TDO
3 6 PCH_JTAG_TMS
4 5 Security Classification Compal Secret Data Compal Electronics, Inc.
RP5
51_8P4R_5%
MCP(5/19) RTC,SATA,HDA,JTAG
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
+3VALW_PCH
MEM Bus : DDR/XDP/WLAN/TP
D +3VS D
1
R6 R7 +3VS
10K_0402_5% 10K_0402_5%
1
HASWELL_MCP_E
UC3G R8 R9
2
10K_0402_5% 10K_0402_5%
LPC_LAD0 AU14 AN2 PCH_SMB_ALERT#
<30> LPC_LAD0 LAD0 SMBALERT/GPIO11
2
LPC_LAD1 AW12 AP2 MEM_SMBCLK
<30> LPC_LAD1
2
LPC_LAD2 AY12 LAD1 LPC SMBCLK AH1 MEM_SMBDATA
G
<30> LPC_LAD2 AW11 LAD2 SMBDATA AL2 6 1
LPC_LAD3 MEM_SMBCLK
<30> LPC_LAD3 LAD3 SML0ALERT/GPIO60 DDR_XDP_WLAN_TP_SMBCLK <17,18,32,6>
S
LPC_LFRAME# AV12 SMBUS AN1 SML0CLK
<30> LPC_LFRAME# LFRAME SML0CLK AK1 SML0DATA QC1B
SML0DATA
5
AU4 PCH_HOT# DMN66D0LDW-7_SOT363-6
EMI EMI@ SML1ALERT/PCHHOT/GPIO73 AU3 SML1_SMBCLK
G
R2333 SML1CLK/GPIO75 AH3 SML1_SMBDATA MEM_SMBDATA 3 4
SML1DATA/GPIO74 DDR_XDP_WLAN_TP_SMBDAT <17,18,32,6>
S
PCH_SPI_CLK_R 1 1 2 15_0402_1% PCH_SPI_CLK AA3
PCH_SPI_CS0# Y7 SPI_CLK AF2 @ T97 QC1A
@EMI@ Y4 SPI_CS0 CL_CLK AD2 @ T98 DMN66D0LDW-7_SOT363-6
C2326 RP39 AC2 SPI_CS1 SPI C-LINK CL_DATA AF4 @ T99
68P_0402_50V8J 2 PCH_SPI_MOSI_1 1 8 PCH_SPI_MOSI AA2 SPI_CS2 CL_RST
PCH_SPI_MISO_1 2 7 PCH_SPI_MISO AA4 SPI_MOSI
PCH_SPI_WP1# 3 6 PCH_SPI_WP# Y6 SPI_MISO
PCH_SPI_HOLD1# 4 5 PCH_SPI_HOLD# AF1 SPI_IO2
SPI_IO3
15_8P4R_5%
+3VALW_PCH
R2334 1 2 1K_0402_1% 7 OF 19 Rev1p2

R2335 1 2 1K_0402_1%
@
SML1 Bus : EC/Sensors

C C
U2302
+3VALW_PCH
WINBOND
64M W25Q64FVSSIQ SOIC 8P +3VALW_PCH
+3VALW_PCH
2
SA000039A30 C2327 QH1B
0.1U_0402_10V7K
G
SPI ROM ( 8MByte ) 1 2
1
RP40
8
SML1_SMBCLK 1 6
EC_SMB_CK2 <30,33,35>
D
MEM_SMBCLK
5
U2302 MEM_SMBDATA 2 7 DMN66D0LDW-7_SOT363-6
PCH_SPI_CS0# 1 8 SML1_SMBCLK 3 6
G
PCH_SPI_MISO_1 2 CS# VCC 7 PCH_SPI_HOLD1# SML1_SMBDATA 4 5 SML1_SMBDATA 4 3
DO(IO1) HOLD#(IO3) EC_SMB_DA2 <30,33,35>
3 6
D
PCH_SPI_WP1# PCH_SPI_CLK_R
4 WP#(IO2) CLK 5 PCH_SPI_MOSI_1 2.2K_0804_8P4R_5% QH1A
GND DI(IO0) DMN66D0LDW-7_SOT363-6
64M EN25Q64-104HIP SOP 8P
RP49
SML0CLK 1 8
@
SML0DATA 2 7
3 6
4 5
For GCLK
1K_0804_8P4R_5%
XTAL24_IN
<19> XTAL24_IN
CC6
15P_0402_50V8J
2 1
B B
1M_0402_5%
XTAL@
3
4
HASWELL_MCP_E
RC12
UC1F XTAL@
YC2
24MHZ_12PF_X3G024000DC1H
1
2
XTAL@ CC7
C43 A25 XTAL24_IN 15P_0402_50V8J
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT 2 1
U2 CLKOUT_PCIE_P0 XTAL24_OUT
PCIECLKRQ0/GPIO18 K21 RC13 XTAL@
B41 RSVD M21 3.01K_0402_1%
A41 CLKOUT_PCIE_N1 RSVD C26 CLK_BIASREF 1 2
CLKOUT_PCIE_P1 DIFFCLK_BIASREF +1.05VS_AXCK_LCPLL
Y5 RP41 10K_8P4R_5%
PCIECLKRQ1/GPIO19 C35 SWAP_1 SWAP_2 1 8
CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 SWAP_2 SWAP_1 2 7
<21> CLK_PCIE_LAN# B42 CLKOUT_PCIE_N2 TESTLOW_C34 AK8 3 6
10/100 LAN -------> CLK_PCIE_LAN
<21> CLK_PCIE_LAN AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 4 5
<21> LAN_CLKREQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
CLK_PCIE_WLAN# B38 AN15 CLKOUT_LPC0 2 1 EMI@
<26> CLK_PCIE_WLAN# C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLK_PCI_LPC <30>
WLAN(Mini Card)---> CLK_PCIE_WLAN R2336 22_0402_5%
<26> CLK_PCIE_WLAN N1 CLKOUT_PCIE_P3 CLKOUT_LPC_1
WLAN_CLKREQ#_R
PCIECLKRQ3/GPIO21 B35
A39 CLKOUT_ITPXDP_N A35 CLK_CPU_ITP# <6>
CLK_PEG_VGA#
<34> CLK_PEG_VGA# B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P CLK_CPU_ITP <6>
dGPU---> CLK_PEG_VGA
<34> CLK_PEG_VGA U5 CLKOUT_PCIE_P4
<35> PEG_CLKREQ# PCIECLKRQ4/GPIO22
B37
A37 CLKOUT_PCIE_N5
T2 CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
@ R2452
1 2 6 OF 19 Rev1p2
+3VS_WLAN_NGFF +3VS
0_0402_5%~D @
DII-DMN65D8LW-7~D RP42
A
1 8 A
1 3 WLAN_CLKREQ#_R 2 7
D
<26> WLAN_CLKREQ# 3 6
Q2409 4 5
G
2
+3VS 10K_8P4R_5%
1
R2453
100K_0402_5%~D
2
MCP(6,7/19) CLK,SMB,SPI,LPC
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
PCH_PLTRST#
1
CC33 ESD@
0.047U_0402_16V4Z +3VS
+3VALW_PCH 2
D @ CC11 D
1 2 ME_SUS_PWR_ACK Place CC33 1 2
RC27 10K_0402_5%
1 2 SUSACK# close to UC3.1 & UC3.2 0.1U_0402_10V7K
@ RC28 10K_0402_5%
1 2 SUS_STAT#/LPCPD#
5
@ RC29 10K_0402_5%
VCC
PCH_PLTRST# 1
IN1 4 PLT_RST#
+3V_DSW 2 OUT PLT_RST# <21,26,30,34,6>
GND
IN2
1
UC3
1 2 AC_PRESENT MC74VHC1G08DFT2G_SC70-5 R159
3
RC32 10K_0402_5% 100K_0402_5%
1 2 PCH_BATLOW#
RC31 8.2K_0402_5% PCH_DPWROK 1 2 PCH_RSMRST#_R
2
1 2 PCIE_WAKE#_R RC33 @ 0_0402_5%
RC34 1K_0402_5%
1 2 PCH_SLP_WLAN# ME_SUS_PWR_ACK_R 1 2 SUSACK#
RC39 10K_0402_5% RC35 @ 0_0402_5%
DSWODVREN - On Die DSW VR Enable

Note: SUSACK# and SUSWARN# can be tied together if
* H：Enable(DEFAULT)
+3VS
EC does not want to involve in the handshake mechanism
for the Deep Sleep state entry and exit
L ：Disable
1 2 CLKRUN# +RTCVCC DSWODVREN - ON DIE DSW VR ENABLE
CAN be NC ,if not support Deep Sx DPWROK: Tired toghter with RSMRST#
RC36 8.2K_0402_5% HIGH = ENABLED (DEFAULT)
UC1H HASWELL_MCP_E that do not support Deep Sx
R2337 1 2 330K_0402_5%
R2338 1 @ 2 330K_0402_5%
SYSTEM POWER MANAGEMENT LOW = DISABLED
SUSACK# RC37 1 @ 2 0_0402_1% SUSACK#_R AK2 AW7 DSWODVREN
<30> SUSACK# AC3 SUSACK DSWVRMEN AV5
SYS_RESET# PCH_DPWROK
SYS_PWROK SYS_PWROK 1 8<6> SYS_RESET#
SYS_PWROK_R AG2 SYS_RESET DPWROK AJ5 PCIE_WAKE#_R 1 2 PCIE_WAKE# PCH_DPWROK <30>
<30,6> SYS_PWROK 2 7 AY7 SYS_PWROK WAKE PCIE_WAKE# <21,30>
1 PCH_PWROK_R @
<30> PCH_PWROK 3 6 AB5 PCH_PWROK
C CC31 @ESD@ PM_APWROK_R RC97 C
4 5 PCH_PLTRST# AG7 APWROK V5 CLKRUN# 0_0402_5%
0.047U_0402_16V4Z PLTRST CLKRUN/GPIO32 AG4 SUS_STAT#/LPCPD#
2 RP50 SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK/GPIO62 AP5 SUSCLK <26>
0_8P4R_5% SIO_SLP_S5#
1 2 0_0402_1% AW6 SLP_S5/GPIO63 SIO_SLP_S5# <30>
Place CC31 RC41 @ PCH_RSMRST#_R
<30> EC_RSMRST# 1 2 0_0402_1% RSMRST T103 PAD~D@
RC42 @ ME_SUS_PWR_ACK_R AV4
on BOT <30> ME_SUS_PWR_ACK AL7 SUSWARN/SUSPWRDNACK/GPIO30 AJ6 T104 PAD~D @
PBTN_OUT# SIO_SLP_S4#
1 <30,6>
2 PBTN_OUT# AJ8 PWRBTN SLP_S4 AT4 SIO_SLP_S4# <30>
<30,35,44,45> ACIN AC_PRESENT SIO_SLP_S3#
AN4 ACPRESENT/GPIO31 SLP_S3 AL5 SIO_SLP_S3# <30>
DH1 RB751V-40_SOD323-2 PCH_BATLOW# @ T105
PCH_PWROK SIO_SLP_S0# AF3 BATLOW/GPIO72 SLP_A AP4
<30> SIO_SLP_S0# AM5 SLP_S0 SLP_SUS AJ7 SLP_SUS# <30>
1 PCH_SLP_WLAN# @ T107
CC34 @ESD@ SLP_WLAN/GPIO29 SLP_LAN
0.047U_0402_16V4Z PCH_BATLOW# Need pull high to VCCDSW3_3 @ T106

2
(If no deep Sx , connect to VCCSUS3_3) 8 OF 19 Rev1p2
Place CC34
close to RP50.2&RP50.3 @
+3VS
HASWELL_MCP_E 1 8
UC1I CPU_DPB_CTRLDAT
+3VS CPU_DPB_CTRLCLK 2 7
@ CPU_DPC_CTRLCLK 3 6
RC81 CPU_DPC_CTRLDAT 4 5
0_0402_1%
1 2 DGPU_PWROK EDP_BIA_PWM 2 1 EDP_BKLCTL B8 B9 CPU_DPB_CTRLCLK RP52
<31,6> EDP_BIA_PWM A9 EDP_BKLCTL DDPB_CTRLCLK C9 CPU_DPB_CTRLCLK <20>
RC73 10K_0402_5% PANEL_BKLEN CPU_DPB_CTRLDAT 2.2K_8P4R_5%
1 2 <30> PANEL_BKLEN C6 EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA D9 CPU_DPB_CTRLDAT <20>
@ PCH_TP_INT# ENVDD_PCH CPU_DPC_CTRLCLK
<31> ENVDD_PCH EDP_VDDEN DDPC_CTRLCLK D11
RC74 10K_0402_5% CPU_DPC_CTRLDAT
1 @ 2 EDP_BIA_PWM DDPC_CTRLDATA CPU_DPB_AUX# 1 8
B B
RC75 10K_0402_5% CPU_DPB_AUX 2 7
1 2 TS_RST# DGPU_PWROK U6 CPU_DPC_AUX 3 6
<30,52> DGPU_PWROK P4 PIRQA/GPIO77 C5 4 5
RC76 10K_0402_5% PXS_PWREN CPU_DPB_AUX# CPU_DPC_AUX#
1 2 <11,36,47,51,52> PXS_PWREN PIRQB/GPIO78 DDPB_AUXN
DGPU_HOLD_RST# DGPU_HOLD_RST# N4 DISPLAY B6 CPU_DPC_AUX#
<34> DGPU_HOLD_RST# N2 PIRQC/GPIO79 DDPC_AUXN B5
RC77 10K_0402_5% FFS_INT1 CPU_DPB_AUX RP51
1 2 <32> FFS_INT1 AD4 PIRQD/GPIO80 DDPB_AUXP A6
FFS_INT1 T117 @ CPU_DPC_AUX 100K_8P4R_5%
RC79 10K_0402_5% PME GPIO DDPC_AUXP
PCH_TP_INT# U7
1 2 ENVDD_PCH TS_RST# L1 GPIO55
<31> TS_RST# L3 GPIO52 C8
@ RC87 100K_0402_5% DPB_HPD
2 1 R5 GPIO54 DDPB_HPD A8 DPB_HPD <20>
CODEC_IRQ DPC_HPD
@ RC88 1K_0402_1% CODEC_IRQ L4 GPIO51 DDPC_HPD D6 CPU_EDP_HPD#
GPIO53 EDP_HPD
9 OF 19 Rev1p2 DPC_HPD 2 1
@ RC84
+3VS 100K_0402_5%
@
2
RC82
0_0402_1%
G
2 1 CPU_EDP_HPD# 2 1
1 3 EDP_CPU_HPD <31>
PCH_TP_INT#
<27> TP_INT#
RC89
D
100K_0402_5%
QC3
2N7002K_SOT23-3
1 2
RC367 0_0402_5%
A @ A

MCP(8,9/19) DDI,EDP,GPIO
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
D D
+1.05VS_PCH
+1.05VS_PCH
Close to R2346
1
CC28
1
100P_0402_50V8J
HASWELL_MCP_E
UC1J @ESD@
R2346 2
1K_0402_5%
ESD solution
2
PCH_AUDIO_EN P1 D60 H_THERMTRIP#
AU2 BMBUSY/GPIO76 THERMTRIP V4 KB_RST#
AM7 GPIO8 RCIN/GPIO82 T4 KB_RST# <30>
PCH_GPIO12 SERIRQ
@ T182 PAD~D AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 1 2 SERIRQ <30>
EC_LID_OUT# PCH_OPI_COMP
<30> EC_LID_OUT# Y1 GPIO15 MISC PCH_OPI_RCOMP AF20
ODD_DA# T3 GPIO16 RSVD AB21 RC101
BT_ON# AD5 GPIO17 RSVD 49.9_0402_1% +3VS +3VS
<26>
1 BT_ON#2 AN5 GPIO24
@ GPIO27
<30> WAKE_PCH# RC38 0_0402_1% GPIO27
HOST_ALERT1_R_N AD7 +3VS
GPIO28
1
KB_DET# AN3
<27> KB_DET# GPIO26 R6 PCH_GPIO83 JET@ UMA@
AG6 GSPI0_CS/GPIO83 L6 PAD~D T177 @ 2 1
PCH_GPIO56 PCH_GPIO84 RC112 RC100 SERIRQ
AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PAD~D T176 @
PCH_GPIO85 10K_0402_5% 10K_0402_5% 10K_0402_5% RC102
AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PAD~D T175 @ 2 1
+3VS SLATE_MODE_R BBS_BIT LCD_CBL_DET#
2
WL_OFF# AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 DGPU_PRSNT# 10K_0402_5% RC106
<26> WL_OFF# AK4 GPIO59 GSPI1_CS/GPIO87 L5 2 1
PCH_GPIO44 Project_ID CPPE#
2 1 DEVSLP0 PCH_GPIO47 AB6 GPIO44 GPIO GSPI1_CLK/GPIO88 N7 PCH_GPIO89 100K_0402_5% RC108
C @ T174 PAD~D GPIO47 GSPI1_MISO/GPIO89 PAD~D T178 @ C
1
RC11 10K_0402_5% PCH_GPIO48 U4 K2 PCH_GPIO90 CPUSB# 2 1
@ T124 PAD~D Y3 GPIO48 GSPI_MOSI/GPIO90 J1 PAD~D T179 @ TOPAZ@ DIS@
PCH_GPIO49 CPPE# 100K_0402_5% RC111
2 1 SIO_EXT_SCI# @ T125 PAD~D TS_INT# P3 GPIO49 UART0_RXD/GPIO91 K3 CPUSB# RC113 RC99 FFS_INT2 2 1
<31> TS_INT# Y2 GPIO50 UART0_TXD/GPIO92 J2
RC98 100K_0402_5% PCH_GPIO93 10K_0402_5% 10K_0402_5% 100K_0402_5% RC115
AT3 HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 G1 PAD~D T180 @
PCH_GPIO94 RP53
PAD~D T181 @
2
2 1 PCH_GPIO56 PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 I2C1_SDA 1 8
@ T126 PAD~D AM4 GPIO14 UART1_RXD/GPIO0 G2 2 7
RC9 100K_0402_5% PCH_GPIO25 FFS_INT2 I2C1_SCL
@ T127 PAD~D AG5 GPIO25 UART1_TXD/GPIO1 J3 FFS_INT2 <32> 3 6
LCD_CBL_DET# I2C0_SDA
PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 I2C0_SCL 4 5
GPIO46 UART1_CTS/GPIO3 F2 I2C0_SDA
+3V_DSW PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 I2C0_SCL 2.2K_0804_8P4R_5%
EC_SCI# AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C1_SDA RC363 2 @ 1 0_0402_5%
<30> EC_SCI# P2 GPIO10 I2C1_SDA/GPIO6 F1 2 1 0_0402_5% I2C1_SDA_PNL <31>
DEVSLP0 I2C1_SCL RC364 @
<32> DEVSLP0 C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 I2C1_SCL_PNL <31>
2 1 GPIO27 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 RC365 2 @ 1 0_0402_1%
N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 2 1 0_0402_1% I2C1_SDA_TP <27>
RC105 10K_0402_5% SIO_EXT_SCI# PCH_GPIO66 RC366 @
V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 I2C1_SCL_TP <27> 2 1 RC109
HDA_SPKR KB_RST# 10K_0402_5%
<22> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3
SDIO_D2/GPIO68 E2 TS_INT# 10K_0402_5% 2 1 RC114
SDIO_D3/GPIO69
+3VALW_PCH 10 OF 19 Rev1p2
@
2 1 KB_DET#
RC103 10K_0402_5%
2 1 PCH_GPIO44
RC104 10K_0402_5%
2 1 SLATE_MODE_R
RC110 10K_0402_5%
2 1 PCH_AUDIO_EN
RC116 10K_0402_5% +3VS +3VS
1
@
@ RC119
RC118 10K_0402_5%
1K_0402_5% +3VALW_PCH +3VS
B B
2
1
PCH_GPIO66 BBS_BIT
@ @
1
RC120 RC121
1
@ 1K_0402_5% 1K_0402_5%
RC122
2
1K_0402_5% RC123
1K_0402_5% HOST_ALERT1_R_N HDA_SPKR
2
+3VS
2
RP54 GPIO66 GPIO86 GPIO15 GPIO81

8 1 ODD_DA#
7 2 BT_ON# TOP-BLOCK SWAP OVERRIDE BOOT BIOS STRAP BIT BBS TLS CONFIDENTIALITY NO REBOOT STRAP
6 3 WL_OFF#
5 4 PXS_PWREN HIGH depop RC288 (DEFAULT) HIGH LPC HIGH HIGH
PXS_PWREN <10,36,47,51,52>
8.2K_8P4R_5% LOW pop RC288 LOW(DEFAULT) SPI LOW(DEFAULT) LOW(DEFAULT)
GPIO15 NOT Used
+3VALW_PCH +3VALW_PCH
1
RC124 RC125
10K_0402_5% 10K_0402_5%
2
PCH_GPIO46 PCH_GPIO9
A A

MCP(10/19) GPIO,LPIO,MISC
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
D D
HASWELL_MCP_E
UC1K
PEG_CRX_GTX_N0 F10 AN8 USB20_JUSB1_N0

<34> PEG_CRX_GTX_N0 E10 PERN5_L0 USB2N0 AM8 USB20_JUSB1_N0 <24>
PEG_CRX_GTX_P0 USB20_JUSB1_P0 USB Conn JUSB1
<34> PEG_CRX_GTX_P0 PERP5_L0 USB2P0 USB20_JUSB1_P0 <24>
PEG_CTX_GRX_N0 DIS@ CC18 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_N0 C23 AR7 USB20_JUSB2_N1
<34> PEG_CTX_GRX_N0 PETN5_L0 USB2N1 USB20_JUSB2_N1 <24>
PEG_CTX_GRX_P0 DIS@ CC19 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_P0 C22 AT7 USB20_JUSB2_P1 USB Conn JUSB2
<34> PEG_CTX_GRX_P0 PETP5_L0 USB2P1 USB20_JUSB2_P1 <24>
PEG_CRX_GTX_N1 F8 AR8 USB20_JUSB3_N2
<34> PEG_CRX_GTX_N1 E8 PERN5_L1 USB2N2 AP8 USB20_JUSB3_N2 <25>
PEG_CRX_GTX_P1 USB20_JUSB3_P2 USB Conn JUSB3
<34> PEG_CRX_GTX_P1 PERP5_L1 USB2P2 USB20_JUSB3_P2 <25>
PEG_CTX_GRX_N1 DIS@ CC20 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_N1 B23 AR10
<34> PEG_CTX_GRX_N1 PETN5_L1 USB2N3
PEG_CTX_GRX_P1 DIS@ CC21 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_P1 A23 AT10
<34> PEG_CTX_GRX_P1 PETP5_L1 USB2P3
PEG_CRX_GTX_N2 H10 AM15 USB20_MINI1_N4
<34> PEG_CRX_GTX_N2 G10 PERN5_L2 USB2N4 AL15 USB20_MINI1_N4 <26>
PEG_CRX_GTX_P2 USB20_MINI1_P4 Mini Card (WLAN)
<34> PEG_CRX_GTX_P2 PERP5_L2 USB2P4 USB20_MINI1_P4 <26>
PEG_CTX_GRX_N2 DIS@ CC22 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_N2 B21 AM13 USB20_TOUCH_N5
<34> PEG_CTX_GRX_N2 PETN5_L2 USB2N5 USB20_TOUCH_N5 <31>
PEG_CTX_GRX_P2 DIS@ CC23 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_P2 C21 AN13 USB20_TOUCH_P5 Touch screen panel
<34> PEG_CTX_GRX_P2 PETP5_L2 USB2P5 USB20_TOUCH_P5 <31>
PEG_CRX_GTX_N3 E6 AP11 USB20_CR_N6
<34> PEG_CRX_GTX_N3 F6 PERN5_L3 USB2N6 AN11 USB20_CR_N6 <25>
PEG_CRX_GTX_P3 USB20_CR_P6 Card Reader
<34> PEG_CRX_GTX_P3 PERP5_L3 USB2P6 USB20_CR_P6 <25>
PEG_CTX_GRX_N3 DIS@ CC24 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_N3 B22 AR13 USB20_CAM_N7
<34> PEG_CTX_GRX_N3 PETN5_L3 USB2N7 USB20_CAM_N7 <31>
PEG_CTX_GRX_P3 DIS@ CC25 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_P3 A21 AP13 USB20_CAM_P7 Camera
<34> PEG_CTX_GRX_P3 PETP5_L3 USB2P7 USB20_CAM_P7 <31>
C PCIE_PRX_LANTX_N3 G11 C
<21> PCIE_PRX_LANTX_N3 F11 PERN3 G20
PCIE_PRX_LANTX_P3 USB3RN1_JUSB1
<21> PCIE_PRX_LANTX_P3 PERP3 USB3RN1 H20 USB3RN1_JUSB1 <24>
10/100 LAN USB3RP1_JUSB1
USB3RP1 USB3RP1_JUSB1 <24>
PCIE_PTX_LANRX_N3 CC32 1 2 0.1U_0402_10V7K PCIE_PTX_LANRX_N3_C C29 USB Conn JUSB1
<21> PCIE_PTX_LANRX_N3 PETN3
PCIE_PTX_LANRX_P3 CC40 1 2 0.1U_0402_10V7K PCIE_PTX_LANRX_P3_C B30 PCIe USB C33 USB3TN1_JUSB1
<21> PCIE_PTX_LANRX_P3 PETP3 USB3TN1 B34 USB3TN1_JUSB1 <24>
USB3TP1_JUSB1
F13 USB3TP1 USB3TP1_JUSB1 <24>
PCIE_PRX_WLANTX_N4
<26> PCIE_PRX_WLANTX_N4 G13 PERN4 E18
PCIE_PRX_WLANTX_P4 USB3RN2_JUSB2
<26> PCIE_PRX_WLANTX_P4 PERP4 USB3RN2 F18 USB3RN2_JUSB2 <24>
NGFF WLAN USB3RP2_JUSB2
USB3RP2 USB3RP2_JUSB2 <24>
PCIE_PTX_WLANRX_N4 CC36 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_N4_C B29 USB Conn JUSB2
<26> PCIE_PTX_WLANRX_N4 PETN4
PCIE_PTX_WLANRX_P4 CC41 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_P4_C A29 B33 USB3TN2_JUSB2
<26> PCIE_PTX_WLANRX_P4 PETP4 USB3TN2 A33 USB3TN2_JUSB2 <24>
USB3TP2_JUSB2
G17 USB3TP2 USB3TP2_JUSB2 <24>
F17 PERN1/USB3RN3
PERP1/USB3RP3
C30
C31 PETN1/USB3TN3 AJ10 USBRBIAS
PETP1/USB3TP3 USBRBIAS AJ11
F15 USBRBIAS AN10 PAD~D T118 @
PERN2/USB3RN4 RSVD
1
G15 AM10 PAD~D T119 @
PERP2/USB3RP4 RSVD RC90
B31 22.6_0402_1%~D
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0#
USB_OC0# <24>
2
OC0/GPIO40 AT1 USB_OC1#
OC1/GPIO41 AH2 USB_OC1# <25>
USB_OC2#
RC91 @ T120PAD~D E15 OC2/GPIO42 AV3 USB_OC3#
3.01K_0402_1% @ T121PAD~D E13 RSVD OC3/GPIO43
1 2 PCH_PCIE_RCOMP A27 RSVD
+1.05VS_AUSB3PLL PCIE_RCOMP
B27 CAD NOTE:
PCIE_IREF
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
11 OF 19 Rev1p2 Recommended minimum spacing to other signal traces is 15 mils.
B B
+3VALW_PCH
USB_OC0# 1 8
USB_OC1# 2 7
USB_OC2# 3 6
USB_OC3# 4 5
RP55
10K_8P4R_5%
A A

MCP(11/19) PCIE,USB
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
VCCST_PG_EC
+CPU_CORE +1.35V
1
C79 ESD@ C40
1 2
220P_0402_50V8J +CPU_CORE
2 22U_0603_6.3V6M UC1L HASWELL_MCP_E
D D
+1.05VS_PCH @ESD@
Place C79 L59 C36
+1.35V J58 RSVD VCC C40
between R286 and UC1 ESD solution RSVD VCC
1
C44
R286 AH26 VCC C48
AJ31 VDDQ VCC C52
10K_0402_5% VDDQ VCC
AJ33 C56
AJ37 VDDQ VCC E23
2
AN33 VDDQ VCC E25
VCCST_PG_EC AP43 VDDQ VCC E27
<30> VCCST_PG_EC VDDQ VCC
AR48 E29
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
Define EC OD pin, need double confirm. +VCCIO_OUT AY44 VDDQ VCC E35
+CPU_CORE AY50 VDDQ VCC E37
VDDQ VCC E39
VCC
2
F59 E41
N58 VCC VCC E43
AC58 RSVD VCC E45
R245 @ RSVD VCC E47
0_0603_5% VCCSENSE E63 VCC E49
1
T38 @ AB23 VCC_SENSE VCC E51
VR_ON +VCCIO_OUT_R A59 RSVD VCC E53
E20 VCCIO_OUT VCC E55
1 +VCCIOA_OUT VCCIOA_OUT VCC
C80 ESD@ AD23 E57
AA23 RSVD 12 OF 19 VCC F24
0.1U_0402_10V7K AE59 RSVD VCC F28
SVID ALERT +1.05VS_PCH
2 RSVD VCC
VCC
F32
H_CPU_SVIDALRT# L62 F36
0_0402_1% 1 @ 2 R248 H_CPU_SVIDCLK N63 VIDALERT VCC F40
Place C80 <50> VR_SVID_CLK L63 VIDSCLK VCC F44
H_CPU_SVIDDATA
close to R250.1 VIDSOUT VCC
1
Place the PU VCCST_PG_EC B59 HSW ULT POWER F48

R252 0_0402_1% 1 @ 2 R250 VR12.5_VR_ON_R F60 VCCST_PWRGD VCC F52
75_0402_5%
resistors close to CPU <30,50> VR_ON
0_0402_1% 1 @ 2 R251 VR_READY_R C59 VR_EN VCC F56
<50> H_VR_READY VR_READY VCC G23
R254 D63 VCC G25
2
43_0402_1% CPU_PWR_DEBUG# H59 VSS VCC G27

C <6> CPU_PWR_DEBUG# PWR_DEBUG VCC C
2 1 H_CPU_SVIDALRT# P62 G29
<50> VR_SVID_ALRT# P60 VSS VCC G31
T39 @
T40 @ P61 RSVD_TP VCC G33
T41 @ N59 RSVD_TP VCC G35
T42 @ N61 RSVD_TP VCC G37
H_CPU_SVIDCLK T43 @ T59 RSVD_TP VCC G39
RF T44
T45
@
@
AD60
AD59
RSVD
RSVD
VCC
VCC
G41
G43
1 RSVD VCC
+1.05VS_PCH RF@ T46 @ AA59 G45
SVID DATA C5212 T47 @ AE60 RSVD
RSVD
VCC
VCC
G47
Place the PU 68P_0402_50V8J T48 @ AC59 G49
2 T49 @ AG58 RSVD VCC G51
SVID_DAT need to pull-up double side resistors close to CPU RSVD VCC
1
+1.05VS_PCH T50 @ U59 G53

( PWR_VR & CPU ) R256 T51 @ V59 RSVD VCC G55
130_0402_1% RSVD VCC G57
@ AC22 VCC H23
R257 +CPU_CORE AE22 VCCST VCC J23
2
0_0402_1% AE23 VCCST VCC K23

2 1 H_CPU_SVIDDATA VCCST VCC K57
<50> VR_SVID_DAT AB57 VCC L22
AD57 VCC VCC M23
AG57 VCC VCC M57
+1.05VS_PCH C24 VCC VCC P57
C28 VCC VCC U57
C32 VCC VCC W57
VCC VCC
2 @ Rev1p2
R253 R253
150_0402_1% @
INTEL Check list , XDP use only
+1.35V
1
CPU_PWR_DEBUG#
+CPU_CORE VDDQ DECOUPLING
2
@
B R255 B
1
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
10K_0402_5%
C35
C36
C37
C38
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
R1
1
C39
C41
C72
C42
C45
C74
100_0402_1%
2
2 2 2 2 2 2 2 2 2 2
VCCSENSE
CAD Note: PU resistor on HW side
<50> VCCSENSE
VSSSENSE CAD Note: PD resistor on HW side

<15,50> VSSSENSE +1.35V : 470UF/2V/7343 *2 (PWR)
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
1
R2
100_0402_1%
2
A A

MCP(12/19) Power
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
+1.05VS_PCH
+1.05VS_PCH +CPU_CORE
C46
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
1 2
D 1 1 22U_0603_6.3V6M D
@ESD@
CD63
CD65
@ESD@
@ESD@
+ + C47
1 2
2 2 22U_0603_6.3V6M
Close to N8
@ESD@
+1.05VS_PCH C57 @1 2 1U_0402_6.3V6K
ESD solution
+RTCVCC
+1.05VS_PCH +1.05VS_AUSB3PLL
L11 2 C58 1 2 1U_0402_6.3V6K

C59 1 2 100U_1206_6.3V6M
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
2.2UH_LQM2MPN2R2NG0L_30% 1 1 1
UC1M HASWELL_MCP_E
C54
C55
C56
+1.05VS_ASATA3PLL K9
+1.05VS_PCH VCCHSIO 2 2 2
L10 0_0603_1% 2 @ 1 R264 +3VALW_PCH
M9 VCCHSIO
L21 2 C63 1 2 1U_0402_6.3V6K N8 VCCHSIO mPHY AH11 C51 1 2 1U_0402_6.3V6K
+1.05VS_PCH VCC1_05 VCCSUS3_3
C65 1 2 100U_1206_6.3V6M P9 RTC AG10 +RTCVCC
2.2UH_LQM2MPN2R2NG0L_30% B18 VCC1_05 VCCRTC AE7
+1.05VS_AUSB3PLL VCCUSB3PLL DCPRTC
B11 +VCCRTCEXT C52 1 2 0.1U_0402_10V7K
+1.05VS_APLLOPI +1.05VS_ASATA3PLL VCCSATA3PLL
R267 +3VALW_PCH
0_0805_1%
1 @ 2 Y20 SPI Y8 @ C68 1 2 0.1U_0402_10V7K
C69 1 2 1U_0402_6.3V6K AA21 RSVD OPI VCCSPI
+1.05VS_APLLOPI VCCAPLL
L31 @ 2 C70 @1 2 100U_1206_6.3V6M W21
2.2UH_LQM2MPN2R2NG0L_30% VCCAPLL AG14 +1.05VS_PCH +3VS
VCCASW +1.05VS_PCH
AG13 C44
+1.05VS_AXCK_DCB VCCASW 1 2
+1.05VS_PCH
+1.05VS_PCH 0_0402_5% 2 @ 1 RC142 J13 USB3
DCPSUS3 J11 C60 1 2 10U_0603_6.3V6M 22U_0603_6.3V6M
C83 1 2 1U_0402_6.3V6K C92 1 @2 1U_0402_6.3V6K VCC1_05 H11 C61 1 2 1U_0402_6.3V6K @ESD@
L4 1 2 C84 1 2 100U_1206_6.3V6M AH14 AXALIA/HDA VCC1_05 H15 C62 1 2 1U_0402_6.3V6K
+VCCHDA VCCHDA VCC1_05
2.2UH_LQM2MPN2R2NG0L_30% AE8 C64
C VCC1_05 AF22
+PCH_VCCDSW 1U_0402_6.3V6K ESD solution C
0_0402_5% 2 @ 1 RC143 AH13 VRM/USB2/AZALIA VCC1_05 AG19 1 2

+1.05VS_AXCK_LCPLL +1.05VS_PCH DCPSUS2 DCPSUSBYP
CORE AG20
C91 1 @2 1U_0402_6.3V6K DCPSUSBYP AE9
VCCASW +1.05VS_PCH
C85 1 2 1U_0402_6.3V6K AF9 @ C66 1 2 22U_0603_6.3V6M
L5 1 2 C86 1 2 100U_1206_6.3V6M AC9 VCCASW AG8 C67 1 2 1U_0402_6.3V6K
+3VALW_PCH VCCSUS3_3 VCCASW +1.05VS_PCH +1.35V
2.2UH_LQM2MPN2R2NG0L_30% AA9 AD10
AH10 VCCSUS3_3 DCPSUS1 AD8 RC137 1 @ 2 0_0402_5% +1.05VS_PCH C43
+3V_DSW VCCDSW3_3 DCPSUS1
V8 GPIO/LCC C93 1 2 1U_0402_6.3V6K 1 2
+3VS VCC3_3
W9 @
VCC3_3 J15 22U_0603_6.3V6M
VCCTS1_5 +1.5VS
THERMAL SENSOR K14 ESD@
VCC3_3 +3VS
K16 C71 1 2 0.1U_0402_10V7K
+1.5VS +3VS +3VALW_PCH +VCCHDA VCC3_3
ESD solution
RC127 1 2 0_0402_5% +1.05VS_AXCK_DCB
J18
K19 VCCCLK SDIO/PLSS U8
VCCCLK VCCSDIO +3VS
RC128 1 @ 2 0_0402_5% A20 T9 C73 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL VCCACLKPLL VCCSDIO
J17
+1.05VS_PCH VCCCLK +PCH_VCCDSW +3V_DSW
RC129 1 @ 2 0_0402_5% R21
+1.05VS_PCH VCCCLK
T21 LPT LP POWER
K18 VCCCLK SUS OSCILLATOR AB8 1 2 0_0402_5% C5215
RC136 @ +1.05VS_PCH Reserve for inrush
C77 1 2 0.1U_0402_10V7K M20 RSVD DCPSUS4 C90 @1 2 1U_0402_6.3V6K 1 2
+VCCHDA RSVD
V21 CC37 @1 2 47U_0603_2.5V7 current issue
AE20 RSVD AC20 CC38 @1 2 47U_0603_2.5V7
Reserve for HDA issue, C77 close to AH14 +3VALW_PCH
AE21 VCCSUS3_3 RSVD AG16 0.47U_0402_6.3V6K
VCCSUS3_3 USB2 VCC1_05 +1.05VS_PCH @
AG17
VCC1_05 C76 1 2 1U_0402_6.3V6K
13 OF 19 Rev1p2
C50 1 2 1U_0402_6.3V6K @
C53 1 2 1U_0402_6.3V6K Close to K9,M9
+1.05VS_PCH
B B
C81 1 2 1U_0402_6.3V6K Close to AH10
+3V_DSW
C78 1 2 22U_0603_6.3V6M Close to AC9/AA9/AE20/AE21

+3VALW_PCH
C82 1 2 22U_0603_6.3V6M Close to V8

+3VS
+1.05VS_PCH C87 1 2 1U_0402_6.3V6K Close to J17
C88 1 2 1U_0402_6.3V6K Close to R21

+1.05VS_PCH
C75 2 1 0.1U_0402_10V7K Close to AH14

+3VALW_PCH
A A

MCP(13/19) Power
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
D D
HASWELL_MCP_E HASWELL_MCP_E
UC1N UC1O UC1P HASWELL_MCP_E
H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
C VSS VSS VSS VSS VSS VSS C
AB7 AL13 AR33 AY16 D54 N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
AH24 VSS VSS AN23 AU33 VSS VSS C11 VSS VSS_SENSE AH16 VSSSENSE <13,50>
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
VSS VSS VSS VSS
1
AH30 AN32 AU53 C18
AH32 VSS VSS AN35 AU55 VSS VSS C20 X@
VSS VSS VSS VSS @
AH34 AN36 AU57 C25 RC163
AH36 VSS VSS AN39 AU59 VSS VSS C27 100_0402_1%
AH38 VSS VSS AN40 AV14 VSS VSS C38
2
AH44 VSS VSS AN45 AV24 VSS VSS D12
B VSS VSS VSS VSS B
AH51 AN48 AV33 D18
AH57 VSS VSS AN52 AV39 VSS VSS D23 CAD Note: RC163 SHOULD BE PLACED CLOSE TO CPU
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV49 VSS VSS D29
VSS VSS VSS 15 OF 19 Rev1p2 VSS
@
14 OF 19 Rev1p2
A A

MCP(14,15,16/19) VSS
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
D D
HASWELL_MCP_E HASWELL_MCP_E
UC1Q UC1R
AY2 A3 N23 @
DC_TEST_AY2_AW2 DC_TEST_A3_B3 RSVD_N23 PAD~D T129
AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 RSVD R23 @
DC_TEST_AY3_AW3 DC_TEST_A4 PAD~D T168 @ RSVD_R23 PAD~D T130
AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 RSVD T23 @
@ T166PAD~D DC_TEST_AY60 @ RSVD_T23 PAD~D T131
DAISY_CHAIN_NCTF_AY60 T128 PAD~D RSVD_AT2 AT2 RSVD @
DC_TEST_AY61_AW61 AY61 A60 DC_TEST_A60 PAD~D T169 @ @ RSVD U10 RSVD_U10 PAD~D T133
DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 T132 PAD~D RSVD_AU44 AU44 RSVD
DC_TEST_AY62_AW62 AY62 A61 DC_TEST_A61_B61 @ RSVD
DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 T134 PAD~D RSVD_AV44 AV44
@ T167PAD~D TP_DC_TEST_B2 B2 A62 DC_TEST_A62 PAD~D T170 @ @ RSVD
DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 T135 PAD~D RSVD_D15 D15 @
DC_TEST_A3_B3 B3 AV1 DC_TEST_AV1 PAD~D T171 @ RSVD AL1 RSVD_AL1 PAD~D T136
B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 RSVD AM11 @
DC_TEST_A61_B61 DC_TEST_AW1 PAD~D T172 @ RSVD_AM11 PAD~D T137
B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 RSVD AP7 @
DC_TEST_AY2_AW2 @ RSVD_AP7 PAD~D T139
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 T138 PAD~D RSVD_F22 F22 RSVD @
DC_TEST_B62_B63 B63 AW3 DC_TEST_AY3_AW3 @ RSVD AU10 RSVD_AU10 PAD~D T141
DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 T140 PAD~D RSVD_H22 H22 RSVD @
C1 AW61 DC_TEST_AY61_AW61 @ RSVD AU15 RSVD_AU15 PAD~D T142
DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 T143 PAD~D RSVD_J21 J21 RSVD @
DC_TEST_C1_C2 C2 AW62 DC_TEST_AY62_AW62 RSVD AW14 RSVD_AW14 PAD~D T144
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 RSVD AY14 @
DC_TEST_AW63 PAD~D T173 @ RSVD_AY14 PAD~D T145
DAISY_CHAIN_NCTF_AW63
17 OF 19 Rev1p2 RSVD
@ 18 OF 19 Rev1p2
C C
UC1S HASWELL_MCP_E
CFG0 AC60 AV63 PAD~D T146 @

CFG STRAPS for CPU
<6> CFG0 AC62 CFG0 RSVD_TP AU63
CFG1 PAD~D T147 @
<6> CFG1 AC63 CFG1 RSVD_TP
CFG2 CFG4
<6> CFG2 AA63 CFG2
CFG3
<6> CFG3 AA60 CFG3 C63
CFG4 PAD~D T148 @
<6> CFG4 CFG4 RSVD_TP
1
CFG5 Y62 C62 PAD~D T149 @
<6> CFG5 Y61 CFG5 RSVD_TP B43
CFG6 PAD~D T150 @ RC138
<6> CFG6 Y60 CFG6 RSVD
CFG7 1K_0402_1%
<6> CFG7 V62 CFG7 A51
CFG8 PAD~D T151 @
<6> CFG8 V61 CFG8 RSVD_TP B51
CFG9 PAD~D T152 @
<6> CFG9
2
CFG10 V60 CFG9 RSVD_TP
<6> CFG10 U60 CFG10 L60
CFG11 PAD~D T153 @
<6> CFG11 T63 CFG11 RESERVED RSVD_TP
CFG12
<6> CFG12 T62 CFG12 N60
CFG13 PAD~D T154 @
<6> CFG13 T61 CFG13 RSVD
B CFG14 B
<6> CFG14 T60 CFG14 W23
CFG15 PAD~D T155 @
<6> CFG15 CFG15 RSVD Y22 PAD~D T156 @ Display Port Presence Strap
CFG16 AA62 RSVD AY15 PROC_OPI_RCOMP
<6> CFG16 U63 CFG16 PROC_OPI_RCOMP
CFG18
<6> CFG18
CFG17 AA61 CFG18 AV62 PAD~D T157 @ 1: Disabled; No Physical Display Port
<6> CFG17 U62 CFG17 RSVD D58
CFG19 PAD~D T158 @
<6> CFG19 CFG19 RSVD CFG4 attached to Embedded Display Port
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21 0: Enabled; An external Display Port device is
@ T159PAD~D A5 VSS
RSVD P20 PAD~D T160 @ connected to the Embedded Display Port
@ T161PAD~D E1 RSVD R20 PAD~D T162 @
@ T163PAD~D D1 RSVD RSVD
@ T164PAD~D J20 RSVD
@ T165PAD~D H18 RSVD
TDI_IREF B12 RSVD
TD_IREF
19 OF 19 Rev1p2
2 1 CFG_RCOMP
RC132 49.9_0402_1%
1 2 TDI_IREF PROC_OPI_RCOMP 1 2
RC133 8.2K_0402_1% 49.9_0402_1% RC134
A A

MCP(17,18,19/19) CFG,RSVD
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
+DIMM1_VREF_DQ
H=4mm
+1.35V +1.35V
1 2 1
JDIMM1
2
2-3A to 1 DIMMs/channel
+SM_VREF_DQ0_DIMM1 VREF_DQ VSS
3 4 DDR_A_D4
VSS DQ4
2.2U_0402_6.3V6M
0.1U_0402_10V7K
D @ DDR_A_D0 5 6 DDR_A_D5 D
RD1 DDR_A_D1 7 DQ0 DQ5 8 +1.35V
0_0402_1% 9 DQ1 VSS 10 DDR_A_DQS#0
Populate RD1, De-Populate RD7 for Intel DDR3 1 1 VSS DQS0#
CD1
CD2
11 12 DDR_A_DQS0
VREFDQ multiple methods M1 13 DM0 DQS0 14
VSS VSS
1
Populate RD7, De-Populate RD1 for Intel DDR3 DDR_A_D2 15 16 DDR_A_D6
2 2 DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7 RD3
VREFDQ multiple methods M3 19 DQ3 DQ7 20 470_0402_5%
DDR_A_D8 21 VSS VSS 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
2
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS VSS 28 1 2
29 DQS1# DM1 30 <18> DDR3_DRAMRST# DDR3_DRAMRST#_CPU <6>
DDR_A_DQS1 DDR3_DRAMRST#
31 DQS1 RESET# 32 @
DDR_A_D10 33 VSS VSS 34 DDR_A_D14 @ESD@ RD5
<7> DDR_A_DQS#[0..7] DQ10 DQ14 1
DDR_A_D11 35 36 DDR_A_D15 CD3 0_0402_1%
37 DQ11 DQ15 38
<7> DDR_A_D[0..63]
All VREF traces should VSS VSS
0.1U_0402_10V7K
have 10 mil trace width DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 2
<7> DDR_A_DQS[0..7] 43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS VSS 46
<7> DDR_A_MA[0..15] 47 DQS2# DM2 48
DDR_A_DQS2
49 DQS2 VSS 50 DDR_A_D22
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
Layout Note: Note: DDR_A_D19 53 DQ18 DQ23 54 CAD NOTE
55 DQ19 VSS 56 DDR_A_D28
Place near JDIMM1 Check voltage tolerance of DDR_A_D24 57 VSS DQ28 58 DDR_A_D29 PLACE THE CAP NEAR TO
DDR_A_D25 59 DQ24 DQ29 60
DQ25 VSS DIMM RESET PIN
VREF_DQ at the DIMM socket 61
63 VSS DQS3#
62
64
DDR_A_DQS#3
DDR_A_DQS3
65 DM3 DQS3 66
+1.35V DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<7> DDR_CKE0_DIMMA 75 CKE0 CKE1 76 DDR_CKE1_DIMMA <7>
C 1 1 1 1 1 1 1 1 VDD VDD C
77 78 DDR_A_MA15
NC A15
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
DDR_A_BS2 79 80 DDR_A_MA14
<7> DDR_A_BS2 81 BA2 A14 82
2 2 2 2 2 2 2 2 DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88 M_ODT
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
A8 A6 1
DDR_A_MA5 91 92 DDR_A_MA4 CD64 ESD@
93 A5 A4 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2 0.1U_0402_10V7K
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0 2
99 A1 A0 100
+1.35V M_CLK_DDR0 101 VDD VDD 102 M_CLK_DDR1 Place CC31
<7>
<7>
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR#0 103
105
CK0
CK0#
CK1
CK1#
104
106
M_CLK_DDR#1
M_CLK_DDR1
M_CLK_DDR#1
<7>
<7> DDR3L SODIMM ODT GENERATION between QD2 and R2349
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <7> +5VALW +1.35V
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
DDR_A_BS0 109 110 DDR_A_RAS#

<7> DDR_A_BS0 111 BA0 RAS# 112 DDR_A_RAS# <7>
QD2
DDR_A_WE# 113 VDD VDD 114 DDR_CS0_DIMMA# BSS138-G_SOT23-3
1 <7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
1 1@ 1 1 1@ 1 1 1 DDR_A_CAS# 115 116 M_ODT0
<7> DDR_A_CAS# CAS# ODT0
1
CD16
CD17
CD12
CD18
CD19
CD20
CD13
CD14
CD15
+ 117 118 1 3 M_ODT 1 2 M_ODT0
S
DDR_A_MA13 119 VDD VDD 120 M_ODT1 R2347 R2348 66.5_0402_1%
DDR_CS1_DIMMA# 121 A13 ODT1 122 +SM_VREF_CA_DIMM 220K_0402_5%~D 1 2 M_ODT1
2 2 2 2 2 2 2 2 2 <7> DDR_CS1_DIMMA# 123 S1# NC 124 R2349 66.5_0402_1%
G
2
125 VDD VDD 126 1 2 1 2
M_ODT2 <18>
2
TEST VREF_CA
2.2U_0402_6.3V6M
0.1U_0402_10V7K
127 128 R2350 66.5_0402_1%
DDR_A_D32 129 VSS VSS 130 DDR_A_D36 @ 1 2
131 DQ32 DQ36 132 M_ODT3 <18>
DDR_A_D33 DDR_A_D37 1 1 RD4 R2352 66.5_0402_1%
DQ33 DQ37
2
CD21
CD22
133 134 0_0402_1% @
DDR_A_DQS#4 135 VSS VSS 136 R2351
DDR_A_DQS4 137 DQS4# DM4 138 2M_0402_5% 0.675V_DDR_VTT_ON
DQS4 VSS 2 2 0.675V_DDR_VTT_ON <49>
139 140 DDR_A_D38
1
DDR_A_D35 143 DQ34 DQ39 144
Layout Note: DQ35 VSS
145 146 DDR_A_D44
Place near JDIMM1.203,204 DDR_A_D40 147 VSS DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
B DQ41 VSS B
151 152 DDR_A_DQS#5
153 VSS DQS5# 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS VSS 158 DDR_A_D46 +1.35V
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 @
161 DQ43 DQ47 162 CD23
+0.675VS DDR_A_D48 163 VSS VSS 164 DDR_A_D52 U2303 0.1U_0402_10V7K
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53 1 5 1 2
167 DQ49 DQ53 168 NC VCC
DDR_A_DQS#6 169 VSS VSS 170 2
171 DQS6# DM6 172 <6> DDR_PG_CTRL A 4
DDR_A_DQS6 0.675V_DDR_VTT_ON
DQS6 VSS Y
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
173 174 DDR_A_D54 3

DDR_A_D50 175 VSS DQ54 176 DDR_A_D55 GND
1 1 1 1 1 1 DQ50 DQ55
CD24
CD25
CD26
CD27
CD28
CD29
DDR_A_D51 177 178 74AUP1G07GW_TSSOP5

179 DQ51 VSS 180 DDR_A_D60
2 2 2 2 2 2 DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
RD61 2 10K_0402_5% 197 VSS VSS 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA DDR_XDP_WLAN_TP_SMBDAT <18,32,6,9>
1 2 201 202
SA1 SCL DDR_XDP_WLAN_TP_SMBCLK <18,32,6,9>
2.2U_0402_6.3V6M
RD7 10K_0402_5% 1 1 203 204

VTT VTT +0.675VS
0.1U_0402_10V7K
@ +0.675VS
CD30
CD31
205 206
207 GND1 GND2 208
2 2 BOSS1 BOSS2
BELLW_80001-1021
CONN@
A A
+3VS +1.35V
CD62
1 2
22U_0603_6.3V6M
ESD@
ESD solution
DDRIII DIMMA
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
+DIMM2_VREF_DQ +1.35V
H=4mm +1.35V
JDIMM2
2-3A to 1 DIMMs/channel
1 2 1 2
+SM_VREF_DQ1_DIMM2 VREF_DQ VSS1
3 4 DDR_B_D22
VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_10V7K
@ DDR_B_D23 5 6 DDR_B_D16
RD8 DDR_B_D17 7 DQ0 DQ5 8
0_0402_1% 9 DQ1 VSS3 10 DDR_B_DQS#2
1 1 VSS4 DQS#0
CD32
CD33
D
11 12 DDR_B_DQS2 D
13 DM0 DQS0 14
Populate RD4, De-Populate RD8 for Intel DDR3 DDR_B_D21 15 VSS5 VSS6 16 DDR_B_D19
VREFDQ multiple methods M1 2 2 DDR_B_D18 17 DQ2 DQ6 18 DDR_B_D20
19 DQ3 DQ7 20
Populate RD8, De-Populate RD4 for Intel DDR3 DDR_B_D3 21 VSS7 VSS8 22 DDR_B_D4
VREFDQ multiple methods M3 DDR_B_D2 23 DQ8 DQ12 24 DDR_B_D5
25 DQ9 DQ13 26
DDR_B_DQS#0 27 VSS9 VSS10 28
DDR_B_DQS0 29 DQS#1 DM1 30 DDR3_DRAMRST#
31 DQS1 RESET# 32 DDR3_DRAMRST# <17>
<7> DDR_B_DQS#[0..7] 33 VSS11 VSS12 34
DDR_B_D0 DDR_B_D6 1
All VREF traces should DDR_B_D1 35 DQ10 DQ14 36 DDR_B_D7
<7> DDR_B_D[0..63] 37 DQ11 DQ15 38
have 10 mil trace width @ESD@
DDR_B_D12 39 VSS13 VSS14 40 DDR_B_D13 CD34
<7> DDR_B_DQS[0..7] 41 DQ16 DQ20 42 2
DDR_B_D8 DDR_B_D9 0.1U_0402_10V7K
43 DQ17 DQ21 44
<7> DDR_B_MA[0..15] 45 VSS15 VSS16 46
DDR_B_DQS#1
DDR_B_DQS1 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D11
Layout Note: Note: DDR_B_D14 51 VSS18
DQ18
DQ22
DQ23
52 DDR_B_D10
CAD NOTE
DDR_B_D15 53 54
Place near JDIMM2 Check voltage tolerance of DDR_B_D31
55
57
DQ19
VSS20
VSS19
DQ28
56
58
DDR_B_D30
DDR_B_D26 PLACE THE CAP NEAR TO
DQ24 DQ29
VREF_DQ at the DIMM socket DDR_B_D25 59
61 DQ25 VSS21
60
62 DDR_B_DQS#3
DIMM RESET PIN
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D27 67 VSS23 VSS24 68 DDR_B_D29
DDR_B_D24 69 DQ26 DQ30 70 DDR_B_D28
+1.35V 71 DQ27 DQ31 72
VSS25 VSS26
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB 75 CKE0 CKE1 76 DDR_CKE3_DIMMB <7>
1 1 1 1 1 1 1 1 VDD1 VDD2
77 78 DDR_B_MA15
NC1 A15
CD35
CD36
CD37
CD38
CD39
CD40
CD41
CD42
C DDR_B_BS2 79 80 DDR_B_MA14 C
<7> DDR_B_BS2 81 BA2 A14 82
2 2 2 2 2 2 2 2 DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
+1.35V 99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 103 CK0 CK1 104 M_CLK_DDR3 <7>
M_CLK_DDR#2 M_CLK_DDR#3
<7> M_CLK_DDR#2 105 CK0# CK1# 106 M_CLK_DDR#3 <7>
VDD11 VDD12
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
DDR_B_MA10 107 108 DDR_B_BS1

109 A10/AP BA1 110 DDR_B_BS1 <7>
DDR_B_BS0 DDR_B_RAS#
<7> DDR_B_BS0 111 BA0 RAS# 112 DDR_B_RAS# <7>
1 VDD13 VDD14
1 1 @ 1 1 @ 1 1 1 1 DDR_B_WE# 113 114 DDR_CS2_DIMMB#
<7> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
CD43
CD44
CD45
CD46
CD47
CD48
CD49
CD50
CD51
+ DDR_B_CAS# 115 116 M_ODT2

<7> DDR_B_CAS# 117 CAS# ODT0 118 M_ODT2 <17>
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
2 2 2 2 2 2 2 2 2 121 A13 ODT1 122 M_ODT3 <17> +SM_VREF_CA_DIMM
DDR_CS3_DIMMB#
<7> DDR_CS3_DIMMB# 123 S1# NC2 124
125 VDD17 VDD18 126 1 2
127 NCTEST VREF_CA 128
VSS27 VSS28
2.2U_0402_6.3V6M
0.1U_0402_10V7K
DDR_B_D32 129 130 DDR_B_D33 @
DDR_B_D35 131 DQ32 DQ36 132 DDR_B_D34 RD10
133 DQ33 DQ37 134 0_0402_1%
VSS29 VSS30 1 1
CD53
DDR_B_DQS#4 135 136
DQS#4 DM4
CD52
DDR_B_DQS4 137 138
139 DQS4 VSS31 140 DDR_B_D39
DDR_B_D36 141 VSS32 DQ38 142 DDR_B_D37 2 2
DDR_B_D38 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
Layout Note: VSS34 DQ44
DDR_B_D40 147 148 DDR_B_D41
Place near JDIMM2.203,204 DDR_B_D45 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
B DM5 DQS5 B
155 156
DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46
161 DQ43 DQ47 162
+0.675VS DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D55
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D48
VSS44 DQ54
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D50 175 176 DDR_B_D54

DDR_B_D53 177 DQ50 DQ55 178
1 1 1 1 1 1 DQ51 VSS45
CD54
CD55
CD56
CD57
CD58
CD59
179 180 DDR_B_D56

DDR_B_D63 181 VSS46 DQ60 182 DDR_B_D57
DDR_B_D62 183 DQ56 DQ61 184
2 2 2 2 2 2 185 DQ57 VSS47 186 DDR_B_DQS#7
189 DM7 DQS7 190
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D61
195 DQ59 DQ63 196
+3VS 197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA DDR_XDP_WLAN_TP_SMBDAT <17,32,6,9>
2 1 201 202
203 SA1 SCL 204 DDR_XDP_WLAN_TP_SMBCLK <17,32,6,9>
RD12 10K_0402_5% +0.675VS +0.675VS
VTT1 VTT2
1
10K_0402_5%
RD13
0.1U_0402_10V7K
205 206
G1 G2
2.2U_0402_6.3V6M
1 1
CD61
@ BELLW_80011-1021
CD60
CONN@
2
2 2
A A

DDRIII DIMMB
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
D D
UG1 GCLK@ UG1 @
SLG3NB3375VTR TQFN 16P CRYSTAL SLG3NB3374VTR TQFN 16P CRYSTAL
SLG3NB3374V is for DIS by output 24M*1,25M*1, 27M*1, 32K*1

SLG3NB3375V is for UMA by output 24M81, 25M*1, 32K*1
+RTCVCC +RTCBATT
+RTCVCC
1
RG4 RG1
1
330_0402_5% 330_0402_5%
+1.05VS_PCH +LAN_VDD33 +3VLP +3VALW @ GCLK@ RG2 @
0_0402_5%
2
1 GCLK@ 1 GCLK@ 1 GCLK@ 1 GCLK@
2.2U_0603_6.3V6K
CG2 CG3 CG4 CG10
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
C CG5 1 C
2 2 2 2 22U_0805_6.3V6M
CG6
GCLK@
GCLK@ 2
UG1 2
GCLK_VRTC 10 14 RTC_VOUT
VBAT VDD_RTC_OUT
Place close 15 CPU_RTC 32.768k(P.8)
+3VLP +V3.3A
to UG1.8 Place RG3 close to YC1
2 0_0402_5%
+3VALW VDD 9 PCH_RTCX1_R RG3 1 2
32kHz PCH_RTCX1 <8>
GCLK@
11 12
VDDIO_27M 27MHz
+LAN_VDD33
8 6 LAN_X1_R RG5 1 2 33_0402_5% XTLI_R 1 2
VDDIO_25M_A 25MHz_A XTLI <21>
GCLK@ RG8 GCLK@ 0_0402_5%
3 5 PCH_X1_R RG6 1 2 22_0402_5%
+1.05VS_PCH VDDIO_25M_B 25MHz_B XTAL24_IN <9>
GCLK@ 1 LAN 25M(P.21)
CLK_X1 1 GCLK@ Place RG8 close to YL2
CLK_X2 16 XTAL_IN
XTAL_OUT
CPU_CLK 24M(P.9) CG7
GND1
GND2
GND3
GND4
CLK_X1 Place RG6 close to YC2 5P_0402_50V8C
CG8 GCLK@ 2
2 1
RG3,RG8, RG6 0ohm_0402
4
7
13
17
15P_0402_50V8J YG1 GCLK@ SLG3NB274VTR_TQFN16_2X3 for isolated CLK tail
1 2
OSC GND @
3 4
OSC GND
CG9 GCLK@ 25MHZ_10PF_7V25000014
2 1
12P_0402_50V8J CLK_X2
B B
A A

Green CLK
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
D Place close to JHDMI D
+VDISPLAY_VCC
WCM-2012HS-900T_4P W=40mils
TMDS_TXCN 1 2 TMDS_L_TXCN +5VS
2 1
1 2
10U_0603_6.3V6M
0.1U_0402_16V7K
1 1
CX21
CX12 2 1 0.1U_0402_10V7K TMDS_TXCN FX1
<6> DDI1_LANE_N3
CX13 2 1 0.1U_0402_10V7K TMDS_TXCP TMDS_TXCP 4 3 TMDS_L_TXCP 1.5A_6V_1206L150PR~D CX22
<6> DDI1_LANE_P3 4 3
CX14 2 1 0.1U_0402_10V7K TMDS_TX0N LX2 EMI@ +3VS 2 2
<6> DDI1_LANE_N2
CX15 2 1 0.1U_0402_10V7K TMDS_TX0P
<6> DDI1_LANE_P2
CX16 2 1 0.1U_0402_10V7K TMDS_TX1N
<6> DDI1_LANE_N1
CX17 2 1 0.1U_0402_10V7K TMDS_TX1P
<6> DDI1_LANE_P1
1
CX18 2 1 0.1U_0402_10V7K TMDS_TX2N RX12
<6> DDI1_LANE_N0 WCM-2012HS-900T_4P
CX19 2 1 0.1U_0402_10V7K TMDS_TX2P 10K_0402_5%
<6> DDI1_LANE_P0 1 2
TMDS_TX0N TMDS_L_TX0N
1 2
2
JHDMI
TMDS_TX0P 4 3 TMDS_L_TX0P HDMI_HPLUG 19
4 3 HP_DET
1
2
3
4
4
3
2
1
18
RP59 RP58 LX3 EMI@ 17 +5V
CPU_DPB_CTRLDAT_R 16 DDC/CEC_GND
680_8P4R_5% 680_8P4R_5% SDA
CPU_DPB_CTRLCLK_R 15
14 SCL
8
7
6
5
5
6
7
8
13 Reserved
TMDS_L_TXCN 12 CEC 20
11 CK- GND 21
WCM-2012HS-900T_4P TMDS_L_TXCP 10 CK_shield GND 22
TMDS_TX1N 1 2 TMDS_L_TX1N TMDS_L_TX0N 9 CK+ GND 23
1 2 8 D0- GND
TMDS_L_TX0P 7 D0_shield
+3VS TMDS_TX1P 4 3 TMDS_L_TX1P TMDS_L_TX1N 6 D0+
4 3 D1-
1
5
D LX4 EMI@ TMDS_L_TX1P 4 D1_shield
C D1+ C
2 QX3 TMDS_L_TX2N 3
G 2N7002K_SOT23-3 2 D2-
D2_shield
1
S TMDS_L_TX2P 1
RX13 D2+
3
100K_0402_5% CONCR_099ATAC19NBLCNF
CONN@
2
LX5 EMI@
TMDS_TX2P 4 3 TMDS_L_TX2P
4 3
TMDS_TX2N 1 2 TMDS_L_TX2N 46@ ROYALTY HDMI W/LOGO

1 2
Part Number Description
WCM-2012HS-900T_4P
RO0000002HM HDMI W/Logo:RO0000002HM
TMDS_L_TXCN @EMI@ CX23 1 2 3.3P_0402_50V8C
TMDS_L_TXCP @EMI@ CX24 1 2 3.3P_0402_50V8C
TMDS_L_TX0N @EMI@ CX25 1 2 3.3P_0402_50V8C
TMDS_L_TX0P @EMI@ CX26 1 2 3.3P_0402_50V8C
TMDS_L_TX1N @EMI@ CX27 1 2 3.3P_0402_50V8C

+5VS
B TMDS_L_TX2N @EMI@ CX29 1 2 3.3P_0402_50V8C B

+3VS
2
RX16 RX17
2.2K_0402_5% 2.2K_0402_5%
QX4B
1
1
2
DMN66D0LDW-7_SOT363-6 +3VS
G
1 6 CPU_DPB_CTRLCLK_R
<10> CPU_DPB_CTRLCLK
S
D
5
1
C
QX5 2 1 2 HDMI_HPLUG
G
<10> CPU_DPB_CTRLDAT
4 3 CPU_DPB_CTRLDAT_R MMBT3904_NL_SOT23-3 B
S
E RX15 1
1
QX4A <10> DPB_HPD 150K_0402_5%
DMN66D0LDW-7_SOT363-6 CX20 @
1
220P_0402_50V8J RX34
2 20K_0402_5%
RX14
2
100K_0402_5%
2
A A

HDMI
1.0
LA-B012P
5 4 3 2 1
1 2 3 4 5
W=40mils +LAN_IO rising time : >1ms and <100ms 60mils_3via

JP3 @
2 1 2 LAN_L@ 1
W=40mils +LAN_REGOUT RL1 +LAN_VDD10
+3VALW 2MM 0_0603_5%
LAN_SW@ 40mils_2via
+LAN_VDD33
CL39 +LAN_REGOUT 1 2
1U_0402_6.3V6K UL2
W=40mils 1.5A LL1
2 1 5 1 2.2UH_LQM2MPN2R2NG0L_30%
VIN VOUT 1 1 1 1 1 1 1
A A
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1U_0402_6.3V4Z
0.1U_0402_10V7K
0.1U_0402_10V7K
LAN_SW@
4.7U_0603_6.3V6K
1 1
CL5
CL6
CL7
CL8
CL9
CL4
WOL_EN 3 CL3
<30> WOL_EN EN 0.1U_0402_25V6
CL15 CL19 2 LAN_L@ 2 2 2 2 2 2
4 2 2 2
SS GND
2
RL27 APL3512ABI-TRG_SOT23-5
100K_0402_5% 1 @
@
CL38 RTL8111G(LDO mode) RTL8111GS(SWR mode) Place close to each VDD10 pin
1
0.1U_0603_25V7K
2
APL3512 PIN 4 tire to VIN
+LAN_VDD33 +3VALW +LAN_VDD33 +LAN_VDDREG

@
RL6 1 2 0_0603_5%
UL3
1 5
+3VALW OUT IN
0.1U_0402_16V7K
4.7U_0603_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
2 @1 @1 1 @ 2 @1
CL12
CL13
CL14
RL40 GND
CL16
CL17
1 2 3 4 WOL_EN
10K_0402_5% OC EN @
2 2 2 1 2
SY6288C20AAC_SOT23-5
B These caps close to UL1: Pin 11,32

+LAN_VDD33 Rising time (10%~90%) 要>1mS and <100mS B
CL30, CL31 close to UL1 Pin 17, 18 UL1

+LAN_VDD10 TL2
CL30 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_P3_C 17 3
<12> PCIE_PRX_LANTX_P3 HSOP AVDD10
CL31 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_N3_C 18 8
<12> PCIE_PRX_LANTX_N3 HSON AVDD10 30
AVDD10 22
DVDD10
+LAN_VDD33 S X'FORM_ NS14Y LF LAN
11 SP050007J00
AVDD33 32 RL19
AVDD33 TL2 75_0603_5%
PCIE_PTX_LANRX_P3 13
<12> PCIE_PTX_LANRX_P3 HSIP MCT0 1 2
PCIE_PTX_LANRX_N3 14 23 +LAN_VDDREG MDI1- 1 16 MDO1-
<12> PCIE_PTX_LANRX_N3 HSIN VDDREG RD+ RX+
24 +LAN_REGOUT MDI1+ 2 15 MDO1+
REGOUT RD- RX-
3 14 MCT0 MCT1 1 2
1 MDI0+ 4 CT CT 13
MDIP0 2 MDI0- NC NC
MDIN0 5 12 RL20
4 MDI1+ 6 NC NC 11 MCT1 1
19 MDIP1 5 MDI1- CT CT 75_0603_5% EMI@
<10,26,30,34,6> PLT_RST# PERSTB MDIN1 MDI0- 7 10 MDO0- CL33
MDI0+ 8 TD+ TX+ 9 MDO0+
ISOLATEB 20 15 TD- TX- 10P_1206_2KV8J
ISOLATEB REFCLK_P CLK_PCIE_LAN <9> 2
16
REFCLK_N CLK_PCIE_LAN# <9> 2
<10,30> PCIE_WAKE#
PCIE_WAKE# 21
LANWAKEB CLKREQB
12
LAN_CLKREQ# <9> CL41
350UH_LF-H1201P-2
@
Place close to TCT pin
28 XTLO
CKXTAL1 0.01U_0402_16V7K
1 2 26 29 XTLI 1
+LAN_VDD33 LED1/GPO CKXTAL2
RL39 10K_0402_5%
@ 25 @ T94 PAD~D
6 LED2 27 @ T95 PAD~D
7 NC LED0
C
9 NC 31 RL31 2 1 2.49K_0402_1%
C
10 NC RSET
NC
GND
33 For GCLK JLAN
RTL8106E-CG QFN 32P E-LAN CTRL XTLI 8

<19> XTLI PR4-
7
PR4+
+3VS
MDO1- 6
PR2-
+LAN_VDD33 CL36 5
1
1 2 XTLI PR3-
RL33
4
1K_0402_5% 10P_0402_50V8J YL2 PR3+
1 2 PCIE_WAKE# 1 2 MDO1+ 3
OSC GND PR2+
2
RL34 XTAL@
3 4 MDO0- 2
10K_0402_5% ISOLATEB OSC GND PR1-
CL37 25MHZ_10PF_7V25000014 MDO0+ 1
1 2 XTLO PR1+
9
2
XTAL@ GND
10P_0402_50V8J
RL35
10
15K_0402_5% GND
XTAL@
+3VS +LAN_VDD33
1
XTAL CONN@
@
LAN_CLKREQ# 1 2
RL37 10K_0402_5%
@
WOL_EN 1 2
D D
RL38 10K_0402_5%
Reserve 10K pull LAN_IO

Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2014/01/20 Deciphered Date 2015/01/19
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL LAN RTL8106EUS
Custom 1.0
1 2 3 4 5
5 4 3 2 1
CA53, CA55 change Value

Line1-VREFO-L
CA71, CA51 place close to Pin 26 from 10U_0603_6.3V6M~D to Line1-VREFO-R
4.7U_0603_6.3V6K
CA57,CA58 close JACK_PLUG Delay circutis
1
+5VA +5V_PVDD +5V_PVDD
RA165 RA166
to UA1 pin1 4.7K_0402_5% 4.7K_0402_5%
+3VS +3VS
4.7U_0603_6.3V6K
CA71
4.7U_0603_6.3V6K
CA53
4.7U_0603_6.3V6K
CA55
1 1 1
+3VS
1 1 1
2
0.1U_0402_16V7K
CA51
0.1U_0402_16V7K
CA54
0.1U_0402_16V7K
CA56
1 1
1
2 2 2
0.1U_0402_16V7K
CA58
4.7U_0603_6.3V6K
CA57
LINE1-L CA67 1 2 1 2 Line-IN-L @ @ JACK_SENSE#
2 2 2 4.7U_0603_6.3V6K RA80 1K_0402_1% RA1 RA2
LINE1-R CA68 1 2 1 2 Line-IN-R 100K_0402_5% 100K_0402_5%
2 2 4.7U_0603_6.3V6K RA82 1K_0402_1%
D D
3
@
5
D
G
QA5A
@ S DMN66D0LDW-7_SOT363-6
CPVDD 1 QA5B
+3VS +CODEC_AVDD2
4
6
UA1 CA61 DMN66D0LDW-7_SOT363-6
CA59 CA60 close CA59
1 1
CA60 1 26 4.7U_0603_6.3V6K JACK_PLUG# 1 2 2 G
D
4.7U_0603_6.3V6K 0.1U_0402_16V7K DVDD AVDD1 40 @

to UA1 pin9 9 AVDD2 2 Reserve for HDA issue S
RA3
1
2 2 DVDD-IO 10K_0402_5% 1 1
36 CPVDD
CPVDD 41 +3VS +1.5VS +CODEC_AVDD2 @ @
6 PVDD1 46 CA1 CA2
<8> PCH_AZ_CODEC_BITCLK BCLK PVDD2 2 2 10U_0603_6.3V6M
RA8 1 2 0_0402_5% 10U_0603_6.3V6M
5
<8> PCH_AZ_CODEC_SDOUT SDATA-OUT 13 JACK_SENSE# RA13 1 2 100K_0402_5%
HP/LINE1 JD(JD1) +3VS
10 14 RA9 1 @ 2 0_0402_5%
<8> PCH_AZ_CODEC_SYNC SYNC MIC2/LINE2 JD(JD2) 15
1 2 8 SPDIFO/FRONT JD(JD3)/GPIO3
<8> PCH_AZ_CODEC_SDIN0 SDATA-IN
RA130 22_0402_5%
11
<8> PCH_AZ_CODEC_RST# RESETB 32 HPOUT-L JACK_PLUG# RA4 1 2 200K_0402_5% JACK_SENSE#
HPOUT-L(PORT-I-L) 33 HPOUT-R
LINE1-R 21 HPOUT-R(PORT-I-R)
LINE1-L
Line1-VREFO-R
22
30
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
Reserve for cancel Delay circutis
Line1-VREFO-L 31 LINE1-VREFO-R 42 INT-SPK-L+ +5V_PVDD +5VS +MIC2-VREFO
23 LINE1-VREFO-L SPK-OUT-L+ 43 INT-SPK-L-
24 LINE2-R(PORT-E-R) SPK-OUT-L- 45 INT-SPK-R+
LINE2-L(PORT-E-L) SPK-OUT-R+ 44 INT-SPK-R- 2 1
+A_VCC SPK-OUT-R- RA1110
16 +5VA @ 0_0603_1% +5VS 2 1 MIC_IN
MONO-OUT RA53 2.2K_0402_5% RA29 1 2 0_0603_1%
2 @
1 2 +MIC2-VREFO 29 GPIO0/DMIC-DATA 3 MIC_CLK_C MIC_DATA <31> 2 1 2 1 RING2 1 2 0_0603_1%
+3VALW +MIC2-VREFO RA30
RA10 0_0402_5% RING2 17 MIC2-VREFO GPIO1/DMIC-CLK 48 RA1111 RA1109 2.2K_0402_5% @
MIC_IN 18 MIC2-L(PORT-F-L)/RING SPDIF-OUT/GPIO2 @ 0_0603_1% RA31 1 2 0_0603_1%
C MIC2-R(PORT-F-R)/SLEEVE C
1 2 2 1 MIC1-L 19 @
+RTCVCC MIC_CAP
RA11 0_0402_5% 10U_0603_6.3V6M CA74 37 RA32 1 2 0_0603_1%
CBP 35 1U_0402_6.3V6K 2 1 CA24 @
@ CBN
20
+A_VCC NC
EC_MUTE# 47
<30> EC_MUTE# PDB 28 2 1
RA12 1 2 100K_0402_5% VREF 12
2.2U_0603_6.3V6K CA23 GNDA GND
CA62 1 2 10U_0603_6.3V6M 27 PCBEEP 34 1U_0402_6.3V6K 2 1 CA25
CA63 1 2 10U_0603_6.3V6M 39 LDO1-CAP CPVEE
@EMI@ CA64 1 2 10U_0603_6.3V6M 7 LDO2-CAP
RA1112 LDO3-CAP Place on the moat between GND & GNDA.
0_0402_5% 0_0402_5%
PCH_AZ_CODEC_BITCLK 1 2 1 2 4 25
@ RA1113 DVSS AVSS1 38
49 AVSS2
1 GND
@EMI@
CA21 ALC3234-CG_MQFN48_6X6
22P_0402_50V8J
2 LA1 EMI@
MIC_CLK_C 1 2 MIC_CLK DA8
MIC_CLK <31> 2
BLM15BB221SN1D_2P
PC_BEEP 2 1 RA79 2 1 CA65 EC Beep <30> BEEP#
1K_0402_1% 0.1U_0402_16V7K 1 PC_BEEP
SM01000BV00 1
@EMI@
100P_0402_50V8J 2 1 CA69 @ CA22 3
need CIS symbol MCU Beep <11> HDA_SPKR
1
22P_0402_50V8J
2 BAT54C-7-F_SOT23-3 @
10K_0402_5% 1 2 RA81 @ RA19
10K_0402_5%
2
+RTCVCC
PC Beep
1
MIC_IN
B RA5 Close to UA1 B
470K_0402_5% Pin11,13,14,16
close to Codec
2
JSPK
3
INT-SPK-R- EMI@ LA3 1 2 NBQ160808T-800Y-N 0603 SPK_R1-_CONN 1

5 G
D
QA6A INT-SPK-R+ EMI@ LA4 1 2 NBQ160808T-800Y-N 0603 SPK_R2+_CONN 2 1
QA6B S DMN66D0LDW-7_SOT363-6 INT-SPK-L- EMI@ LA5 1 2 NBQ160808T-800Y-N 0603 SPK_L1-_CONN 3 2
DMN66D0LDW-7_SOT363-6 INT-SPK-L+ EMI@ LA6 1 2 NBQ160808T-800Y-N 0603 SPK_L2+_CONN 4 3
4
4
6
5
PCH_AZ_CODEC_RST# 1 2 2
D
6 G1
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R-
G
G2
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
RA6 10K_0402_5% S
1 1 1 1 ACES_50278-00401-001
1
3
Speaker 4 ohm : 40mil
EMI@ CA29
EMI@ CA30
EMI@ CA31
EMI@ CA32
1 2 CONN@
+3VS
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
RA7 @ 10K_0402_5%
Speaker 8 ohm : 20mil 2 2 2 2 ESD@

DA13
ESD@
DA14
1
JHP
RING2_R 3
iPhone and Nokia type Combo Jack AUD_HP_OUT_L_CN 1
EMI@
MIC_IN LA7 2 1 BLM15PX330SN1D 0402 40mil MIC_IN_R JACK_PLUG# 5
EMI@
RA55 RING2 LA10 2 1 BLM15PX330SN1D 0402 40mil RING2_R 6
8.2_0402_1% EMI@
HPOUT-L 1 2 Line-IN-L LA8 2 1 CHILISIN NBQ160808T-800Y-N 0603 AUD_HP_OUT_L_CN AUD_HP_OUT_R_CN 2
EMI@
HPOUT-R 1 2 Line-IN-R LA9 2 1 CHILISIN NBQ160808T-800Y-N 0603 AUD_HP_OUT_R_CN MIC_IN_R 4
7
8.2_0402_1%
1
RA56 SINGA_2SJ3080-001111F
A RA84 RA83 CONN@ A
10K_0402_5% 10K_0402_5%
@ @
2
2
AZ5125-02S.R7G_SOT23-3
DA10
ESD@
AZ5123-02S SOT23
DA12
ESD@
1 1 1 1
100P_0402_50V8J
CA39 EMI@
100P_0402_50V8J
CA33 EMI@
1000P_0402_50V7K
CA38 EMI@
1000P_0402_50V7K
CA40 EMI@
2 2 2 2
1
Audio Codec ALC3234
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
1.0
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Reserved Page
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
+5VALW
USB connector1
USB20 port0
CI18
1
CI12
1 1
CI14
USB30 port1
1
LI1 EMI@
2
47U_0805_6.3V4Z
2
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR1
USB3RN1_JUSB1 USB3RN1_JUSB1_R
<12> USB3RN1_JUSB1
D D
UI3
USB3RP1_JUSB1 4 3 USB3RP1_JUSB1_R 1 8 +5V_USB_PWR1
<12> USB3RP1_JUSB1 2 GND VOUT 7 80mil
DLW21SN670HQ2L_4P 3 VIN VOUT 6 JUSB1
VIN VOUT
EPAD
USB_EN# 4 5 USB_OC0# 1
<25,30> USB_EN# EN FLG VBUS
10U_0603_6.3V6M
0.1U_0402_16V7K
USB20_JUSB1_N0_R 2
USB20_JUSB1_P0_R 3 D-
1 1 1 D+
CI13 CI15 1 1 4
9
@ AP2301MPG-13_MSOP8 CI1 + USB3RN1_JUSB1_R 5 GND
StdA-SSRX-
0.1U_0402_16V7K
CI40
CI2
0.1U_0402_16V7K USB3RP1_JUSB1_R 6 10
2 2 220U_6.3V_M 7 StdA-SSRX+ GND 11
2 2 2 USB3TN1_JUSB1_R 8 GND-DRAIN GND 12
StdA-SSTX- GND
3
USB3TP1_JUSB1_R 9 13
StdA-SSTX+ GND
DI2 TAITW_PUBAU6-09FLBS1NN4H0
LI3 EMI@ CONN@
USB3TN1_JUSB1 2 1 USB3TN1_JUSB1_C 1 2 USB3TN1_JUSB1_R L30ESDL5V0C3-2_SOT23-3
<12> USB3TN1_JUSB1
CI3 0.1U_0402_10V7K
ESD@
USB3TP1_JUSB1 2 1 USB3TP1_JUSB1_C 4 3 USB3TP1_JUSB1_R +5V_USB_PWR1
<12> USB3TP1_JUSB1 +5VALW
CI4 0.1U_0402_10V7K
1
DLW21SN670HQ2L_4P UI5
1
5 OUT
IN 2
USB_EN# 4 GND
EN 3 USB_OC0#
OCB ESD@
SY6288D20AAC_SOT23-5 DI1
USB3RN1_JUSB1_R 1 10 USB3RN1_JUSB1_R
USB3RP1_JUSB1_R 2 9 USB3RP1_JUSB1_R
EMI@
LI2 USB3TN1_JUSB1_R 4 7 USB3TN1_JUSB1_R
USB20_JUSB1_N0 1 2 USB20_JUSB1_N0_R
<12> USB20_JUSB1_N0 1 2 5 6
USB3TP1_JUSB1_R USB3TP1_JUSB1_R
C C
USB20_JUSB1_P0 4 3 USB20_JUSB1_P0_R 3
<12> USB20_JUSB1_P0 4 3
WCM-2012HS-900T_4P 8
IP4292CZ10-TBR_XSON10_2.5X1~D
USB connector2
+5VALW USB20 port0
USB30 port1
1 1
CI6 CI7
1
LI4 EMI@
2
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR2
USB3RN2_JUSB2 USB3RN2_JUSB2_R
<12> USB3RN2_JUSB2
UI2
USB3RP2_JUSB2 4 3 USB3RP2_JUSB2_R 1 8
B
<12> USB3RP2_JUSB2 2 GND VOUT 7 80mil +5V_USB_PWR2
B
DLW21SN670HQ2L_4P 3 VIN VOUT 6
VIN VOUT
EPAD
USB_EN# 4 5 USB_OC0# JUSB2
EN FLG USB_OC0# <12> 1
VBUS
10U_0603_6.3V6M
0.1U_0402_16V7K
1 1 USB20_JUSB2_N1_R 2
CI26 CI17 USB20_JUSB2_P1_R 3 D-
1
9
@ AP2301MPG-13_MSOP8 4 D+
1 1 GND
0.1U_0402_16V7K
0.1U_0402_16V7K CI8 + USB3RN2_JUSB2_R 5

2 2 StdA-SSRX-
CI43
CI9
USB3RP2_JUSB2_R 6 10
220U_6.3V_M 7 StdA-SSRX+ GND 11
2 2 2 USB3TN2_JUSB2_R 8 GND-DRAIN GND 12
USB3TP2_JUSB2_R 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
3
LI6 EMI@
USB3TN2_JUSB2 2 1 USB3TN2_JUSB2_C 1 2 USB3TN2_JUSB2_R TAITW_PUBAU6-09FLBS1NN4H0
<12> USB3TN2_JUSB2
CI10 0.1U_0402_10V7K DI5 CONN@
USB3TP2_JUSB2 2 1 USB3TP2_JUSB2_C 4 3 USB3TP2_JUSB2_R L30ESDL5V0C3-2_SOT23-3

<12> USB3TP2_JUSB2
CI11 0.1U_0402_10V7K
DLW21SN670HQ2L_4P +5V_USB_PWR2 ESD@
+5VALW
UI6
1
1
5 OUT
IN 2
USB_EN# 4 GND
EN 3 USB_OC0# ESD@
OCB DI4
SY6288D20AAC_SOT23-5 USB3RN2_JUSB2_R 1 10 USB3RN2_JUSB2_R
EMI@
LI5 USB3RP2_JUSB2_R 2 9 USB3RP2_JUSB2_R
USB20_JUSB2_N1 1 2 USB20_JUSB2_N1_R
<12> USB20_JUSB2_N1 1 2 4 7
USB3TN2_JUSB2_R USB3TN2_JUSB2_R
USB20_JUSB2_P1 4 3 USB20_JUSB2_P1_R USB3TP2_JUSB2_R 5 6 USB3TP2_JUSB2_R

<12> USB20_JUSB2_P1 4 3
WCM-2012HS-900T_4P 3
A
8 A
IP4292CZ10-TBR_XSON10_2.5X1~D

USB3.0
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
D
IO to MB CONN D
+5VALW
Substitute:SP01001FS00
1 1
CI44 CI45 JIO
1
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR3
+5V_USB_PWR3
2 1
2
3
4 3
UI4 5 4
1 8 6 5
2 GND VOUT 7 80mil +3VS
7 6
3 VIN VOUT 6 7
8
VIN VOUT 8
EPAD
<24,30> USB_EN# USB_EN# 4 5 USB_OC1# 9
EN FLG USB_OC1# <12> 9
10
USB20_CR_P6_R 11 10
1 1 11
CI46 CI47 USB20_CR_N6_R 12
9
@ AP2301MPG-13_MSOP8 13 12
13
0.1U_0402_16V7K
0.1U_0402_16V7K USB20_JUSB3_P2_R 14
2 2 USB20_JUSB3_N2_R 15 14
16 15
C 16 C
17
18 GND
GND
ACES_51524-0160N-001
CONN@
+5V_USB_PWR3
+5VALW
UI7
1
5 OUT
IN 2
USB_EN# 4 GND
EN 3 USB_OC1#
OCB
SY6288D20AAC_SOT23-5
B LED/B TO M/B B
+3VALW_EC +5VS +5VALW

SP01001A900
WCM-2012HS-900T_4P
4 3 USB20_JUSB3_P2_R JLED
<12> USB20_JUSB3_P2 4 3
1
2 1
1 2 USB20_JUSB3_N2_R 3 2
<12> USB20_JUSB3_N2 1 2 3
LID_SW# 4
LI7 <30> LID_SW# 4
<30> BATT_LOW_LED# BATT_LOW_LED# 5
EMI@ BATT_CHG_LED# 6 5 9
<30> BATT_CHG_LED# 6 G1
SATA_ACT# 7 10
<8> SATA_ACT# 7 G2
8
WCM-2012HS-900T_4P 8
4 3 USB20_CR_P6_R ACES_51524-0080N-001
<12> USB20_CR_P6 4 3
CONN@
1 2 USB20_CR_N6_R
<12> USB20_CR_N6 1 2
LI8
EMI@
A A

IO/B, LED/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
closed to pin 2, 4 closed to pin 64, 66
+3VS_WLAN_NGFF +3VS_WLAN_NGFF
NGFF WL Con (E Key)
22U_0603_6.3V6M~D
0.1U_0402_10V7K~D
22U_0603_6.3V6M~D
0.1U_0402_10V7K~D
1 1 1 1
CM4
CM6
CM5
CM7
2 2 2 2
D D
+3VS_WLAN_NGFF
JNGFF
1 2
USB20_MINI1_P4 3 GND 3.3VAUX 4
<12> USB20_MINI1_P4 5 USB_D+ 3.3VAUX 6
USB20_MINI1_N4 @ T3861 PAD~D
<12> USB20_MINI1_N4 7 USB_D- LED1# 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
17 SDO_DAT1 LED2# 18 @ T3862 PAD~D
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22
For EC to detect
23 SDIO_WAKE# UART_RX debug card
SDIO_RESET#
insert.
RM9 100K_0402_5%
24 1 2
25 UART_TX 26
27 GND UART_CTS 28
<12> PCIE_PTX_WLANRX_P4 PETP0 UART_RTS
29 30 EC_TX
<12> PCIE_PTX_WLANRX_N4 PETN0 RESERVED EC_TX <30>
31 32 EC_RX
33 GND RESERVED 34 EC_RX <30>
<12> PCIE_PRX_WLANTX_P4 35 PERP0 RESERVED 36
<12> PCIE_PRX_WLANTX_N4 37 PERN0 COEX3 38 @ T4927 PAD~D
39 GND COEX2 40 @ T4928 PAD~D
<9> CLK_PCIE_WLAN CLK_PCIE_WLAN
<9> CLK_PCIE_WLAN# CLK_PCIE_WLAN# 41
43
REFCLKP0
REFCLKN0
COEX1
SUSCLK
42
44
@ T4929 PAD~D
SUSCLK_R RM51
PLT_RST#_R RM61
@
@
2 0_0402_1%
2 0_0402_1%
SUSCLK <10> +3VALW TO +3VS_WLAN_NGFF
45 GND PERST0# 46 PLT_RST# <10,21,30,34,6>
WLAN_CLKREQ# BT_ON#
<9> WLAN_CLKREQ# 47 CLKEQ0# W_DISABLE2# 48 BT_ON# <11>
WLAN_WAKE# WL_OFF#_R
<30> WLAN_WAKE# 49 PEWAKE0# W_DISABLE1# 50
51 GND I2C_DATA 52 +3VS +3VS_WLAN_NGFF
53 RSRVD/PETP1 I2C_CLK 54
C RSRVD/PETN1 ALERT C
55 56
57 GND RESERVED 58
59 RSRVD/PERP1 RESERVED 60 RM7
61 RSRVD/PERN1 RESERVED 62 1 2
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66 0_1206_5%
67 RESERVED 3.3VAUX NAOAC@
GND
69 68
MTG77 MTG76
+3VS_WLAN_NGFF
LOTES_APCI0019-P009A +3VALW
CONN@
2
2 AOAC@
AOAC@ CM3
CM8 100U_1206_6.3V6M
1U_0402_6.3V6K UM1 1
1 5 1
IN OUT +3VALW
2
GND RM10
+3VS_WLAN_NGFF +3VS 4 3 2 1
<30> AOAC_WLAN EN OC 10K_0402_5%
SY6288C20AAC_SOT23-5 AOAC@
1
AOAC@
RM8
10K_0402_5%~D QM1
2
DII-DMN65D8LW-7~D
G
2
WL_OFF#_R 1 3
WL_OFF# <11>
S
B Prevent Backdriver from +3VS_WLAN_NGFF to +3VS B
A A

NGFF WLAN
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
Power ON Circuit +FAN_POWER
40mil
+3VLP
FAN Control circuit HE1 place around FAN area.
ON/OFF switch
2.2U_0603_6.3V6K
1000P_0402_50V7K
1 1
2
TOP Side RE49 CE22 CE23
100K_0402_5% +5VS +3VALW +3VLP
2 2 CE25
2
D SW1 2.2U_0603_6.3V6K D
2
SMT1-05-A_4P 1 2 RE332
1 3 13.7K_0402_1% RE333
ON/OFFBTN# <30>
AOAC@ @ 13.7K_0402_1%
2 4 1 UE3
1
1 8
1
CE20 2 VEN GND 7
6
5
0.1U_0402_16V7K 3 VIN GND 6

2 4 VO GND 5 <30> VCIN0_PH2
<30> EN_DFAN1 EN_DFAN1
VSET GND
1
APE8875M SOP 8P
AOAC@
@ESD@
+3VS HE1
2
L03ESDL5V0CC3-2_SOT23-3 100K_0402_1%_TSM0B104F4251RZ
DE2
1
+FAN_POWER
1
RE50
10K_0402_5%
40mil JFAN
2
1
2 1 4
<30> FAN_SPEED1 3 2 GND 5
3 GND
J519 short 1
ACES_88231-03041
CE24 CONN@
J519 @ 0.01U_0402_16V7K
1 2 2
1 2
JUMP_43X39
RE330 +V_TP +3VS_TOUCH
0_0603_5%
+3VALW
1 2 +V_TP UE4
1 7
2 VIN VOUT 8
C VIN VOUT C
RE331 0_0603_5%
0.1U_0402_10V6K
1
1 2 3 6
+3VS <30> TP_EN ON CT
CE59
2200P_0402_25V7K
1
CE60
@ @
4 2
VBIAS 5 @
GND 9 2
+3VALW GND
TPS22967DSGR_SON8_2X2
2
CE61
For Test,
APE8937(SA000070L00)
AOZ1336(SA00006U600)
INT_KBD Connector
@ 1U_0402_6.3V6K TPS22967(SA000070S00)
1
JKB
* Key Board Back Light
30 32
KSI7 29 30 GND 31
KSI6 28 29 GND
KSI4 27 28
KSI2 26 27
KSI5 25 26 +5VS FE1 KBBL@ +5VS_KBL
KSI1 24 25
+3VS_TOUCH KSI3 23 24 0.75A_24V_1812L075-24DR~OK
KSI0 22 23
KSO5 21 22 2 1
21
10U_0603_6.3V6M
+3VS KSO4 20 20mil
20
1U_0603_10V6K
KSO7 19 1 2
19
1
KSO6 18 1 RE59 1
18
CE56
RE334 RE335 KSO8 17 0_0805_5%
17
CE57
10K_0402_5% @ 10K_0402_5% KSO3 16 KBBL@ KBBL@
16 @
B @ KSO1 15 B
15
2
@ KSO2 14 2 2
2
KSO0 13 14
G
I2C1_SDA_TP 1 6 I2C1_SDA_TP_R KSO12 12 13

11 12
S
KSO16
QE6B KSO15 10 11
10
5
DMN66D0LDW-7_SOT363-6 KSO13 9
KSO14 8 9
G
I2C1_SCL_TP 4 3 @ I2C1_SCL_TP_R KSO9 7 8 +3VS

+5VS 6 7
S
KSO11
QE6A RE60 KSO10 5 6 @
DMN66D0LDW-7_SOT363-6 1 2 KB_CAPS_PWR 4 5 RE68
3 4 1 2
3 <11> KB_DET#
240_0402_1% 2
1 2 10K_0402_5% +5VS_KBL
<30> CAPS_LED 1
HB_A823020-SBHR21 JKBBL
1
CONN@ D 1
2 2 1
KSI[0..7] G 3 2
<30> KSI[0..7] 4 3
QE4 S KB_BL_PWM
Touch pad
3
4
1
KSO[0..16] 2N7002KW 1N SOT323-3 5
<30> KSO[0..16] 6 GND
KBBL@ RE58
100K_0402_5%
20mil GND
+3VS_TOUCH KBBL@ ACES_50524-00401-P01
+3VS_TOUCH CONN@
1
2
5
6
+3VS_TOUCH
PTP 3
G
D QE5
AP2606AGY-HF 1N SOT26-6
<30> KB_LED_PWM
2
+3VS_TOUCH +3VS_TOUCH +3VS_TOUCH S KBBL@

RE340 RC78 RE329
4
10K_0402_5% 10K_0402_5% 100K_0402_5% JTP1
@ 1 12
JTP 11 GND
1
8 CE58 GND
8
<11> I2C1_SDA_TP RE336 1 @ 2 0_0402_1% I2C1_SDA_TP_R 7
7 G2
10 1U_0402_6.3V6K~D 10
10
2
A <11> I2C1_SCL_TP RE337 1 @ 2 0_0402_1% I2C1_SCL_TP_R 6
6 G1
9 I2C1_SDA_TP_R 9
9 A
1 RE338 2 0_0402_5% 5 I2C1_SCL_TP_R 8
<30> EC_TP_INT# 4 5 7 8
PTP@ TP_INT#
<10> TP_INT# 3 4 6 7
PTP_DIS# TP_INT#
<30> PTP_DIS# 2 3 5 6
PTP_DIS#
<30> TP_DATA 1 2 4 5
TP_DATA
<30> TP_CLK 1 3 4
TP_CLK
ACES_51524-0080N-001 2 3
<30> PTP_KBBL# 1 2
CONN@
1
1 RE339 2 ACES_51524-0100N-001
+3VS_TOUCH
10K_0402_5%
CONN@ Security Classification Compal Secret Data Compal Electronics, Inc.
FAN / TP / PWR SW / KBBL
1.0
LA-B012P
5 4 3 2 1
A B C D E
+5VS and +3VS switch

1 1
+5VALW +5VS
SHORT DEFAULT
U2301 J510
1 14 5VS 2 1
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1
C2307
10U_0805_10V4Z
C2308
10U_0603_6.3V6M
R2313 C5216 @ JUMP_43X79
1 2 82K_0402_5% 5VS_GATE 3 12 1 2 1000P_0402_50V7K 1 1
<28,30,47,48> SUSP# ON1 CT1
4 11
R2318 VBIAS GND C5217 @
1 2 470K_0402_5% 3VS_GATE 5 10 1 2 1000P_0402_50V7K 2 2
10mil ON2 CT2
+3VALW TO +3V_DSW
6 9 3VS +3V_DSW have soft start
VIN2 VOUT2
1
1
C2322 C2309 +3VALW 7 8
VIN2 VOUT2 sequence: +3V_DSW stable > +3VALW_PCH > 0ms
0.01U_0603_25V7K
0.01U_0603_25V7K
15 +3VS J518 open
2
2
GPAD J518 @
TPS22966DPUR_SON14_2X3 J511 1 2
2 1 1 2
2 1 JUMP_43X39
+3VALW +3V_DSW
C2324
10U_0603_6.3V6M
C2323
10U_0603_6.3V6M
@ JUMP_43X79
+3VALW +5VALW U2408
1 1
SHORT DEFAULT @
+5VALW 1
2 VIN VOUT
7
8
2 2 VIN VOUT
0.1U_0402_10V6K
1
3 6
<30> PCH_DSW_EN ON CT
C2316
10U_0603_6.3V6M
C2318
10U_0603_6.3V6M
C2306
10U_0603_6.3V6M
C2305
10U_0603_6.3V6M
C5213
2200P_0402_25V7K
1
C5214
1 1 1 1 @
4 2
VBIAS 5 @
GND 9 2
2 2 2 2 +3VALW GND
2 2
@ TPS22967DSGR_SON8_2X2
CT pin use 2200pf for
2 For Test,
APE8937(SA000070L00) soft start tuning
C89 AOZ1336(SA00006U600)
@ 1U_0402_6.3V6K TPS22967(SA000070S00)
1
+3VALW_PCH switch
3 3
+5VALW
+5VALW +3VALW +3VALW_PCH +3VALW
SHORT DEFAULT
U2304 J513 J516
10mil
1
1 14 3VALW_PCH 2 1 2 1
2 VIN1 VOUT1 13 2 1 2 1
VIN1 VOUT1
C2310
10U_0805_10V4Z
C2312
10U_0603_6.3V6M
R416 C5218 @ @ JUMP_43X79 @ JUMP_43X79 R10

1 2 0_0402_1% +3VALW_PCH_GATE 3 12 1 2 1000P_0402_50V7K 1 1 100K_0402_5%
<30> PCH_PWR_EN ON1 CT1 +0.675VS +1.05VS_PCH
2
@ 4 11 SUSP
VBIAS GND C5219 @ @
1
1 2 470K_0402_5% +1.05VS_GATE 5 10 1 2 1000P_0402_50V7K 2 2
<28,30,47,48> SUSP# ON2 CT2 D
R2314 R2315
R2451 6 9 +1.05V 22_0603_5% 470_0603_5% SUSP# 2 Q8
VIN2 VOUT2
1
C2325 C2314 +1.05VS 7 8 @ G 2N7002K_SOT23-3

10mil VIN2 VOUT2
0.01U_0603_25V7K
0.01U_0603_25V7K
1 2
1 2
1
15 +1.05VS_PCH +1.05VS
2
3
GPAD R16
TPS22966DPUR_SON14_2X3 J512 J515 D D 100K_0402_5%
2 1 2 1 2 SUSP 2 SUSP
2 1 2 1 G G
2
C2329
10U_0603_6.3V6M
C2328
10U_0603_6.3V6M
@ JUMP_43X79 @ JUMP_43X79 S Q2307 S Q2308

+1.05VS +3VALW 2N7002K_SOT23-3 2N7002K_SOT23-3
1 1
3
@
@
SHORT DEFAULT
2 2
C2315
10U_0603_6.3V6M
C2317
10U_0603_6.3V6M
C2311
10U_0603_6.3V6M
C2313
10U_0603_6.3V6M
1 1 1 1
2 2 2 2 For Intel S3 Power Reduction

4 4

DC/DC Interface
1.0
LA-B012P
A B C D E
5 4 3 2 1
D D
ZZZ
Screw Hole PCB 13P LA-B011P REV0 M/B

DA60013U000
H1 H20 H21 H22 H23

H_2P8N H_2P8N H_2P8N H_2P8X3P3N H_2P8X4P8N
@ @ @ @ @
1
1
H2 H3 H4 H5 H6 H7 H8 H9
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8
@ @ @ @ @ @ @ @
1
1
H10
H_3P0
@
1
C C
H11 H12
H_2P8 H_2P8
@ @
1
H13 H14 H15 H16

H_3P6 H_3P6 H_3P6 H_3P6
@ @ @ @ CPU bracket
1
H17 H18
H_3P3 H_3P3
@ @ VGA stand-off
1
H19
H_3P3
@ NGFF stand-off
1
B B
FD1 FD2 FD3 FD4

@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
1
A A

Screw Hole
Size
Document Number Rev
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
SD034120280 12K_0402_1%
SD034270280 27K_0402_1%
RE5 TOPAZ@
SD034430280 43K_0402_1%
+3VALW_EC
SD034560280 56K_0402_1%
Board ID
SD034750280 75K_0402_1%
2
EMI@ 160K_0402_1% RE3
LE1 +EC_VCCA
Ra 100K_0402_1% SD034100380 100K_0402_1%
+3VALW_EC FBMA-L11-160808-800LMT_0603 SD034160380
SD034130380 130K_0402_1%
1
2 RE327 1 +3VALW_EC 1 2 +EC_VCCA AD_BID0
+3VALW
@ 1 1 2 2
SD034160380 160K_0402_1%
0_0603_1% CE1 CE2 @EMI@ @EMI@ RE5 JET@
1 1 SD034200380 200K_0402_1%
2
0.1U_0402_10V7K 0.1U_0402_10V7K CE5 CE6 +3VLP CE7
D D
2 RE328 1 1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_10V7K Rb RE5 CE8
+3VLP
@ 2 2 1 1
100K_0402_1% 0.1U_0402_10V7K
SD028430380 430K_0402_1%
0_0603_5% 2 2
ECAGND
UMA@ SD034150280 15K_0402_1%
ECAGND <44>
1
130K_0402_1% SD034330280 33K_0402_1%
PLT_RST#
SD034130380
1 SD028200280 20K_0402_1%
111
125
CE36 ESD@
22
33
96
67
9
UE1
0.047U_0402_16V4Z
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
2
Place CC30 PCH_DSW_EN 1 21 KB_LED_PWM +3VS

close to RC51.1 <28> PCH_DSW_EN
KB_RST# 2 GATEA20/GPIO00 GPIO0F 23 BEEP#
KB_LED_PWM <27>
<11> KB_RST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# <22>
SERIRQ USB_EN#
<11> SERIRQ 4 SERIRQ GPIO12 27 USB_EN# <24,25> 2 1
LPC_LFRAME# ACOFF TP_CLK
<9> LPC_LFRAME# 5 LPC_FRAME# ACOFF/GPIO13 ACOFF <45>
LPC_LAD3 4.7K_0402_5% RE9
<9> LPC_LAD3 7 LPC_AD3 2 1 100P_0402_50V8J ECAGND 2 1
@EMI@ @EMI@ LPC_LAD2 PWM Output CE9 TP_DATA
<9> LPC_LAD2 8 LPC_AD2 63
CE12 R2354 LPC_LAD1 BATT_TEMP 4.7K_0402_5% RE10
<9> LPC_LAD1 10 LPC_AD1 BATT_TEMP/GPIO38 64 BATT_TEMP <44,45>
0.1U_0402_10V7K 0_0402_5% LPC_LAD0 LPC & MISC VCIN2_PH
2 1 1 2 <9> LPC_LAD0 LPC_AD0 GPIO39 65 VCIN2_PH <44>
ADP_I
12 ADP_I/GPIO3A 66 ADP_I <44,45> 2 1
CLK_PCI_LPC AD Input VCIN0_PH2 VCIN0_PH2 <27>
<9> CLK_PCI_LPC 13 CLK_PCI_EC GPIO3B 75
PLT_RST# AD_BID0
2 1 47K_0402_5% <10,21,26,34,6> PLT_RST# 37 PCIRST#/GPIO05 GPIO42 76
+3VALW_EC RE8 EC_RST# PANEL_BKLEN PANEL_BKLEN <10> AOAC@
EC_SCI# 20 EC_RST# IMON/GPIO43 RE7
2 1 <11> EC_SCI# 38 EC_SCII#/GPIO0E
CE11 0.1U_0402_10V7K PTP_DIS# 0_0402_5%
<27> PTP_DIS# GPIO1D 68 EN_INVPWR
DAC_BRIG/GPIO3C 70 EN_INVPWR <31>
EN_DFAN1
+3VALW_EC EN_DFAN1/GPIO3D 71 EN_DFAN1 <27>
DA Output EC_ENVDD
55 IREF/GPIO3E 72 EC_ENVDD <31>
KSI0 LCD_TEST
56 KSI0/GPIO30 CHGVADJ/GPIO3F LCD_TEST <31>
KSI1
@ KSI[0..7] KSI2 57 KSI1/GPIO31
1 2 <27> KSI[0..7] 58 KSI2/GPIO32 83
EC_LID_OUT# KSI3 EC_MUTE#
KSO[0..16] 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 EC_MUTE# <22>
RE73 10K_0402_5% KSI4 SIO_SLP_S4# VR_ON
1 2 <27> KSO[0..16] 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 SIO_SLP_S4# <10>
LID_SW# KSI5 AOAC_WLAN 1 VR_ON
61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 AOAC_WLAN <26>
C RE71 10K_0402_5% KSI6 PS2 Interface SYS_PWROK CE34 ESD@ C
62 KSI6/GPIO36 EAPD/GPIO4D 87 SYS_PWROK <10,6>
KSI7 TP_CLK TP_CLK <27> VCCST_PG_EC
+3VS_WLAN_NGFF KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA 0.1U_0402_10V7K
40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <27> 2
KSO1
KSO2 41 KSO1/GPIO21
KSO2/GPIO22
2
1 2 WLAN_WAKE# KSO3 42 97 SUSACK# Place CE34
43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 SUSACK# <10>
RE72 10K_0402_5% KSO4 WOL_EN
2
KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN
WOL_EN <21> between DE1 and RE12
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
ME_EN <8>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <44>
DE1
+3VALW_EC KSO7/GPIO27 SPI Device Interface
KSO8 47 VCCST_PG_EC
KSO9 48 KSO8/GPIO28 119 EC_TP_INT# @ESD@
KSO9/GPIO29 SPIDI/GPIO5B EC_TP_INT# <27> 1
+3VALW
1
RP36 KSO10 49 120 PTP_KBBL# CE35 ESD@
5 4 50 KSO10/GPIO2A SPIDO/GPIO5C 126 PTP_KBBL# <27>
EC_SMB_CK1 KSO11 SPI Flash ROM RTC_DIS
RTC_DIS <8>
1
6 3 EC_SMB_DA1 KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 220P_0402_50V8J L03ESDL5V0CG3-2_SOT-523-3
7 2 EC_SMB_CK2 KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A 2
8 1 EC_SMB_DA2 KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73 ERP_LOT6
81 KSO15/GPIO2F ENBKL/GPIO40 74 ERP_LOT6 <44> Place CE35
2.2K_0804_8P4R_5% KSO16 WAKE_PCH# Place DE1 close to UE1
TP_EN 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 SIO_SLP_S0#
WAKE_PCH# <11> between DE1 and UE1
<27> TP_EN KSO17/GPIO49 FSTCHG/GPIO50 90 SIO_SLP_S0# <10>
WLAN_WAKE#
BATT_CHG_LED#/GPIO52 91 WLAN_WAKE# <26>
CAPS_LED
77 CAPS_LED#/GPIO53 92 CAPS_LED <27>
EC_SMB_CK1 GPIO BATT_CHG_LED#
<44,45> EC_SMB_CK1 78 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 93 BATT_CHG_LED# <25>
EC_SMB_DA1 BATT_LOW_LED# BATT_LOW_LED# <25>
<44,45> EC_SMB_DA1 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95
Reserve for ESD EC_SMB_CK2 SM Bus SYSON
<33,35,9> EC_SMB_CK2 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 1 2 SYSON <48,49>
EC_SMB_DA2 VR_ON_EC @ VR_ON
<33,35,9> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 2 1 VR_ON <13,50>
@ 1
PM_SLP_S4#/GPIO59 PCH_DPWROK <10>
2
2 1 SIO_SLP_S3# 0_0402_1% RE37 RE12 0_0402_5% @
RE1 CE26
CE27 ESD@ SIO_SLP_S3# 6 100 EC_RSMRST# 10K_0402_5% 0.1U_0402_10V7K
<10> SIO_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <10> 2
0.1U_0402_10V7K SIO_SLP_S5# EC_LID_OUT#
<10> SIO_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <11>
2
EC_SMI# 15 102 VCIN1_PH
<8> EC_SMI# VCIN1_PH <44>
1
2 1 SIO_SLP_S5# PS_ID 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 VCOUT1_PH RE2
<44> PS_ID 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 VCOUT1_PH <44>
SLP_SUS# VCOUT0_PH# 10K_0402_5%
<10> SLP_SUS# 18 GPIO0B VCOUT0_PH/GPXIOA07 105 VCOUT0_PH# <46>
CE28 ESD@ DGPU_PWROK GPO BKOFF#
<10,52> DGPU_PWROK 19 GPIO0C BKOFF#/GPXIOA08 106 BKOFF# <31>
0.1U_0402_10V7K TS_EN GPIO PBTN_OUT#
<31> TS_EN PBTN_OUT# <10,6>
1
DBC_EN 25 GPIO0D PBTN_OUT#/GPXIOA09 107 2 1
Please close to EC <31> DBC_EN
FAN_SPEED1 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 ACIN_65W
PCH_PWR_EN <28>
B RE36 43_0402_1% B
<27> FAN_SPEED1 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 ACIN_65W <35>
PCIE_WAKE#
<10,21> PCIE_WAKE# 30 EC_PME#/GPIO15
<26> EC_TX EC_TX
2 1 PCH_PWROK EC_RX 31 EC_TX/GPIO16 110 ACIN ESD@
<26> EC_RX 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 ACIN <10,35,44,45> 1 2
PCH_PWROK EC_ON LID_SW#
<10> PCH_PWROK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <46>
RE18 ME_SUS_PWR_ACK ON/OFFBTN# CE30 0.1U_0402_10V7K
<10> ME_SUS_PWR_ACK 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 ON/OFFBTN# <27>
10K_0402_5% RUNPWROK GPI LID_SW# ESD@
<6> RUNPWROK NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 LID_SW# <25> 1 2
SUSP# PCH_PWROK
SUSP#/GPXIOD05 117 SUSP# <28,47,48>
65W#/90W CE31 1000P_0402_50V7K
GPXIOD06 118 1 65W#/90W
2 <44>
PECI_KB9012 ESD@
122 PECI_KB9012/GPXIOD07
AGND/AGND PECI_EC <6> 1 2
+1.05V_PGOOD SYS_PWROK
<48> +1.05V_PGOOD 123 XCLKI/GPIO5D 124
VCCST_PG_EC +V18R RE43 CE32 1000P_0402_50V7K
GND/GND
GND/GND
GND/GND
GND/GND
<13> VCCST_PG_EC XCLKO/GPIO5E V18R

1 43_0402_1% Reserve for abnormal shutdown
GND0
FAN_SPEED1 CE16
1 4.7U_0805_10V4Z 1 2 EC_RSMRST#
2 <46> EC_SPOK
CE29 KB9012QF-A4_LQFP128_14X14 DE3 RB751V-40_SOD323-2
11
24
35
94
113
69
220P_0402_50V8J LE2 1 2 PCH_PWROK Place CE30,CE31,CE32 close to UE1

2 ECAGND 2 1 DE4 RB751V-40_SOD323-2
FBMA-L11-160808-800LMT_0603
Please close to EC 20mil

+3VS
0.1U_0402_10V7K
<50> VR_HOT#
VR_HOT# 1 ME_FWP PCH has internal 20K PD. CE18
CE15
ACIN 2 1 100P_0402_50V8J
1
(suspend power rail)

@
RE44
0_0402_1%
2 KB9012A3 change to ME_EN
5
1
KB9012A4 SA00004OB30 @
2
UE2 RE326
P
<44,6> H_PROCHOT# H_PROCHOT# 4 2 VCOUT1_PH 1K_0402_5%

Y A
NC
2
A SN74LVC1G06DCKR_SC70-5
1 RE47 A
1
100K_0402_5%
CE19
47P_0402_50V8J
1

EC ENE-KB9012
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
+LCDVDD +3VS
UX4
1 5
+3VS OUT IN
RX10
2
GND
LCD PWR CTRL
1 2 3 4 ENVDD_R
10K_0402_5% OC EN
SY6288C20AAC_SOT23-5 eDP Connector

D D
JEDP
0.1U_0402_16V7K 2 1 C4312 EDP_TX0_C 1
<6> EDP_TX0 2 1 C4311 EDP_TX0#_C 2 1 41
0.1U_0402_16V7K
+LCDVDD +LCDVDD_CONN DX1 <6> EDP_TX0# 3 2 G1 42
+3VS 2 1 DISPOFF# 0.1U_0402_16V7K 2 1 C4314 EDP_TX1_C 4 3 G2 43
W=60mils <30> BKOFF# <6> EDP_TX1 2 1 C4313 EDP_TX1#_C 5 4 G3 44
UX1 0.1U_0402_16V7K
<6> EDP_TX1# 5 G4
1
W=60mils 1 1 2 6 45
5 VOUT FBMA-L11-201209-221LMA30T_0805 RB751V-40_SOD323-2 0.1U_0402_16V7K 2 1 C4321 EDP_AUX_C 7 6 G5 46
VIN 10K_0402_5% <6> EDP_AUX 7 G6
LX1 <6> EDP_AUX# 0.1U_0402_16V7K 2 1 C4322 EDP_AUX#_C 8
RX9 8
0.1U_0402_10V7K
CX11
4.7U_0805_10V4Z
CX8
1 2 9
4 GND EDP_CPU_HPD 10 9
1 1 1 <10> EDP_CPU_HPD
2
SS 10
0.1U_0402_10V7K
CX9
CX7 @ 11
+VDD_TOUCH 11
4.7U_0805_10V4Z 3 12
2 EN USB20_TOUCH_N5 13 12
2 APL3512ABI-TRG_SOT23-5 2 2 USB20_TOUCH_P5 14 13
@ 15 14
@ 1 RX37 2 0_0402_5% I2C1_SDA_PNL_R 16 15
<11> I2C1_SDA_PNL 1 RX38 2 0_0402_5% I2C1_SCL_PNL_R 17 16
@
2 1 <11> I2C1_SCL_PNL 18 17
@ ENVDD_R
<10> ENVDD_PCH WCM-2012HS-900T_4P 19 18
RX7 0_0402_1% TS_RST#
2 1 4 3 <10> TS_RST# 20 19
<30> EC_ENVDD USB20_CAM_P7_R
<12> USB20_CAM_P7 4 3 21 20
RX8 @ 0_0402_5% TS_INT#
<11>1 TS_INT# 2 22 21
Css Tss TS_EN @ TS_EN_R
1 2 USB20_CAM_N7_R RX25 0_0402_1% DBC_EN_R 23 22
<12> USB20_CAM_N7 1 2 24 23
0.1uF 100mS LX6 24
W=60mils 25
10nF 10mS SS table EMI@
+LCDVDD_CONN
+VDD_TOUCH
26 25
26
USB20_CAM_P7_R 27
1 2 USB20_CAM_N7_R 28 27
1nF 1mS 28
RX22 0_0402_5% 29
+3VS_CAM 29
Open or 1mS @EMI@ MIC_CLK 30
1 2 <22> MIC_CLK 31 30
tied to 31
RX21 0_0402_5% MIC_DATA 32
VIN <22> MIC_DATA
LCD_TEST 33 32
@EMI@ <30> LCD_TEST
34 33
35 34
C +3VS 35 C
USB20_TOUCH_N5 36
<12> USB20_TOUCH_N5 <10,6> EDP_BIA_PWM 37 36
DISPOFF#
USB20_TOUCH_P5 38 37
<12> USB20_TOUCH_P5 38
1
39
+INV_PWR_SRC 39
RX26 40
40
3
100K_0402_5% W=60mils
STARC_107K40-000001-G2
CONN@
2
@ESD@
LCD backlight PWR CTRL
PESD5V0U2BT_SOT23-3
DX2
QX2
60mil 60mil
1
SI3457CDV-T1-GE3_TSOP6
+INV_PWR_SRC +INV_PWR_SRC
B+ 6 +3VS +LCDVDD_CONN
5
2
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0805_10V6K
4 1
S
1 1 1 1
1000P_0402_50V7K
CX4
100K_0402_5%
RX2
CX1
CX2
CX3
1
CX5 +VDD_TOUCH
G
1
0.1U_0603_25V7K
3
2 2 2 2
RX35 1 @ 2 100K_0402_5% TS_INT#
2
2
PWR_SRC_ON RX24 1 @ 2 100K_0402_5% TS_RST#

Place close to JEDP
1
B+ +INV_PWR_SRC
RX3
100K_0402_5% J520 @
1 2
1 2
2
JUMP_43X39
B B
1
D DBC_EN 1 @ 2 DBC_EN_R
2 <30> DBC_EN RX23 0_0402_1%
<30> EN_INVPWR QX1
G 2N7002KW_SOT323-3
1
S @
* Touch Screen Panel
3
1
+3VS +5VS RX36

RX41 0_0402_5%
100K_0402_5%
2
+V_TS +VDD_TOUCH
1
1
2
@ RX30 RX29 2 RX28 1

0_0603_5% 0_0603_1%
@ 0_0603_1% @
+V_TS
2
+VDD_TOUCH
+VDD_TOUCH
UX3
Webcam PWR CTRL 5 VOUT
1
+VDD_TOUCH
VIN
0.1U_0402_10V7K
CX50
4.7U_0805_10V4Z
CX49
1
2 1 1
@1 4 GND @ RX39 RX40
+3VS +3VS_CAM SS @
1 10K_0402_5% 10K_0402_5%
0.1U_0402_10V7K
CX52
CX51 @ 3
EN
2
4.7U_0805_10V4Z 2 2
2
2 APL3512ABI-TRG_SOT23-5
G
1 2 2 @ I2C1_SDA_PNL 6 1 I2C1_SDA_PNL_R
S
@ QX6B
5
RX27 DMN66D0LDW-7_SOT363-6
0_0603_1%
G
<30> TS_EN 3 4
I2C1_SCL_PNL I2C1_SCL_PNL_R
S
QX6A
A Css Tss A
0.1uF 100mS
10nF 10mS SS table
1nF 1mS
Open or 1mS
tied to
VIN Security Classification Compal Secret Data Compal Electronics, Inc.
eDP / webcam / TouchScreen
1.0
LA-B012P
5 4 3 2 1
A B C D E F G H
SATA HDD Connector

+3VS
US2 US2 @ US2 @ JHDD

SATA_PRX_DTX_P0 1
SATA_PRX_DTX_N0 2 1
3 2
SATA_PTX_DRX_N0 4 3
1 4 1
SATA_PTX_DRX_P0 5
5
0.01U_0402_16V7K
0.1U_0402_25V6K
SN75LVCP601RTJR PI3EQX6741STZDEX PS8520CTQFN20GTR2-A1 6
RS8 1 @ 2 0_0402_5% JHDD_P10 7 6
1 1 <11> DEVSLP0 7
2
SA00003ZX00 SA00004H100 SA00005U300 FFS_INT2_CONN 8
8
4.7K_0402_5%
RS33
4.7K_0402_5%
RS34
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
9
9
1
CS42
CS27
@ +5V_HDD
10
2 2 10
RS25
RS26
RS27
RS28
11
@ @ 12 GND
1
+3VS GND
E&T_4260K-F10N-00L
2
US2 CONN@
RS19 1 2 0_0402_5% 7 6 DEW2
EN VDD 16 DEW1
CS37 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P0_R 1 VDD
<8> SATA_PTX_DRX_P0_C A_INp
<8> SATA_PTX_DRX_N0_C CS36 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0_R 2 10
A_INn NC 20 HDD_REXT_SATA0
CS35 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P0_RC 5 REXT
<8> SATA_PRX_DTX_P0_C B_OUTp
CS33 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N0_RC 4 9 HDD_A0_PRE0
<8> SATA_PRX_DTX_N0_C B_OUTn A_PRE0 8 HDD_B0_PRE0
+3VS RS29 1
RS30 1
@
@
2 0_0402_5%
2 0_0402_5%
HDD_B0_PRE1
HDD_A0_PRE1
17
19 B_PRE1
A_PRE1
B_PRE0
A_OUTp
15
14
SATA_PTX_DRX_P0_RC CS30 1
SATA_PTX_DRX_N0_RC CS32 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
+5V_HDD Source
RS20 1 @ 2 0_0402_5% 18 A_OUTn
3 TEST 11 SATA_PRX_DTX_P0_R CS34 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P0
RS22 1 @ 2 0_0402_5% HDD_B0_EQ 13 GND B_INp 12 SATA_PRX_DTX_N0_R CS31 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N0 +5V_HDD @ +5VS
21 GND B_INn JP13
EPAD 1 2
PS8520BTQFN20GTR2_TQFN20_4X4 1 2 +5V_HDD
@ JUMP_43X79
+3VS
1000P_0402_50V7K
0.1U_0402_25V6K
SHORT DEFAULT
10U_0805_10V6K
1 1 1
RS38 1 @ 2 0_0402_5% CS5 CS6 CS7
2 2
HDD_B0_EQ RS37 1 2 0_0402_5% 2 2 2
DEW2 RS35 1 2 4.7K_0402_5%
DEW1 RS36 1 2 4.7K_0402_5%
Pin 20: Pin 9: HDD_B0_PRE0 RS21 1 @ 2 0_0402_5%

PARADE PS8250B: PARADE PS8250B: HDD_B0_PRE1 RS18 1 @ 2 0_0402_5%
Depop RS26 Depop RS24.
HDD_A0_PRE1 RS23 1 @ 2 0_0402_5%
PERICOM PI3EQX6741ST: PERICOM PI3EQX6741ST:
HDD_A0_PRE0 RS24 1 2 2K_0402_5%
Pop RS26 Depop RS24
HDD_REXT_SATA0 RS31 1 @ 2 5.1K_0402_1%
ASMEDIA ASM1466: ASMEDIA ASM1466:
Pop RS26 Pop RS24 to pull down
3 3
+3VS
Free Fall Sensor
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
1 1
+5VS
CS43
CS44
FFS@ FFS@
1
2 2 +3VS
US3
LNG3DM @ RS32
10 100K_0402_5%~D
RES
2
G
1 13 FFS@ FFS@
2
14 VDD_IO RES 15
VDD RES 16 FFS_INT2 3 1 1 2 FFS_INT2_CONN
FFS_INT1 11 RES DS1 SDM10U45-7_SOD523-2~D
D
<10> FFS_INT1 9 INT 1 5
FFS_INT2
<11> FFS_INT2 INT 2 GND 12
GND QS1
7 SSM3K7002FU_SC70-3~D
6 SDO/SA0
<17,18,6,9> DDR_XDP_WLAN_TP_SMBDAT 4 SDA / SDI / SDO
<17,18,6,9> DDR_XDP_WLAN_TP_SMBCLK SCL/SPC 2
8 NC 3
CS NC
FFS_INT1 connect to PCH GPIO & EC LNG3DMTR_LGA16_3X3~D
FFS@
discuss with BIOS to use which pin
4 4

HDD
1.0
LA-B012P
A B C D E F G H
5 4 3 2 1
D D
Fintek thermal sensor

placed near by TOP DDR3
+3VS +3VS
1
R2448
U2407 10K_0402_5%
@
C C
2
1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 <30,35,9>
REMOTE1+ 2 9 EC_SMB_DA2
DP1 SMDATA EC_SMB_DA2 <30,35,9>
1
C2498 REMOTE1- 3 8
0.1U_0402_10V6K DN1 ALERT#
REMOTE2+ 4 7 R2450 1 @ 2
2 DP2/DN3 THERM# MAINPWON
0_0402_5%
REMOTE2- 5 6
DN2/DP3 GND
F75303M_MSOP10
Address 1001_101xb
2nd source
SA000029210-->EMC1403-2-AIZL-TR
REMOTE1,2 (+/-) :
REMOTE1+ BOTTOM DDR3
Close U2407 Trace width/space:10/10 mil
1
REMOTE1+ C
1 @ C2500 2 Q2407 Trace length:<8"
2200P_0402_25V7K B MMST3904-7-F_SOT323-3
2
C2502 E
3
2200P_0402_25V7K REMOTE1-
2 REMOTE1-
REMOTE2+
1
REMOTE2+ BOTTOM CPU
C2504
1
1
B B
2200P_0402_25V7K C
2 REMOTE2- @ C2505 2 Q2408
2200P_0402_25V7K B MMST3904-7-F_SOT323-3
2
E
3
REMOTE2-
A A

Thermal Sensor
1.0
5 4 3 2 1
1 2 3 4 5
@
UV1A
A A
<12> PEG_CTX_GRX_P0 PEG_CTX_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0 0.1U_0402_10V7K 2 1 CV1 DIS@ PEG_CRX_GTX_P0 PEG_CRX_GTX_P0 <12>
PEG_CTX_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0 0.1U_0402_10V7K 2 1 CV2 DIS@ PEG_CRX_GTX_N0
<12> PEG_CTX_GRX_N0 PCIE_RX0N PCIE_TX0N PEG_CRX_GTX_N0 <12>
PEG_CTX_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 0.1U_0402_10V7K 2 1 CV3 DIS@ PEG_CRX_GTX_P1 PEG_CRX_GTX_P1 <12>
<12> PEG_CTX_GRX_P1 PCIE_RX1P PCIE_TX1P
PEG_CTX_GRX_N1 AD28 AF28 PCIE_CRX_C_GTX_N1 0.1U_0402_10V7K 2 1 CV4 DIS@ PEG_CRX_GTX_N1 PEG_CRX_GTX_N1 <12>
<12> PEG_CTX_GRX_N1 PCIE_RX1N PCIE_TX1N
PEG_CTX_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 0.1U_0402_10V7K 2 1 CV5 DIS@ PEG_CRX_GTX_P2 PEG_CRX_GTX_P2 <12>
<12> PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2 0.1U_0402_10V7K 2 1 CV6 DIS@ PEG_CRX_GTX_N2
PEG_CTX_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 0.1U_0402_10V7K 2 1 CV7 DIS@ PEG_CRX_GTX_P3 PEG_CRX_GTX_P3 <12>
<12> PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3 0.1U_0402_10V7K 2 1 CV8 DIS@ PEG_CRX_GTX_N3
No Use GPU Display Port outpud
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25 @
PCIE_RX4N PCIE_TX4N UV1F
UV1 TOPAZ@ AA29 Y23

Y28 PCIE_RX5P PCIE_TX5P Y24 +VGA_CORE
PCIE_RX5N PCIE_TX5N AB11
VARY_BL AB12
Y30
PCIE_RX6P PCIE_TX6P
AB27 DIGON TOPAZ
W31 AB26
PCIE_RX6N PCIE_TX6N
TOPAZ XT S3 FCBGA 631P GPU 0FD
SA000079N0L W29 Y27 AL15
V28 PCIE_RX7P PCIE_TX7P Y26 TXCAP_DPA3P AK14
PCIE_RX7N PCIE_TX7N TXCAM_DPA3N
B B
AH16
UV1 JET@ V30 W24 TX0P_DPA2P AJ15
U31 NC#V30 NC#W24 W23 TX0M_DPA2N
NC#U31 NC#W23 AL17
TX1P_DPA1P AK16
U29 V27 TX1M_DPA1N
T28 NC#U29 NC#V27 U26 AH18
NC#T28 NC#U26 TX2P_DPA0P AJ17
JET XT S3 FCBGA 631P GPU 0FD TX2M_DPA0N
PCI EXPRESS INTERFACE

SA00007A50L T30 U24 AL19
R31 NC#T30 NC#U24 U23 NC_TXOUT_L3P AK18
NC#R31 NC#U23 NC_TXOUT_L3N
R29 T26 TMDP

P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 AH20
TXCBP_DPB3P AJ19
P30 T24 TXCBM_DPB3N
N31 NC#P30 NC#T24 T23 AL21
NC#N31 NC#T23 TX3P_DPB2P AK20
TX3M_DPB2N
N29 P27 AH22
M28 NC#N29 NC#P27 P26 TX4P_DPB1P AJ21
NC#M28 NC#P26 TX4M_DPB1N
AL23
M30 P24 TX5P_DPB0P AK22
L31 NC#M30 NC#P24 P23 TX5M_DPB0N
NC#L31 NC#P23 AK24
NC_TXOUT_U3P AJ23
L29 M27 NC_TXOUT_U3N
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
2160856030-A0_FCBGA631
C ? C
CLOCK
CLK_PEG_VGA AK30
<9> CLK_PEG_VGA PCIE_REFCLKP
CLK_PEG_VGA# AK32
<9> CLK_PEG_VGA# PCIE_REFCLKN +VGA_PCIE
CALIBRATION
Y22 RV1 1 DIS@ 2 1.69K_0402_1%
PCIE_CALR_TX
RV2 1 DIS@ 2 1K_0402_1% N10 AA22 RV3 1 DIS@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
PLT_RST_VGA# AL27
PERSTB
2160856030-A0_FCBGA631
+3VGS
UV2 DIS@
5
PLT_RST# 2
P
<10,21,26,30,6> PLT_RST# B 4 PLT_RST_VGA#

DGPU_HOLD_RST# 1 Y
<10> DGPU_HOLD_RST# A
G
1
3
RV4
100K_0402_5%
D D
DIS@
2
MC74VHC1G08DFT2G_SC70-5

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_PCIE/DP
Custom 1.0
1 2 3 4 5
1 2 3 4 5
+3VGS
@
UV1B
Resistor Divider Lookup Lable +1.8VGS
U? PS_0[3:1]=001 Strap Name :
R_pu (ohm) R_pd (ohm) Bitd [3:1] PS_0[5:4]=11
1
RV5 RV6 AF2 DIS@
PS_0[1] ROM_CONFIG[0]
NC#AF2
5
45.3K_0402_1% 45.3K_0402_1% AF4 NC 4.75k 000 RV8 PS_0[2] ROM_CONFIG[1]
G
NC#AF4 8.45K_0402_1%
DIS@ DIS@ @ 1 N9 AG3 8.45k 2k 001 PS_0[3] ROM_CONFIG[2]
T201
2
@ 1 L9 DBG_DATA16 NC#AG3 AG5 PS_0
T202 DBG_DATA15 NC#AG5
3 4 VGA_SMB_DA3 @ 1 AE9 4.53k 2k
DPA 010 PS_0[4] N/A
S
<30,33,9> EC_SMB_DA2 T203 DBG_DATA14
1
@ 1 Y11 AH3
D
1
0.68U_0402_10V
T204 DBG_DATA13 NC#AH3
QV1B @ 1 AE8 AH1 6.98k 4.99k DIS@
T205 DBG_DATA12 NC#AH1 011 PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
2
DMN66D0LDW-7 2N SOT363-6 @ 1 AD9 CV29 RV9
G
T206 DBG_DATA11
DIS@ @ 1 AC10 AK3 4.53k 4.99k 100 2K_0402_1%
T207 DBG_DATA10 NC#AK3 2
@ 1 AD7 AK1 @
T208
2
@ 1 AC8 DBG_DATA9 NC#AK1
A
6 1 VGA_SMB_CK3
T209
@ 1 AC7 DBG_DATA8 DVO
AK5
3.24k 5.62k 101 A
S
<30,33,9> EC_SMB_CK2 T210 DBG_DATA7 NC#AK5
@ 1 AB9 AM3
D
QV1A
T211
@ 1 AB8 DBG_DATA6 NC#AM3 3.4k 10k 110
T212 DBG_DATA5
DMN66D0LDW-7 2N SOT363-6 @ 1 AB7 AK6
DIS@
T213
@ 1 AB4 DBG_DATA4 NC#AK6 AM5
4.75k NC 111
T214 DBG_DATA3 NC#AM5
@ 1 AB2
T215
@ 1 Y8 DBG_DATA2 DPB
AJ7
0402 1% resistors are equired
T216
@ 1 Y7 DBG_DATA1 NC#AJ7 AH6 +1.8VGS Strap Name :
+3VGS T217 DBG_DATA0 NC#AH6 PS_1[3:1]=000
DIS@ AK8 PS_1[5:4]=11 PS_1[1] STRAP_BIF_GEN3_EN_A
RV146 NC#AK8
1
+3VGS AL7
1 2 THM_ALERT# NC#AL7 @
Capacitor Divider Lookup Lable RV11
PS_1[2] TRAP_BIF_CLK_PM_EN
4.7K_0402_5% W6 8.45K_0402_1% PS_1[3] N/A
NC#W6
2
DIS@ V6
Cap (nF) Bitd [5:4]
2
RV58 NC#V6 V4 PS_1
+3VGS 4.7K_0402_5% AC6 NC#V4 U5
PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
NC#AC5 NC#U5
1
AC5
680nF 00 1 PS_1[5] STRAP_TX_DEEMPH_EN
0.68U_0402_10V
1000P_0402_50V7K NC#AC6 W3 DIS@
1
@ UV3 AA5 NC#W3 V2 CV28 RV12

1 2 VGA_DPLUS CV9 DIS@ 1 2 AA6 NC#AA5 NC#V2 82nF 01 4.75K_0402_1%
DPC
VDD1 D+ NC#AA6 Y4 @ 2
10nF 10
2
DIS@ THM_ALERT# 6 3 VGA_DMINUS +1.8VGS NC#Y4 W5
1 ALERT# D- NC#W5
CV10 NC 11
0.1U_0402_16V4Z 4 8 VGA_SMB_CK3 RV82 2 TOPAZ@1
TOPAZ@ 4.7K_0402_5% BP_0 U1 AA3 PLL_Analog_out
THERM# SCLK @ 1FB_VDDCI W1 NC#U1 NC#AA3 Y2
T222 NC#W1 NC#Y2
1
2 5 7 VGA_SMB_DA3 RV81 2 TOPAZ@1
TOPAZ@ 4.7K_0402_5% BP_1 U3
GND SDATA Y6 NC#U3 J8 RV83
@ 1PLL_Analog_in AA1 NC#Y6 NC#J8 16.2K_0402_1% +1.8VGS
ADM1032ARMZ_MSOP8
T221 NC#AA1 TOPAZ@
PS_2[3:1]=000 Strap Name :
PS_2[5:4]=00
1
@
PS_2[1] N/A
I2C RV28 PS_2[2] N/A
8.45K_0402_1%
@ 1 R1 PS_2[3] STRAP_BIOS_ROM_EN
T223
2
@ 1 R3 SCL PS_2
+3VGS +3VGS +3VGS T224 SDA
+1.8VGS PS_2[4] STRAP_BIF_VGA_DIS
1
AM26 1
0.68U_0402_10V
+VGA_CORE R AK26 DIS@
U6
GENERAL PURPOSE I/O AVSSN#AK26 +3VGS CV11 RV13
PS_2[5] N/A
2 GPIO_0
2
CV166 2 JET@ U10 AL25 4.75K_0402_1%

RV71 RV72 T10 GPIO_1 G AJ25 DIS@ 2
2
GPIO_2 AVSSN#AJ25
1
0.1U_0402_10V7K 10K_0402_5% 10K_0402_5% CV170 VGA_SMB_DA3 U8
B
JET@ 1 JET@ JET@ VGA_SMB_CK3 U7 SMBDATA AH24 RV162 B
0.1U_0402_10V7K
1 VGA_AC__BATT T9 SMBCLK B AG25 4.7K_0402_5%
1
JET@ PCC_GPIO_6 T8 GPIO_5_AC_BATT AVSSN#AG25 @

U1 JET@ T7 GPIO_6 DAC1 AH26
2
JET@ 33_0402_5% 1 8 33_0402_5% P10 GPIO_7_BLON HSYNC AJ27 WAKEB
GPU_VID3 RV75 1 2 GPU_VID3_GPIO_15 2 VCCA VCCB 7 RV77 1 2 SVI2_SVD P4 GPIO_8_ROMSO VSYNC
A1 B1 SVI2_SVD <52> GPIO_9_ROMSI
1
GPU_VID1 RV76 1 2 GPU_VID1_GPIO_20 3 6 RV78 1 2 SVI2_SVC P2 +1.8VGS
JET@ 33_0402_5% DIR 5 A2 B2 4
SVI2_SVC <52>
N6 GPIO_10_ROMSCK AD22 RV163
PS_3[3:1]=000 Strap Name :
DIR GND 33_0402_5%JET@ +VGA_CORE N5 GPIO_11 RSET 4.7K_0402_5%
GPIO_12 PS_3[5:4]=11
2
1
N3 AG24 DIS@ PS_3[1] BOARD_CONFIG[0] (Memory ID)
S IC SN74AVC2T45DCTR_SM8 Y9 GPIO_13 AVDD AE22 1G@
2
GPU_VID3 N1 GPIO_14_HPD2 AVSSQ RV15
RV73 RV74 M4 GPIO_15_PWRCNTL_0 AE23 8.45K_0402_1%
PS_3[2] BOARD_CONFIG[1] (Memory ID)
10K_0402_5% 10K_0402_5% THM_ALERT# R6 GPIO_16 VDD1DI AD23
U1 CPN is phase out PS_3[3] BOARD_CONFIG[2] (Memory ID)
1
2
JET@ JET@ W10 GPIO_17_THERMAL_INT VSS1DI PS_3
GPIO19_CTF M2 GPIO_18
GPIO_19_CTF FutureASIC/SEYMOUR/PARK PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
1
GPU_VID1 P8 AM12 1
0.68U_0402_10V
P7 GPIO_20_PWRCNTL_1 CEC_1 1G@
N8 GPIO_21 CV15 RV16
PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
AK10 GPIO_22_ROMCSB AK12 TOPAZ@ 1 RV155 2 0_0402_5% SVI2_SVD 2K_0402_1%
JET@ AM10 GPIO_29 RSVD#AK12 AL11 TOPAZ@ 1 RV156 2 0_0402_5% SVI2_SVT @ 2 RV15 2G@ RV16 2G@
SVI2_SVT <52>
2
+3VGS 10K_0402_5% CV169 10U_0603_6.3V6M 1 2 PEG_CLKREQ#_R N7 GPIO_30 RSVD#AL11 AJ11 TOPAZ@ 1 RV157 2 0_0402_5% SVI2_SVC
<9> PEG_CLKREQ# CLKREQB RSVD#AJ11
RV79 2 1 DIR 2 1
3.3V TO 1.8V LEVEL SHIF RV153 JTAG_TRSTB L6
JTAG_TRSTB
JET@ CV167 0_0402_5% JTAG_TDI L5
2 1 0.1U_0402_10V7K For JET/SUN to support SVI2 reaulator @ JTAG_TCK L3 JTAG_TDI
JTAG_TMS L1 JTAG_TCK AL13 Topaz SVI2 4.53K_0402_1% 4.99K_0402_1%
JET@ DNI for TOPAZ T86 @ 1 JTAG_TDO K4 JTAG_TMS
JTAG_TDO
GENLK_CLK
GENLK_VSYNC
AJ13
TESTEN K7 SD034453180 SD034499180
PAD AF24 TESTEN +1.8VGS +1.8VGS
+VGA_CORE NC#AF24 AG13
SWAPLOCKA AH12
AB13 SWAPLOCKB
GENERICA
2
+3VGS +1.8VGS W8
W9 GENERICB RV84 RV87 Memory ID P/N Vendor Configuration Size
W7 GENERICC AC19 PS_0 10K_0402_5% 10K_0402_5%
RV154 1 @ 2 5.1K_0402_1% RV152 @ AD10 GENERICD PS_0 TOPAZ@ @
2 1 GPIO19_CTF AJ9 GENERICE AD19 PS_1
000 SA000068U0L SAMSUNG K4W2G1646Q-BC1A 1GB
1
@ 1 AL9 NC#AJ9 PS_1
RV17 1 DIS@ 2 1K_0402_1% TESTEN 10K_0402_5% T4930 NC#AL9 AE17 PS_2
PS_2
2
DIS@ AC14 SVI2_SVD

RV151
T218
@ 1 PX_EN AB16 HPD1 AE20 PS_3 SVI2_SVC (default) 001 SA00006H40L HYNIX H5TC2G63FFR-11C 1GB
PX_EN PS_3
10K_0402_5%
C AE19 010 SA00006750L Micron MT41J128M16JT-093G 1GB C

1
TS_A
2
AC16
DBG_VREFG
+3VGS 011 SA000076P0L SAMSUNG K4W4G1646B-HC11 2GB
RV89 RV88
10K_0402_5% 10K_0402_5%
DDC/AUX
(default) 100 SA00006E80L HYNIX H5TC4G63AFR-11C 2GB
1
1 8 JTAG_TRSTB AE6 @ TOPAZ@
2 7 JTAG_TDI PLL/CLOCK DDC1CLK AE5
3 6 JTAG_TMS DDC1DATA
4 5 JTAG_TCK AD2 101 SA000077K0L Micron MT41J256M16HA-093G 2GB
RV20 DIS@ AUX1P AD4 +VGA_CORE
1M_0402_5% RP34 10K_8P4R_5% AUX1N RV60 TOPAZ@
XTALOUT XTALIN @ AC11 1 2
DDC2CLK AC13 0_0603_5%
YV1 DIS@ DDC2DATA
27MHZ_10PF_7V27000050 XTALIN AM28 AD13
XTALOUT AK28 XTALIN AUX2P AD11
RV150 XTALOUT AUX2N
3 1
3 1 1 2 PEG_CLKREQ#_R RV29 1 @ 2 10K_0402_5% AC22 AD20 FB_GND TOPAZ@ 1 RV158 2 0_0402_5% VSSSENSE_VGA <52>
GND GND XO_IN NC#AD20
1
RV59 1 @ 2 10K_0402_5% AB22 AC20 FB_VDDC TOPAZ@ 1 RV159 2 0_0402_5% VCCSENSE_VGA <52>
CV18 CV17 XO_IN2 NC#AC20
4
8.2P_0402_50V8D 2 8.2P_0402_50V8D 10K_0402_5% AE16
2
DIS@ DIS@ @ NC#AE16 AD16

NC#AD16
SEYMOUR/FutureASIC AC1
+1.8VGS VGA_DPLUS T4 DDCVGACLK AC3
LV2 DIS@ VGA_DMINUS T2 DPLUS THERMAL DDCVGADATA
1 2 13mA DMINUS
BLM15BD121SN1D_0402
GPIO28 R5 +VGA_CORE
CV19 2 DIS@
1 10U_0603_6.3V6M +TSVDD AD17 GPIO28_FDO
AC17 TSVDD
CV20 2 DIS@
1 1U_0402_6.3V4Z TSVSS VCCSENSE_VGA @ 1 RV161 2 0_0402_5%
VSSSENSE_VGA @ 1 RV160 2 0_0402_5%
CV21 2 DIS@
1 0.1U_0402_10V6K
2160856030-A0_FCBGA631
+3VGS RV21 1 JET@ 2 10K_0402_5% ?
+3VGS
1
Enable MLPS
1
DIS@
RV147 10K_0402_5%
DIS@ RV148
4.7K_0402_5%
2
VGA_AC__BATT +3VGS
2
D D
QV8A
2
DIS@
3
D
RV91
PACIN# 5 G 10K_0402_5%
S TOPAZ@
DIS@
4
QV8B
6
DMN66D0LDW-7_SOT363-6 RV90
1 2 2 G
D
PCC_GPIO_6 1 2 OCP_L OCP_L <52>
<10,30,44,45> ACIN S
2
RV149 CVT90 1K_0402_5%
1
0_0402_5%
@ 0.1U_0402_10V7K
TOPAZ@
1 TOPAZ@ Peak Current Control (PCC) CKT Security Classification Compal Secret Data
Title
<30> ACIN_65W Reversed Issued Date 2014/01/20 Deciphered Date 2015/01/19 TOPAZ_MSIC
Custom 1.0
1 2 3 4 5
1 2 3 4 5
+3VS TO +3VGS +5VALW +3VS +3VGS

J514 @
1 2
1 2
CV22
10U_0603_6.3V6M
CV23
0.1U_0402_10V7K
JUMP_43X79
1 1
1
QV2 DIS@
DIS@
DIS@
DIS@ AO3413_SOT23-3
RV22 2 2
D
51K_0402_5% 3 1
A A
1
G
2
RV23 DIS@ RV24
DGPU_PWR_EN# 1 2 470_0603_5%
10K_0402_5% @
12
D
CV24
0.1U_0402_10V7K
RV25 1 2 270K_0402_5% 2 QV3 D RV26 @
<10,11,47,51,52> PXS_PWREN
DIS@ G 2N7002K_SOT23-3 1 2 1 2 DGPU_PWR_EN#
S DIS@ QV4 G 10K_0402_5%
CV25
0.1U_0402_10V7K
2N7002K_SOT23-3 S
DIS@
@ 1
3
2
@
2
@
UV1E U?
AA27 A3
370mA (HDMI) No Use GPU Display Port outpud AB24 GND GND A30
+1.35VS_VGA TO +1.35V_MEM_GFX +1.8VGS
1 RV27 2
188mA (Display Port) @
+DP_VDDR UV1G U?
AB32
AC24
AC26
GND
GND
GND
GND
GND
GND
AA13
AA16
AB10
AC27 GND GND AB15
B
@ 0_0603_1% AD25 GND GND AB6 B
CV26
CV27
DP POWER NC/DP POWER
AD32 GND GND AC9
1 1 GND GND
AG15 AE11 AE27 AD6
AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
10U_0603_6.3V6M
1U_0402_6.3V4Z
2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
AG18 DP_VDDR#AG17 NC#AF13 AG8 K28 GND GND AH10
DIS@
DIS@
AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
DP_VDDR#AF14 M32 GND GND B12
N25 GND GND B14
N27 GND GND B16
P25 GND GND B18
AG20 AF6 P32 GND GND B20
AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
+1.35VS_VGA +1.35V_MEM_GFX +VGA_PCIE AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
280mA AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
1 RV30 2 +DP_VDDC AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
DP_VDDC#AD14 U27 GND GND B8
@ 0_0603_1% V32 GND GND C1
CV33
CV34
W25 GND GND C32
1 1 GND GND
AG14 AE1 W26 E28
AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
SHORT DEFAULT
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
AM18 DP_VSSR NC#AG6 AH5 GND GND F16
DIS@
DIS@
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
AE14 DP_VSSR NC#AG11 N21 GND GND
GND F8
DP_VSSR P6 GND GND G10
C C
P9 GND GND G27
R12 GND GND G31
AF17 AE10 R15 GND GND G8
DPAB_CALR NC#AE10 R17 GND GND H14
R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
2160856030-A0_FCBGA631 GND GND
? T18 H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
U9 GND GND K6
V13 GND GND
V16 GND
V18 GND
Y10 GND
Y15 GND
Y17 GND
Y20 GND
+1.8VS TO +1.8VGS R11

T11
AA11
GND
GND
GND
VSS_MECH
VSS_MECH
A32
AM1
AM32
M12 GND VSS_MECH
N11 GND
+1.8VS +1.8VGS V11 GND
GND
@ 2160856030-A0_FCBGA631
?
2 1
2MM J9
D D
SHORT DEFAULT

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_Power/GND
Custom 1.0
1 2 3 4 5
1 2 3 4 5
A
+VGA_CORE 10uF 1uF 0.1uF A
VDDC TBD 5 (1@) 10 (2@) 0 @

UV1D +1.8VGS
+1.35V_MEM_GFX
U?
100mA
AM30 +PCIE_PVDD
VDDCI 3.5A 1 3 0 1.5A MEM I/O PCIE_PVDD
PCIE
CV38
CV46
CV39
H13 AB23 1 1 1
H16 VDDR1 NC#AB23 AC23
H19 VDDR1 NC#AC23 AD24
CV43
CV44
CV45
CV40
CV47
CV48
CV41
CV42
CV49
CV50
CV51
CV52
CV53
J10 VDDR1 NC#AD24 AE24
CV174
CV175
CV176
CV177
CV178
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
J23 VDDR1 NC#AE24 AE25 2 2 2
+VGA_PCIE 10uF 1uF 0.1uF J24 VDDR1 NC#AE25 AE26
DIS@
DIS@
DIS@
J9 VDDR1 NC#AE26 AF25
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 K10 VDDR1 NC#AF25 AG26
K23 VDDR1 NC#AG26
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
PCIE_VDDC 2.5A 2 (1@) 5 (1@) 0 K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L12 VDDR1 PCIE_VDDC L25
BIF_VDDC 1.4A 0 1 0 L13 VDDR1 PCIE_VDDC L26
L20 VDDR1 PCIE_VDDC M22 +VGA_PCIE
L21 VDDR1 PCIE_VDDC N22 2.5A
L22 VDDR1 PCIE_VDDC N23
SPLL_VDDC 100mA 1 1 1 VDDR1 PCIE_VDDC N24
CV54
CV55
CV56
CV57
CV58
CV59
CV60
PCIE_VDDC R22
PCIE_VDDC 1 1 1 1 1 1 1
T22
+1.8VGS 13mA LEVEL PCIE_VDDC U22
LV3 DIS@ TRANSLATION PCIE_VDDC V22
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2 +VDD_CT AA20 PCIE_VDDC 2 2 2 2 2 2 2
+1.35V_MEM_GFX 10uF 2.2uF 0.1uF 0.01uF VDD_CT
@
BLM15BD121SN1D_0402 AA21
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
AB20 VDD_CT AA15
CV61
CV62
CV63
B
AB21 VDD_CT CORE VDDC N15 B
1 1 1 VDD_CT VDDC N17
VDDR1 1.5A 3 5 5 5 +3VGS VDDC R13
LV4 DIS@ 25mA I/O VDDC R16
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 1 2 +VDDR3 AA17 VDDC R18
BLM15BD121SN1D_0402 AA18 VDDR3 VDDC Y21
DIS@
DIS@
DIS@
AB17 VDDR3 VDDC T12
CV64
CV65
CV66
AB18 VDDR3 VDDC T15 +VGA_CORE
+1.8VGS 10uF 1uF 0.1uF 1 1 1 VDDR3 VDDC T17 TBD
V12 VDDC T20
Y12 VDDR4 VDDC U13
CV67
CV68
CV69
CV70
CV71
CV72
CV73
CV74
CV75
CV76
CV77
CV78
CV79
CV80
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_10V6K
2 2 2 U12 VDDR4 VDDC U16
PCIE_PVDD 100mA 1 1 1 VDDR4 VDDC 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@
U18
DIS@
DIS@
VDDC V21
VDDC V15
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDDC V17 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MPLL_PVDD 130mA 1 1 1 VDDC
@
V20
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 1 1 1 VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDR4 (300mA) 0 0 0 VDDC
+1.8VGS
LV6 DIS@ 130mA PLL
1 2 +MPLL_PVDD CV168 1U_0402_6.3V4Z
VDD_CT 13mA 1 1 1 BLM15BB221SN1D_2P +VGA_PCIE +BIF_VDDC 1 2
CV81
CV82
CV83
1 1 1
1.4A
R21 +BIF_VDDC 1 @ 2 DIS@
BIF_VDDC U21 RV31 0_0805_1%
+TSVDD 13mA 1 1 1 BIF_VDDC
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
2 2 2 L8
+1.8VGS MPLL_PVDD
DIS@
DIS@
DIS@
C
LV7 DIS@ 75mA +VDDCI DIS@ +VGA_CORE
C
+DP_VDDR 0 0 0 1 2 +SPLL_PVDD
ISOLATED
CORE I/O
3.5A (DDR3) LV25
BLM15BD121SN1D_0402 M13 1 2
CV84
CV85
CV86
H7 VDDCI M15 BLM15BD121SN1D_0402
CV88
CV89
CV90
CV87
1 1 1 SPLL_PVDD VDDCI M16 LV26
+DP_VDDC 0 0 0 VDDCI M17
1 1 1 1
1 2
+VGA_PCIE VDDCI M18 BLM15BD121SN1D_0402
100mA
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 LV8 DIS@ VDDCI M20
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2 +SPLL_VDDC H8 VDDCI M21 2 2 2 2
DIS@
DIS@
DIS@
SPLL_VDDC VDDCI DIS@

BLM15BD121SN1D_0402 N20
CV91
CV92
CV93
DIS@
DIS@
DIS@
DIS@
J7 VDDCI
+3VGS 10uF 1uF 0.1uF 1 1 1 SPLL_PVSS
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2
VDDR3 25mA 0 2 (1@) 1 2160856030-A0_FCBGA631
?
DIS@
DIS@
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_Power
Custom 1.0
1 2 3 4 5
1 2 3 4 5
M_DA[63..0]
<39,40> M_DA[63..0]
M_MA[15..0]
<39,40> M_MA[15..0]
M_DQM[7..0]
<39,40> M_DQM[7..0]
M_DQS[7..0]
<39,40> M_DQS[7..0]
A A
M_DQS#[7..0]
<39,40> M_DQS#[7..0]
@
UV1C U?
GDDR5/DDR3 GDDR5/DDR3
M_DA0 K27 K17 M_MA0
M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M_MA2
M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M_MA4
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M_MA6
+1.35V_MEM_GFX +1.35V_MEM_GFX M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_10
1
1
M_DA11 C28 J14 M_MA8
DIS@ DIS@ M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
RV33 RV32 M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
40.2_0402_1% 40.2_0402_1% M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
2
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2

DQA0_16 MAA1_5/MAA_BA2 M_BA2 <39,40>
+MVREFDA +MVREFSA M_DA17 C25 J16 M_BA0
DQA0_17 MAA1_6/MAA_BA0 M_BA0 <39,40>
M_DA18 E25 L15 M_BA1
DQA0_18 MAA1_7/MAA_BA1 M_BA1 <39,40>
M_DA19 D24 G14 M_MA14
DQA0_19 MAA1_8/MAA_14
1
1 1 M_DA20 E23 L16
MEMORY INTERFACE
DIS@ DIS@ DIS@ DIS@ M_DA21 F23 DQA0_20 MAA1_9/RSVD
RV34 CV94 RV35 CV95 M_DA22 D22 DQA0_21 E32 M_DQM0
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1
2 2 M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
2
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3

M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4
B
M_DA27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 M_DQM5 B
M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6
M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7
M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
M_DA31 C17 DQA0_30 H28 M_DQS0
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4
M_DA36 D14 DQA1_3 EDCA1_0/QSA1_0 D10 M_DQS5
DIS@ DIS@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
RV36 RV37 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
49.9_0402_1% 10_0402_1% M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3
1 2 2 1 DRAM_RST M_DA40 E11 DQA1_7 H27 M_DQS#0
<39,40> DRAM_RST# DQA1_8 DDBIA0_0/QSA0_0B
M_DA41 A11 A27 M_DQS#1
M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
DQA1_10 DDBIA0_2/QSA0_2B
1
1 1 M_DA43 F11 C19 M_DQS#3

DIS@ DIS@ @ M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4
CV96 RV38 CV97 M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5
120P_0402_50V8J 5.1K_0402_1% 68P_0402_50V8J M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
2 2 M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
2
M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B

M_DA49 A7 DQA1_16 L18 VRAM_ODT0
DQA1_17 ADBIA0/ODTA0 VRAM_ODT0 <39>
M_DA50 C7 K16 VRAM_ODT1
DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 <40>
M_DA51 F7
M_DA52 A5 DQA1_19 H26 M_CLK0
DQA1_20 CLKA0 M_CLK0 <39>
M_DA53 E5 H25 M_CLK#0
DQA1_21 CLKA0B M_CLK#0 <39>
M_DA54 C3
M_DA55 E1 DQA1_22 G9 M_CLK1
Place close to GPU (within 25mm) M_DA56 G7 DQA1_23 CLKA1 H9 M_CLK#1
M_CLK1 <40>
DQA1_24 CLKA1B M_CLK#1 <40>
and place componment close to each other M_DA57 G6
DQA1_25
M_DA58 G1 G22 M_RAS#0
DQA1_26 RASA0B M_RAS#0 <39>
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 <40>
M_DA60 J6
M_DA61 J1 DQA1_28 G19 M_CAS#0
C C
DQA1_29 CASA0B M_CAS#0 <39>
M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 <40>
M_DA63 J5
DQA1_31 H22 M_CS#0
CSA0B_0 M_CS#0 <39>
+MVREFDA K26 J22
+MVREFSA J26 MVREFDA CSA0B_1
MVREFSA G13 M_CS#1
CSA1B_0 M_CS#1 <40>
J25 K13
RV39 1 DIS@ 2 120_0402_1% K25 NC#J25 CSA1B_1
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 <39>
J17 M_CKE1
CKEA1 M_CKE1 <40>
G25 M_WE#0
WEA0B M_WE#0 <39>
DRAM_RST L10 H10 M_WE#1
DRAM_RST WEA1B M_WE#1 <40>
RV40 @ 1 2 51.1_0402_1% CV98 @1
@ 2 0.1U_0402_16V4Z K8
RV41 @ 1 2 51.1_0402_1% CV99 @
@1 2 L7 CLKTESTA
0.1U_0402_16V4Z CLKTESTB
Route 50ohms single-ended/100ohm diff and keep short

2160856030-A0_FCBGA631
debug only, for clock observation,if not need, DNI. ?
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_MEM
Custom 1.0
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Lower 32 bits

M_DA[63..0]
<38,40> M_DA[63..0]
M_MA[15..0]
<38,40> M_MA[15..0]
M_DQM[7..0]
<38,40> M_DQM[7..0]
M_DQS[7..0]
<38,40> M_DQS[7..0]
M_DQS#[7..0]
<38,40> M_DQS#[7..0]
+1.35V_MEM_GFX +1.35V_MEM_GFX
A A
1
DIS@ DIS@
RV42 RV43
4.99K_0402_1% UV5 4.99K_0402_1% UV6
2
+FBA_VREF0 M8 E3 M_DA17 +FBA_VREF1 M8 E3 M_DA30
H1 VREFCA DQL0 F7 M_DA23 H1 VREFCA DQL0 F7 M_DA27
VREFDQ DQL1 F2 M_DA21 VREFDQ DQL1 F2 M_DA31
DQL2 DQL2
1
1 M_MA0 N3 F8 M_DA22 1 M_MA0 N3 F8 M_DA24
DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA18 DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA29
RV44 CV100 M_MA2 P3 A1 DQL4 H8 M_DA19 RV45 CV101 M_MA2 P3 A1 DQL4 H8 M_DA26
4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA16 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA28
2 M_MA4 P8 A3 DQL6 H7 M_DA20 2 M_MA4 P8 A3 DQL6 H7 M_DA25
2
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
M_MA6 R8 A5 M_MA6 R8 A5
M_MA7 R2 A6 D7 M_DA5 M_MA7 R2 A6 D7 M_DA8
M_MA8 T8 A7 DQU0 C3 M_DA3 M_MA8 T8 A7 DQU0 C3 M_DA14
M_MA9 R3 A8 DQU1 C8 M_DA4 M_MA9 R3 A8 DQU1 C8 M_DA9
M_MA10 L7 A9 DQU2 C2 M_DA1 M_MA10 L7 A9 DQU2 C2 M_DA12
M_MA11 R7 A10/AP DQU3 A7 M_DA6 M_MA11 R7 A10/AP DQU3 A7 M_DA10
M_MA12 N7 A11 DQU4 A2 M_DA0 M_MA12 N7 A11 DQU4 A2 M_DA15
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA11
M_MA14 T7 A13 DQU6 A3 M_DA2 M_MA14 T7 A13 DQU6 A3 M_DA13
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX
M_BA0 M2 B2 M_BA0 M2 B2
<38,40> M_BA0 BA0 VDD BA0 VDD
M_BA1 N8 D9 M_BA1 N8 D9
M_BA2 M3 G7 M_BA2 M3 G7
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9
B <38> M_CLK0 CK VDD CK VDD B
M_CLK#0 K7 R1 M_CLK#0 K7 R1
<38> M_CLK#0 CK VDD CK VDD
M_CKE0 K9 R9 M_CKE0 K9 R9
<38> M_CKE0 CKE/CKE0 VDD +1.35V_MEM_GFX CKE/CKE0 VDD +1.35V_MEM_GFX
VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1
<38> VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
M_CS#0 L2 A8 M_CS#0 L2 A8
<38> M_CS#0 CS/CS0 VDDQ CS/CS0 VDDQ
M_RAS#0 J3 C1 M_RAS#0 J3 C1
<38> M_RAS#0 RAS VDDQ RAS VDDQ
M_CAS#0 K3 C9 M_CAS#0 K3 C9
<38> M_CAS#0 CAS VDDQ CAS VDDQ
M_WE#0 L3 D2 M_WE#0 L3 D2
<38> M_WE#0 WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS3 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS1 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ
M_DQM2 E7 A9 M_DQM3 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM1 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
M_DQS#2 G3 VSS J2 M_DQS#3 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#1 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9
<38,40> DRAM_RST# RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1
M_CLK0 DIS@ L1 NC/ODT1 VSSQ B9 DIS@ L1 NC/ODT1 VSSQ B9
M_CLK#0 RV46 J9 NC/CS1 VSSQ D1 RV47 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ VSSQ
1
C E8 E8 C
RV48 RV49 VSSQ F9 VSSQ F9
40.2_0402_1% 40.2_0402_1% UV5 VSSQ G1 UV6 VSSQ G1
DIS@ DIS@ VSSQ G9 VSSQ G9
VSSQ VSSQ
2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C FBGA 96P H5TC2G63FFR-11C FBGA 96P
1 256MX16 H5TC4G63AFR-11C FBGA 96P 1G@ 256MX16 H5TC4G63AFR-11C FBGA 96P 1G@
DIS@
CV102 SA00006E80L SA00006E80L
0.01U_0402_16V7K
2 +1.35V_MEM_GFX
2G@ 2G@ +1.35V_MEM_GFX
U1406 side
U1407 side
CV103
CV104
CV105
CV106
CV107
CV108
CV109
CV110
CV111
CV112
CV113
CV114
CV115
CV116
CV117
CV171
CV172
CV118
CV119
CV120
CV121
CV122
CV123
CV124
CV125
CV126
CV127
CV128
CV129
CV130
CV131
CV132
CV173
CV179
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_VRAM
Size Document Number
A Lower Rev
Custom 1.0
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Upper 32 bits
+1.35V_MEM_GFX
+1.35V_MEM_GFX
1
1
DIS@
DIS@ RV51
RV50 4.99K_0402_1% UV8
4.99K_0402_1% UV7
2
A M_DA[63..0] +FBA_VREF3 +FBA_VREF3 M8 E3 M_DA49 A
<38,39> M_DA[63..0]
2
+FBA_VREF2 M8 E3 M_DA38 H1 VREFCA DQL0 F7 M_DA53
M_MA[15..0] H1 VREFCA DQL0 F7 M_DA36 VREFDQ DQL1 F2 M_DA51
<38,39> M_MA[15..0] VREFDQ DQL1 DQL2
1
F2 M_DA37 1 M_MA0 N3 F8 M_DA54
DQL2 A0 DQL3
1
M_DQM[7..0] 1 M_MA0 N3 F8 M_DA35 DIS@ DIS@ M_MA1 P7 H3 M_DA50
<38,39> M_DQM[7..0] A0 DQL3 A1 DQL4
DIS@ DIS@ M_MA1 P7 H3 M_DA39 RV53 CV134 M_MA2 P3 H8 M_DA55
M_DQS[7..0] RV52 CV133 M_MA2 P3 A1 DQL4 H8 M_DA32 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA48
<38,39> M_DQS[7..0] A2 DQL5 2 A3 DQL6
4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 G2 M_DA34 M_MA4 P8 H7 M_DA52
2
M_DQS#[7..0] 2 M_MA4 P8 A3 DQL6 H7 M_DA33 M_MA5 P2 A4 DQL7
<38,39> M_DQS#[7..0]
2
M_MA5 P2 A4 DQL7 M_MA6 R8 A5
M_MA6 R8 A5 M_MA7 R2 A6 D7 M_DA60
M_MA7 R2 A6 D7 M_DA41 M_MA8 T8 A7 DQU0 C3 M_DA59
M_MA8 T8 A7 DQU0 C3 M_DA44 M_MA9 R3 A8 DQU1 C8 M_DA63
M_MA9 R3 A8 DQU1 C8 M_DA43 M_MA10 L7 A9 DQU2 C2 M_DA56
M_MA10 L7 A9 DQU2 C2 M_DA45 M_MA11 R7 A10/AP DQU3 A7 M_DA62
M_MA11 R7 A10/AP DQU3 A7 M_DA42 M_MA12 N7 A11 DQU4 A2 M_DA57
M_MA12 N7 A11 DQU4 A2 M_DA46 M_MA13 T3 A12 DQU5 B8 M_DA61
M_MA13 T3 A12 DQU5 B8 M_DA40 M_MA14 T7 A13 DQU6 A3 M_DA58
M_MA14 T7 A13 DQU6 A3 M_DA47 M_MA15 M7 A14 DQU7
M_MA15 M7 A14 DQU7 A15/BA3 +1.35V_MEM_GFX
A15/BA3 +1.35V_MEM_GFX
M_BA0 M2 B2
M_BA0 M2 B2 M_BA1 N8 BA0 VDD D9
M_BA1 N8 D9 M_BA2 M3 G7
M_BA2 M3 G7 K2
<38,39> M_BA2 BA2 VDD VDD
K2 K8
VDD K8 VDD N1
VDD N1 M_CLK1 J7 VDD N9
M_CLK1 J7 VDD N9 M_CLK#1 K7 CK VDD R1
<38> M_CLK1 CK VDD CK VDD
M_CLK#1 K7 R1 M_CKE1 K9 R9
<38> M_CLK#1 CK VDD CKE/CKE0 VDD +1.35V_MEM_GFX
M_CKE1 K9 R9
<38> M_CKE1 CKE/CKE0 VDD +1.35V_MEM_GFX
VRAM_ODT1 K1 A1
VRAM_ODT1 K1 A1 M_CS#1 L2 ODT/ODT0 VDDQ A8
<38> VRAM_ODT1 ODT/ODT0 VDDQ CS/CS0 VDDQ
M_CS#1 L2 A8 M_RAS#1 J3 C1
B <38> M_CS#1 CS/CS0 VDDQ RAS VDDQ B
M_RAS#1 J3 C1 M_CAS#1 K3 C9
<38> M_RAS#1 RAS VDDQ CAS VDDQ
M_CAS#1 K3 C9 M_WE#1 L3 D2
<38> M_CAS#1 CAS VDDQ WE VDDQ
M_WE#1 L3 D2 E9
<38> M_WE#1 WE VDDQ VDDQ
E9 F1
VDDQ F1 M_DQS6 F3 VDDQ H2
M_DQS4 F3 VDDQ H2 M_DQS7 C7 DQSL VDDQ H9
M_DQS5 C7 DQSL VDDQ H9 DQSU VDDQ
DQSU VDDQ
M_DQM6 E7 A9
M_DQM4 E7 A9 M_DQM7 D3 DML VSS B3
M_DQM5 D3 DML VSS B3 DMU VSS E1
DMU VSS E1 VSS G8
VSS G8 M_DQS#6 G3 VSS J2
M_DQS#4 G3 VSS J2 M_DQS#7 B7 DQSL VSS J8
M_DQS#5 B7 DQSL VSS J8 DQSU VSS M1
DQSU VSS M1 VSS M9
VSS M9 VSS P1
M_CLK1 VSS P1 DRAM_RST# T2 VSS P9
M_CLK#1 DRAM_RST# T2 VSS P9 RESET VSS T1
<38,39> DRAM_RST# RESET VSS VSS
T1 L8 T9
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS
1
1
RV54 RV55 J1 B1
NC/ODT1 VSSQ
1
40.2_0402_1% 40.2_0402_1% J1 B1 DIS@ L1 B9

DIS@ DIS@ DIS@ L1 NC/ODT1 VSSQ B9 RV57 J9 NC/CS1 VSSQ D1
RV56 J9 NC/CS1 VSSQ D1 243_0402_1% L9 NC/CE1 VSSQ D8
2
243_0402_1% L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
2
NCZQ1 VSSQ E2 VSSQ E8
2
VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
1 VSSQ VSSQ
DIS@ G1 UV8 G9
CV135 VSSQ G9 VSSQ
0.01U_0402_16V7K UV7 VSSQ 96-BALL
2 96-BALL SDRAM DDR3
C SDRAM DDR3 H5TC2G63FFR-11C FBGA 96P C
H5TC2G63FFR-11C FBGA 96P 1G@
1G@ 256MX16 H5TC4G63AFR-11C FBGA 96P
256MX16 H5TC4G63AFR-11C FBGA 96P SA00006E80L
SA00006E80L 2G@
2G@
+1.35V_MEM_GFX +1.35V_MEM_GFX
U1408 side U1409 side

CV136
CV137
CV138
CV139
CV140
CV141
CV142
CV143
CV144
CV145
CV146
CV147
CV148
CV149
CV150
CV180
CV181
CV151
CV152
CV153
CV154
CV155
CV156
CV157
CV158
CV159
CV160
CV161
CV162
CV163
CV164
CV165
CV182
CV183
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_VRAM
Size Document Number
A Upper Rev
Custom 1.0
1 2 3 4 5
5 4 3 2 1
D D
Power-Up/Down Sequence
1. All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µs.
2. The external pull ups on the DDC/AUX signals (if applicable) should ramp up
before or after both VDDC and VDD_CT have ramped up.
3. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
4. For power down, reversing the ramp-up sequence is recommended.
C C
PLT_RST#
VDDR3(3.3VGS) AND
PCH GATE
PLT_RST_VGA# PERSTB GPU
PCIE_VDDC(0.95V)
GPIO50 DGPU_HOLD_RST
VDDR1(1.5VGS) GPIO54 DGPU_PWR_EN
TACH0/GPIO17 DGPU_PWROK
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
NOT DGPU_PWR_EN#
PERSTb
+3VS +3VS_VGA
REFCLK MOS 1
B B
Straps Reset +3VS +0.95VS_VGA +1.8VS +1.8VS_VGA

Regulator 2 MOS 5
Straps Valid
B+ +VGA_CORE +1.5VS +1.5VS_VGA
PWM 4 MOS 3
Global ASIC Reset
T4+16clock
CPU part
A A

TOPAZ_NOTE
1.0
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Reserved Page
Document Number Rev
1.0
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Reserved Page
Document Number Rev
1.0
5 4 3 2 1
A B C D
@EMI@
PL6 @ PR11
2.2UH_PCMB053T-2R2MS_5.5A_20% 1 2
1 2 0_0402_5%
EMI@ PL1
VIN PR4 PSID@
FBMJ4516HS720NT_2P 33_0402_5%
ADPIN 1 2 1 3 PSID-3 1 2 PS_ID <30>
S
PQ6 PSID@
FDV301N_G 1N SOT23-3
1000P_0402_50V7K
1000P_0402_50V7K
G
2
1
100K_0402_1%
PJPDC
100P_0402_50V8J
100P_0402_50V8J
PR8
2
1 EMI@ PL4 PSID@ PR3 PSID@
1
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
PR6
2 2 1
PSID@
FBMJ4516HS720NT_2P PSID-2 +5VALW 2.2K_0402_5%
2 3 1 2
2
3 4
2
4 5 10K_0402_1%
+3VALW
1
5
1
1 1 2 C 1
6 PSID-1 2 PQ5 PSID@

GND 7 B
15K_0402_1%
2.2UH_PCMB053T-2R2MS_5.5A_20% MMST3904-7-F_SOT323
GND
2
PL7 @EMI@ E
3
PR9
PSID@
ACES_50299-00501-003
CONN@
PL2
BLM15AG102SN1D_2P
1
PSID 2 1
EMI@
BATT+ EMI@ PL5 BATT++

FBMJ4516HS720NT_2P
1 2
BATT+
EMI@ PL3
FBMJ4516HS720NT_2P
1 2 BATT++
1
1000P_0402_50V7K
0.01U_0402_25V7K
1
PC8
1
EMI@ PC7
PD1 PD2
2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMI@
EMI@ EMI@
3
SMART
Battery:
PBATT BATT_TEMP <30,45>
01.GND1 1
1
2
02.GND2 2
2 2
3 BAT_ALERT PR15 PR16
03.BAT_ALERT 3 4 SYS_PRES 100_0402_5% 10K_0402_1%
4
04.SYS_PRES 5
5 BATT_PRS 1 2 1 2
+3VALW_EC
6 DAT_SMB
05.BATT_PRS 6 7 CLK_SMB
7 8
06.DAT_SMB 8 9 PR18
07.CLK_SMB 9 10 100_0402_5%
GND 11 1 2 EC_SMB_CK1 <30,45>
08.BATT1+ GND
09.BATT2+ LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2 PR20
CONN@ 100_0402_5%
1 2 EC_SMB_DA1 <30,45>
Other component (37.1)

<30,45> ADP_I <45> BATT_I
ADP_I(with selector) Delay adaptor OC H_PROCHOT# PH1 under CPU bottem side :
need near EC side 2ms while hybrid power CPU thermal protection at 93 +/- 3 degree C
2
transition +EC_VCCA +3VALW

PR23 PR35
150K_0402_1% 499K_0402_1% H_PROCHOT# H_PROCHOT# <30,6>
2
1
PR24 @ PR25
12.1K_0402_1% 12.1K_0402_1%
2
PR27 PR36 PR30
1
392K_0402_1% 392K_0402_1% 160K_0402_1%
@ PC13 .1U_0402_16V7K
@ PC17 .1U_0402_16V7K
L2N7002DW1T1G_SC88-6
<30> VCIN0_PH
PQ3A
<30> VCIN1_PH <30> VCIN2_PH 1 2 2

61
31
0.01U_0402_25V7K
1
1
2
1
PQ4A
PQ4B
PC15
115K_0402_1%
115K_0402_1%
2
2
PR26
PR34
3
2 5 3
2
PH1
1
2
VCOUT1_PH <30> 100K_0402_1%_TSM0B104F4251RZ
1
<30> ECAGND
<30> 65W#/90W
Adapter protection: Battery protection: Erp lot6 Circuit VIN

if battery removed, adaptor only, asserts H_PROCHOT# when adaptor is
then trigger the H_PROCHOT#, unplugged, keep low for 10ms
3.3K_1206_5%
keep @ in BOM since battery can not till SW PROCHOT# is issued by EC
1
ERP_LOT6 <30>
be removed by end user
PR5
JRTC CONN@
H_PROCHOT# 1
VIN +3VALW PR7 +RTCBATT 2 1
2
2
ACIN <10,30,35,45>
10K_0402_1%
3 2
1
H_PROCHOT# 1M_0402_1% 3
+3VALW GND
PR28
4
GND
6
10K_0402_1%
PR31 PC16
1
PQ1B
.1U_0402_16V7K
ACES_50271-0020N-001
1
1
PQ2A
PR37
1M_0402_1% 5
3 2
3
PC14 1 2 2 @ PR1
6
.1U_0402_16V7K
4
PQ3B
PQ2B
100K_0402_1%
@ 200K_0402_1%
2
1
1
PQ1A
BATT_PRS 1 2 5 PR10
2
PR29
5 2
100K_0402_1%
10K_0402_1%
PR33 1M_0402_1%
4
1
1
PR2 1
@ PC5
4
1
PR32
1M_0402_1%
2
0.1U_0402_25V6
2
4 4
2

PWR_DCIN/BATT CONN/OTP
1.0
LA-B012P
A B C D
A B C D
CHG_B+
VIN
Iada=0~3.33A(65W)
PR702 EMI@
PQ700 PQ701 0.02_1206_1% PL702 Iada=0~4.62A(90W)
AO4407AL_SO8 AO4423L_SO8 1UH_PCMB053T-1R0MS_7A_20%
8 1 1 8 1 4 1 2
7 2 2 7
6 3 3 6 2 3
10_0402_1%
5600P_0402_25V7K
3.3K_1206_5%
0.022U_0402_25V7K
PR718
5 5
200K_0402_1%
1
2
PC702
PR704
2200P_0402_25V7K
0.1U_0402_25V7K
PC706 @EMI@
EMI@
PR720
PC733
PR717
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
4
4
1 10_0402_1% 1
1
1
@EMI@ PC735
0.1U_0402_25V6
2
1
PC729
PC730
PC731
@EMI@ PC734
PC704
PC703
@
3 2
PC705
PQ702
2
AO4407AL_SO8 BATT+
0.1U_0402_25V6
2
2
+VCHGR
PR725
1 8
150K_0402_1%
PQ706B
2 7
5 3 6
<30> ACOFF
PC708
5
PC707
4 AGATE
4
For DT Mode Place PC735 close to PC4 PC717 PR706
VIN 0.047U_0402_25V7K 0_0402_5%
1 2 BGATE 2 1
1000P_0402_25V8J
2
PC724
CSIP
VSMB
CSIN
1
PR705
1
10K_0402_1%
10_1206_5%
PR719
1 2 DCIN
VIN
232K_0402_1%
PC711 B+
2
1
0.01UF_0402_25V7K PC710 PC739
PR723
1 2 1U_0603_25V6K AGATE 10U_0805_25V6K
1 2
2
PR711
51.1K_0402_1% PC738
1
1 2 ACDET 10U_0805_25V6K
PR727 1K_0402_1% 1 2
PC728 2200P_0402_50V7K PR728 9.09K_0402_1% VSMB 1 2
1 2 1 2 ICOMP PC737
CELL 10U_0805_25V6K
SIR472DP-T1-GE3_POWERPAK8-5
1 2 1 2 VCOMP 1 2
2 2
PR726 PC727 PC736
1
27K_0402_1% 220P_0402_50V8J PU701 10U_0805_25V6K
1 1 2
CELL
DCIN
ADET
VFSW
VCOMP
ICOMP
AGATE
100U_25V_M
+
PC732
PC718
PQ703
PR701 3K_0402_1% PC701 1000P_0402_50V7K 10U_0805_25V6K
1 2 1 2 VFB 8 28 1 2
VFB CSIP 2
9 27 4 PC714
@ PR715 0_0402_5% AMON CSIN 10U_0805_25V6K Near PL701
<30,44> EC_SMB_DA1 1 2 SDA 10 26 PR709 PC721 1 2
@ PR714 0_0402_5% SDA SGATE 2.2_0603_5% 0.22U_0603_25V7K
<30,44> EC_SMB_CK1 1 2 SCL 11 25 BST 1 2BST_CHGA 1 2 DCR=7m-Ohm(Max)
3
2
1
SCL BOOT PR716
<30,44> ADP_I PD700
VSMB 12 24 DH_CHG PL701 0.02_1206_1%
VSMB UGATE
REGN 2 2.2UH_PCMB104T-2R2MS_12A_20% +VCHGR
2
PC720 1 RST# 13 23 LX_CHG 1 2 1 4

1000P_0402_25V8J 3 RST# PHASE
+3VLP 14 22 2 3
SIRA06DP-T1-GE_POWERPAKSO-8-5
1
BAS40CW_SOT323-3 ACOK PGND
1
REGN
680P_0402_50V7K
PC720 Close EC pin
BGATE
LGATE
BMON
5
AGND
CSON
CSOP
@EMI@
VDDP
PC715
VDD
2
2
1
PQ705
100K_0402_1%
PC726
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PR707
.1U_0402_16V7K ISL9520HRTZ-T_TQFN28_4X4~D
1
29
15
16
17
18
19
20
21
1
PC716
PC712
PC713
2.2_0402_1%
PR708
One-shot BATT_TEMP RST# DL_CHG 4
2
ACIN <10,30,35,44>
1
VSMB ACIN
4.7_1206_5%
1
PR722
REGN
Plug in
1
2
3
1
@EMI@
158K_0402_1%
PR710
battery Low High 4.7_0603_5%
BGATE
PR712
1 2 PC722
2
1U_0603_25V6K
1
1 2
499K_0402_1%
2
PR713
3 3
Plug out
2
PC709
PC719
1U_0603_10V6K
1U_0603_10V6K
battery High Low
2
RST#
1
6
PQ706A
@ PC723
2 1 2
<30,44> BATT_TEMP <44> BATT_I
1
2
499K_0402_1%
0.47U_0402_6.3V6K PC725
2
1000P_0402_25V8J
PR724
CSOP
1
PC725 Close EC pin CSON

1
2S2P : CV = 8.4V CC = 3.9A

3S1P : CV = 12.6V CC = 2A
4 4

PWR_CHARGER
1.0
LA-B012P
A B C D
A B C D E
1 1
+3VLP
PC109
4.7U_0603_10V6K
1 2
Output capacitor ESR need follow

@ PC102 @ PC108
100P_0402_50V8J 100P_0402_50V8J below equation to make sure feed back
1 2 1 2 loop stability
PR109 PR104 ESR=20mV*L*fsw/2V
130K_0402_1% 150K_0402_1%
1 2 1 2
VFB=2V VFB=2V
PR107 PR106
200K_0402_1% 100K_0402_1%
1 2 1 2
POK need pull high, it 3/5V_B+

will pull high on VS
transfer circuit
2 PR105 2
EMI@
1
PL102 1 2
1UH_PCMB053T-1R0MS_7A_20% PR108
B+ 1 2 3/5V_B+
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V7K
23.7K_0402_1% 23.7K_0402_1%
FB_3V
FB_5V
1
CS2
CS1
@EMI@ PC117
@EMI@ PC116
PC112
2
+3VALW
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V7K
2
1
1
@EMI@ PC113
EMI@ PC114
PC115
MDV1528URH-1N-PDFN33-8
MDV1528URH-1N-PDFN33-8
5
5
PU100 21
CS2
VFB2
VREG3
VFB1
CS1
2
PR115 TP
10K_0402_5%
3V_EN 6 20 5V_EN
EN2 EN1
PQ101
PQ103
PR114
1
4 200_0402_5% 4
7 19 1 2
<30> EC_SPOK PGOOD VCLK
LX_3V 8 18 LX_5V
1
2
3
3
2
1
PL100 PC104 PR103 SW2 SW1 PR111 PC110 PL101
2.2UH_PCMB063T-2R2MS_8A_20% 0.22U_0603_25V7K 2.2_0603_5% TPS51285BRUKR_QFN20_3X3 2.2_0603_5% 0.22U_0603_25V7K 2.2UH_PCMB063T-2R2MS_8A_20%
2 1 1 2 1 2 BST_3V 9 17 BST_5V 1 2 1 2 1 2 +5VALWP
+3VALWP VBST2 VBST1
UG_3V 10 16 UG_5V
DRVH2 DRVH1
1
4.7_1206_5%
680P_0603_50V8J 4.7_1206_5%
VREG5
DRVL2
DRVL1
1
@EMI@ PR113
@EMI@ PR112
VO1
5
5
VIN
FDMC7692S-1N-MLP
220U_6.3V_M
220U_6.3V_M
ESR=18m ohm
ESR=18m ohm
1 1
2
11
12
13
14
15
FDMC7692S-1N-MLP
2
PQ102
PQ104
+ +
PC101
PC107
4 LG_3V LG_5V 4
680P_0603_50V8J
1
1
2 2
@EMI@ PC103
@EMI@ PC111
3 +5VALWP 3
2
1
2
3
3
2
1
2
3/5V_B+
VL
1U_0603_25V6K
4.7U_0603_10V6K
1
1
@ PC105
PC106
2
Change to 4.7u for TPS51285
@ PR100 0_0402_5%
3V_EN 1 2
3VALWP
TDC 5.95A @ PR101 0_0402_5%
Peak Current 8.5A 5V_EN 1 2
OCP current 10.2A

TYP MAX 5VALWP
H/S Rds(on): 22mohm , 30mohm PR102
TDC 5.96A
L/S Rds(on):10.8mohm ,13.6mohm <30> EC_ON
10K_0402_5% Peak Current 8.51A
1 2
OCP current 10.2A
TYP MAX
3V_EN
@ PJP100 @ PJP101
H/S Rds(on): 22mohm , 30mohm
5V_EN
+3VALWP
1 2 +3VALW +5VALWP
1 2
+5VALW L/S Rds(on):10.8mohm , 13.6mohm
4 4
<30> VCOUT0_PH#
PAD-OPEN 4x4m PAD-OPEN 4x4m
@ PJP102 @ PJP103
4.7U_0603_6.3V6K
1 2 1 2
3
PC100
PR110
EMI@ 20K_0402_1% PAD-OPEN 4x4m PAD-OPEN 4x4m
2
PD101
2
TVNST52302AB0_SOT523-3
1
PWR_3.3VALWP/5VALWP
Place PD101 close to PU100 Size Document Number Rev
1.0
LA-B012P
A B C D E
A B C D
+3VALW +5VALW
PJP401 @
1 2
+1.5VSP 1 2 +1.5VS
1
JUMP_43X79
1
PC400
1
1U_0402_6.3V6K
JUMP_43X79
2
2
@ PJP400
1
Ultra Low Dropout 0.23V(typical) at 3A Output Current 1
2
PC401 PU400
1
4.7U_0603_10V6K APL5930KAI-TRG_SO8
6
5 VCNTL 3
2
PR402 9 VIN VOUT 4
10K_0402_5% VIN VOUT +1.5VSP
1
<28,30,48> SUSP# 1 2 8
1.58K_0402_1%
EN
1
7 2
GND
POK FB
PR400
PC403
1
0.01U_0402_25V7K
Rup
0.1U_0402_16V7K
1
PC402
PR403 PC404
2
10K_0402_5% 22U_0805_6.3V6M
2
2
@
1
PR401
1.74K_0402_1%
Rdown
2
Vout=0.8V* (1+Rup/Rdown)
2 2
PJP601 @
1 2
+1.8VSP 1 2 +1.8VS
JUMP_43X79
@ PR601
0_0402_5%
+1.8VSP_ON 1 2 PXS_PWREN PXS_PWREN <10,11,36,51,52>
0.1U_0402_16V7K
1
PC603
1
PR604 VGA@
1M_0402_5%
@
Note:Iload(max)=2.5A
2
VGA@
2
PU600
9
1 PGND 8
FB SGND
PJP600 @ 2 7 VGA@ PL600
PG EN 1UH_PH041H-1R0MS_3.8A_20%
1 2 3 6 LX_1.8VSP 1 2
+3VALW 1 2 IN LX +1.8VSP
1
4 5
68P_0402_50V8J
JUMP_43X79 PGND NC
1
PC605
4.7_0603_5%
1
@EMI@ PR605
VGA@ PC604
22U_0805_6.3VAM VGA@
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
VGA@ SY8003DFC_DFN8_2X2 PR603
Rup
VGA@ PC602
VGA@ PC600
20K_0402_1%
2
2
2
FB_1.8VSP
3 3
1
1
FB=0.6V
680P_0402_50V7K
VGA@
@EMI@ PC601
Note:Iload(max)=3A PR602
Rdown
10K_0402_1%
4 4

PWR_1.5VSP / 1.8VSP
1.0
LA-B012P
A B C D
5 4 3 2 1
D D
EN pin don't floating

If have pull down resistor at HW side, pls delete PR301
@ PR310
0_0402_5%
1 2
SYSON <30,49>
@ PR300
0_0402_5%
1 2
SUSP# <28,30,47>
C C
1
@ PC300
1M_0402_1%
0.22U_0402_10V6K
2
PR301
2
@EMI@ PR302 @EMI@ PC301
4.7_1206_5% 680P_0603_50V7K
EMI@ PL302 1 2SNB_1.05V 1 2 +1.05VSP @ PJP300
FBMJ4516HS720NT_2P PU300 1 2
1 2 +1.05VS
B+ 1 2 B+_1.05V 8
IN EN
1 @ PR303 PC302
0_0603_5% 0.1U_0603_25V7K JUMP_43X118
10U_0805_25V6K
10U_0805_25V6K
6 BST_1.05V 1 2 1 2 PL301
0.1U_0402_25V6
2200P_0402_50V7K
BS
1
0.68UH +-20% 7.9A 5X5X3 MOLDING

@EMI@ PC304
PC305
PC306
+1.05V_LDO_3V 9 10 LX_1.05V 1 2
+1.05VSP
EMI@ PC303
GND LX
2
15K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
1
330P_0402_50V7K
1
1
4
PR305
@ PR304 FB @ PJP301
PC307
PC308
PC309
PC310
@ PC311
0_0402_5% ILMT_1.05V 3 7 2 1
Rup
+3VALW
2
ILMT BYP 2 1
2
2
4.7U_0603_6.3V6K
ILMT_1.05V
+3VS 1 2 +1.05V_PGOOD 2
PG LDO
5+1.05V_LDO_3V JUMP_43X39
1
PR308
PC313
4.7U_0603_6.3V6K
1
10K_0402_5% SY8206DQNC_QFN10_3X3
PC312
1K_0402_1%
FB = 0.6V
PR309
2
@ PR306
2
0_0402_5%
2
2
1
<30> +1.05V_PGOOD
Pin 7 BYP is for CS. PR307
B
The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC313 Rdown B
20K_0402_1%
is pull low, floating or pull high
2
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.05V
+1.05VSP
TDC 5A
Peak Current 6.6A
OCP current 8A
A A

PWR_+VCCIO
C 1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
D D
0.675Volt +/- 5%
EMI@ PL201
FBMJ4516HS720NT_2P
TDC 0.7A
B+ 1 2 1.35V_B+ PR200 Peak Current 1A
2.2_0603_5%
BST_1.35V 1 2 BOOT_1.35V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1
@ PR209
@EMI@ PC208
EMI@ PC201
PC206
PC212
0_0402_5%
1 2 DH_1.35V +0.675VSP
2
SW_1.35V
10U_0805_6.3V6K
10U_0805_6.3V6K
1
1
PC200
PC205
PC211
5
0.1U_0603_25V7K
16
17
18
19
20
2
PU200
2
VLDOIN
BOOT
VTT
PHASE
UGATE
21
PQ200 PAD
AON7408L 4 DL_1.35V 15 1
LGATE VTTGND
14 2
PL200 PR205 PGND VTTSNS
1
2
3
1UH_PCMB063T-1R0MS_12A_20% 11.8K_0402_1%
+1.35VP 1 2 1 2 CS_1.35V 13
CS GND
3
PC204 RT8207MZQW_WQFN20_3X3
1
1U_0603_10V6K
5
@EMI@ PC207 1 2 12 4 VTTREF_1.35V
ESR=16m ohm
680P_0402_50V7K PR206 VDDP VTTREF
2
330U_2.5V_M
C 1 5.1_0603_5% C
1 2 VDD_1.35V 11 5
+5VALW VDD VDDQ +1.35VP
1
+
PC213
PGOOD
PQ201
1
AON7752 4 PC210
TON
1
PR210 0.033U_0402_16V7K
FB
S5
S3
2
2 @EMI@ PR203 PC209 5.1_0603_5%
4.7_1206_5% 1U_0603_10V6K @ PC214
10
6
220P_0402_25V8J
1
2
3
2
1 2
EN_0.675VSP
FB_1.35V
TON_1.35V
EN_1.35V
PR207
+5VALW 54.9K_0402_1%
PR208 1 2 +1.35VP
680K_0402_1%
1.35V_B+ 1 2
1.35VP
1
TDC 6A
Peak Current 8A @ PR201 PR204
0_0402_5% 68.1K_0402_1%
OCP current 10A <30,48> SYSON
1 2
2
1
@ PC202
0.1U_0402_10V7K
2
@ PR202
0_0402_5%
1 2
<17> 0.675V_DDR_VTT_ON
1
@ PJP200
@ PC203 +1.35VP 1 2 +1.35V
0.1U_0402_10V7K 1 2
2
JUMP_43X118
B @ PJP201 B
1 2
1 2
JUMP_43X118
@ PJP203
2 1
+0.675VSP 2 1 +0.675VS
JUMP_43X39
A A

PWR_+1.35VP/0.675VSP
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
EMI Part (47.1)

+1.05VS_PCH PR500 130_0402_1%
2 1
EMI@ PL501 B+
@ PR503 75_0402_5% FBMJ4516HS720NT_2P
2 1 +VCC_PWR_SRC 1 2
PC548
1U_0402_6.3V6K PR504 54.9_0402_1% @EMI@
1 2 2 1 PL503
PC532 @EMI@
PC519 @EMI@
EMI@
2.2UH_PCMB053T-2R2MS_5.5A_20%
@ PR505 0_0402_5% 1 2
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V7K
1 2
100U_25V_M
100U_25V_M
<13> VR_SVID_DAT 1 1
15W@ PR507
1
+ +
PC524
PC517
PC518
PC521
PC515
PC516
@ PR506 0_0402_5% 90.9K_0402_1%
D
1 2 SDA_CPU 1 2 D
<13> VR_SVID_ALRT#
2
@ PR508 0_0402_5% 2@ 2
1 2 ALERT#
<13> VR_SVID_CLK
SCLK_CPU
CPU_CORE
<13,30> VR_ON
@ PR511
1 2
0_0402_5% TDC 10A/14A(PL2)@15W CPU
TDC 16A/19A(PL2)@28W CPU
1
PR519 Peak Current 32A@15W CPU
@ PR552
21
20
19
18
17
1.5K_0402_5%
PU501 0_0402_5% Peak Current 40A@28W CPU
1 2
OCP current 40A@15w
ALERT#
PRGM1
PAD
SCLK
SDA
2
1
PC500
1 2 VR_ON_1 1 16 LGATE
2 DCR=0.48m-Ohm +/-5% OCP current 48A@28W
VR_ON LGATE PL502 Choke DCR 1.1m-Ohm(Max)
1000P_0402_50V7K 7 0.15UH_PCMB104T-R15MSMS0R485_40A_20%
<13> H_VR_READY
2 15 PHASE 3 6 SW_CPU2 SW_CPU2 1 4 Load line -2mV/A
PR521 PGOOD PHASE 5
97.6K_0402_1% 4 2 3
+CPU_CORE
1
2 1 IMON 3 14 UGATE
680P_0402_50V7K
IMON UGATE
PC520
@ PR510 0_0402_5% ISL95813HRZ-T_QFN20_3X4 PR538
2
1 2 VR_HOT#_1 4 13 2 1 1 2 PQ501
<30> VR_HOT#
8
PR525 VR_HOT# BOOT 2.2_0603_5% PR536
3.83K_0402_1% PC525 CSD87351Q5D_SON8
47P_0402_50V8J
3.65K_0603_1%
@EMI@
2 1 1 2 NTC 5 12 0.22U_0603_16V7K
4.7_1206_5%
NTC VCC
1
PC510
@EMI@ PR534
PH500
ISUMP 1
470K_0402_5%_ TSM0B474J4702RE
ISUMN
COMP 6 11
2
PR528 COMP PRGM2
ISUMN
ISUMP
2
27.4K_0402_1%
RTN
1
2 1
FB
+5VALW
1
PR512
C 124K_0402_1% PC528 C
10
909_0402_1%
0.1U_0603_25V7K
2
2
2
PR539
PC531
2 1
33P_0402_50V8J
1
6800P_0402_25V7K
PC526
4700P_0402_50V7K
1
PC523
PR507 28W@ PR535 28W@ PR537 28W@
210_0402_1%
2
1
@
15W@ PR535
PC522
PR533 82P_0402_50V8J 113K_0402_1% 261_0402_1% 1.62K_0402_1%
2 1 2 1
2
2
1.5K_0402_1%
PR545
0_0402_5%
15W@ PR537
2 1 @
1
1.37K_0402_1%
2
PR543
2K_0402_1%
4.99M_0402_1%
PC530
2 1
.047U_0402_16V7K
PR558
1 2
PC527
330P_0402_50V7K
1
2
B @ B
PC529
0.1U_0402_10V6K
1 2
<13> VCCSENSE
PR549
11K_0402_1%
@ PC541 1 2
Check are there a pair 100Ω 1 2
at HW side and close to CPU. PR551
0.082U_0402_16V7K
PC545
330P_0402_50V7K
1
5.23K_0402_1%
1 2 1 2
2
PC546 @ PH501
1 2 10KB_0402_5%_ERTJ0ER103J
ISUMP
0.01U_0402_50V7K
<13,15> VSSSENSE ISUMN
A A

PWR_VCORE
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
VGA@_EMI@ PL1100
FBMJ4516HS720NT_2P
+1.35VGPUP_B+ 1 2
B+
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
1
1
@EMI@ PC1100
VGA@_EMI@ PC1101
VGA@ PC1102
+3VS
2
TDC=9A
5
1
D Peak Current=13A @ 1
@ PJP1100
2
D
+1.35VGPUP 1 2 +1.35VS_VGA
OCP=16A PR1110 VGA@
100K_0402_5% PQ1100 JUMP_43X118
4 AON7408L @ PJP1101
2
VGA@ VGA@ 1 2
PR1101 PC1103 1 2
PU1100 VGA@ 2.2_0603_5% 0.1U_0603_25V7K JUMP_43X118
PR1102 VGA@ 1 10 1
BST_+1.35VGPUP 2 1 2
3
2
1
154K_0402_1% PGOOD VBST
@ PR1103 1 2 TRIP_+1.35VGPUP2 9 UG_+1.35VGPUP VGA@ PL1101
0_0402_5% TRIP DRVH 1UH_PCMB063T-1R0MS_12A_20%
1 2 EN_+1.35VGPUP 3 8 SW _+1.35VGPUP 1 2
<10,11,36,47,52> PXS_PW REN EN SW
+1.35VGPUP
FB_+1.35VGPUP 4 7
VFB V5IN
+5VALW
ESR=16m ohm
0.1U_0402_16V7K
RF_+1.35VGPUP 5 6 LG_+1.35VGPUP
TST DRVL
1
PR1104 @EMI@
@ PC1104
330U_2.5V_M
1
1
11 VGA@ 4.7_1206_5%
TP
1
VGA@ PQ1101 +
PC1108
2
2
4
VGA@
PR1105 VGA@ TPS51212DSCR_SON10_3X3 PC1105 AON7752
470K_0402_1% 1U_0603_10V6K
1
PC1106 @EMI@ 2
2
680P_0402_50V7K
3
2
1
2
C C
PR1107 VGA@
9.09K_0402_1%
1 2
1
PR1108 VGA@
10K_0402_1%
2
B B
A A

PWR_+1.35VGPU
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
@EMI@
GPU_B+ PL1004
2.2UH_PCMB053T-2R2MS_5.5A_20%
1 2
VGA@_EMI@ PL1000
FBMJ4516HS720NT_2P
1 2
B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K
MDU1516URH_POWERDFN56-8-5
1
5
VGA@_EMI@ PC1047
@EMI@ PC1052
VGA@ PC1048
VGA@ PC1041
VGA@ PC1046
@EMI@ PC1045
PQ1005 VGA@
D D
2
2
2
@ PR1062
0_0402_5%
UGATE2 1 2 4
SH00000NX00 (DCR:1.4± 5%)

VGA@ PL1003
3
2
1
10K_0402_1% VGA@
10K_0402_1% VGA@
.36UH 20% PDME064T-R36MS1R405 24A
PHASE2 1 4
VGA@
PR1055
VGA@
PC1043 VGA@ PR1059 2 3
+VGA_CORE
2.2_0603_1% 0.22U_0603_25V7K @EMI@ 10K_0402_1%
1
BOOT2 1 2 1 2 PR1054 ISEN2 1 2
1
4.7_1206_5%
VGA@ PR1057
5
MDU1511RH 1N POWERDFN56-8
3.65K_0603_1%
+5VALW 1 2
PR1035
PR1056
@EMI@ VSUM+
1 2
@
PQ1006 VGA@
PC1044
2
@ PR1063 680P_0603_50V7K VGA@ PR1053
0_0402_5% 1_0402_1%
LGATE2 1 2 4 4 VSUM- 1 2
2
PQ1008
VGA@
41
40
39
38
37
36
35
34
33
32
31
PU1000
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
3
2
1
3
2
1
VGA@ PR1032 100K_0402_1%
1 2 1 30 BOOT2
VGA@ PR1033 100K_0402_1% NTC_NB BOOT2
1 2 2 29 UGATE2
IMON_NB UGATE2
3 28 PHASE2
<35> SVI2_SVC SVC PHASE2
4 27 LGATE2 +5VALW VGA_CORE
<35> OCP_L VR_HOT_L LGATE2
@ PR1020 100K_0402_1%
1 2 5 26
TDC 31A
+3VS <35> SVI2_SVD SVD VDDP
ISL62771HRTZ-T_TQFN40_5X5 VGA@ PR1024 GPU_B+ Peak Current 38A
+1.8VGS 1@ PR1022 2 0_0402_5% VDDIO 6 25 1 2
VDDIO VDD 1_0603_5% OCP current 45A
1U_0603_10V6K
@PR1025
@PR1025
1
0_0402_5% 7 24 LGATE1
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
<35> SVI2_SVT SVT LGATE1 Load line -1mV/A(only Topaz)
1
C 1 2 C
@ PR1027
0.1U_0402_25V6K
1U_0603_10V6K
+1.5VS
PC1019 1 2 ENABLE 8 23
VGA@ PC1021
PHASE1
<10,11,36,47,51> PXS_PWREN FSW=300kHz
2
ENABLE PHASE1
MDU1516URH_POWERDFN56-8-5
VGA@ PC1020
0.1U_0402_25V6K 0_0402_5%
1
5
VGA@_EMI@ PC1042
DGPU_PWROK 9 22 UGATE1
VGA@ PC1049
VGA@ PC1024
VGA@ PC1023
@EMI@ PC1025
VGA@
PWROK UGATE1
VGA@
1 2 IMON_GPU 10 21 BOOT1
2
2
2
IMON BOOT1 +3VS
PR1029 VGA@ @ PR1060
PGOOD
133K_0402_1% 0_0402_5%
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
1 2 4
PQ1003
UGATE1
NTC
RTN
1 2 VGA@ FB
1
1000P_0402_50V7K VGA@ VGA@
PC1022 PR1031 PR1052 SH00000NX00 (DCR:1.4± 5%)
11
12
13
14
15
16
17
18
19
27.4K_0402_1% 13.3K_0402_1% 20 @ PR1030 VGA@ PL1002
3
2
1
1 2 1 2 100K_0402_1% .36UH 20% PDME064T-R36MS1R405 24A
2
PHASE1 1 4
PH1002 near GPU_CORE H/S mos 1 2 DGPU_PWROK <10,30>
VGA@
PR1034
VGA@
PC1026 VGA@ PR1058 2 3
+VGA_CORE
VGA@ PH1002 2.2_0603_1% 0.22U_0603_25V7K @EMI@ 10K_0402_1%
1
470K_0402_5%_TSM0B474J4702RE PC1050 VGA@ BOOT1 1 2 1 2 PR1036 ISEN1 1 2
0.22U_0402_10V6K 4.7_1206_5%
1 2 ISEN2 VGA@ PR1039
5
3.65K_0603_1%
PC1051 VGA@ @EMI@ VSUM+ 1 2
1 2
@
VGA@
0.22U_0402_10V6K PC1029
VSUM- 1 2 ISEN1 @ PR1061 680P_0603_50V7K VGA@ PR1043
VGA@ 0_0402_5% 1_0402_1%
VGA@ VGA@ PC1028 LGATE1 1 2 4 4 VSUM- 1 2
2
PQ1004
PQ1007
PC1027 PR1037 100P_0402_50V8J @ PR1038
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1%
VSUM+ 1 2 1 2 1 2 1 2
PR1042 VGA@
330P_0402_50V7K
3
2
1
3
2
1
@ PC1030
VGA@ VGA@
2.61K_0402_1%
1
VGA@ PR1040 PR1041 PC1033

10K_0402_5%_ERTJ0ER103J
0.01U_0402_50V7K
0.22U_0603_16V7K
825_0402_1% 137K_0402_1% 390P_0402_50V7K

11K_0402_1%
1
1 2 1 2 1 2
PC1031
2
1
1
VGA@ PR1044
VGA@ PC1032
VGA@ VGA@
1 2
PR1045 PC1034
2
@ 2K_0402_1% 330P_0402_50V7K
2
1 2 1 2
PH1003 near GPU_CORE choke
VGA@
PH1003
B VGA@ B
PR1046 VGA@ PR1047
2
590_0402_1% 10_0402_5%
VSUM- 1 2 1 2 +VGA_CORE
@ PC1036 @ PR1049
1
VGA@ @ PR1048 820P_0402_50V7K 0_0402_5%

PC1035 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 VCCSENSE_VGA <35> VGA@
2
@ VGA@ PL1300
PJP1301 +VGA_PCIEP
4
+3VALW PU1300 0.47UH_PCMB063T-R47MS_18A_20%
1 2 2 1 PCIE_B+ 10 2 LX_PCIE 1 2
PG
VSSSENSE_VGA <35> 2 1 PVIN LX
0.01U_0402_50V7K
VGA@ PR1051
0_0402_5% 10_0402_5% 9 3
JUMP_43X79 PVIN LX
1
1
VGA@ PC1040
@ PR1050 1 2 VGA@
4.7_1206_5%
1
PC1301 8
SVIN
@EMI@ PR1303
22U_0805_6.3VAM
2
6 FB_PCIE
2
5 FB
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
2
EN
1
SS
TP
LX
VGA@ PC1300
VGA@ PC1303
VGA@ PC1305
VGA@ PC1308
VGA@ PR1300 SY8036LDBC_DFN10_3x3
11
2
1 2EN_PCIE
PC1307 VGA@
PXS_PWREN
SNUB_PCIE
1
VGA@ PC1302
200K_0402_5% PR1302 VGA@
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
@ PR1304 5.9K_0402_1%
47K_0402_5% 2 1
2
2
680P_0402_50V7K
@EMI@ PC1304
PC1306
VGA@
2
1
2 1
VGA@ PR1301
+VGA_PCIEP
10K_0402_1% 22P_0402_50V8J
+VGA_PCIE
Vout=0.95V
2
TDC 3A
PJP1300
@ Peak Current 4.2A
A +VGA_PCIEP
2
2 1
1
+VGA_PCIE
OCP current 6A A
JUMP_43X79

PWR_VGA_CORE/PCIE
Custom 1.0
LA-B012P
5 4 3 2 1
A
B
C
D
5
5
+CPU_CORE
2 1 2 1 2 1
@
@
@
PC917 PC909 PC901

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
@
PC918 PC910 PC902

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
@
@
@
PC919 PC911 PC903

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
4
4
@
@
PC920 PC912 PC904

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
@
@
PC921 PC913 PC905

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
@
@
PC922 PC914 PC906

22U_0805_6.3V6M 2.2U_0402_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
@
PC923 PC915 PC907

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1
2
1
+
@
220U_D2_2.5VY_R9M PC916 PC908

PC924 22U_0805_6.3V6M 22U_0805_6.3V6M
3
3
Issued Date
Security Classification
+VGA_CORE
2014/01/20
VGA@ 10U_0603_6.3V6M VGA@ 2.2U_0402_6.3V6M VGA@ 2.2U_0402_6.3V6M
PC857 PC848 PC840
2
1
2
1
2
1
VGA@ 10U_0603_6.3V6M VGA@ 2.2U_0402_6.3V6M VGA@ 2.2U_0402_6.3V6M

PC858 PC849 PC841
2
1
2
1
2
1
VGA@ 0.1U_0402_10V7K VGA@ 2.2U_0402_6.3V6M VGA@ 2.2U_0402_6.3V6M
2
2
PC859 PC850 PC842

2
1
2
1
2
1
VGA@ 0.1U_0402_10V7K VGA@ 2.2U_0402_6.3V6M VGA@ 2.2U_0402_6.3V6M

PC860 PC851 PC843
2
1
2
1
2
1
Compal Secret Data
VGA@ 2.2U_0402_6.3V6M VGA@ 2.2U_0402_6.3V6M

Deciphered Date
PC852 PC844
2
1
2
1
VGA@ 2.2U_0402_6.3V6M VGA@ 2.2U_0402_6.3V6M

PC872 PC845
2
1
2
1
VGA@ 10U_0603_6.3V6M VGA@ 2.2U_0402_6.3V6M

PC853 PC846
2
1
2
1
VGA@ 10U_0603_6.3V6M VGA@ 2.2U_0402_6.3V6M

PC854 PC847
2
1
2
1
2015/01/19
VGA@ 10U_0603_6.3V6M VGA@ 2.2U_0402_6.3V6M

PC855 PC869
2
1
2
1
VGA@ 10U_0603_6.3V6M VGA@ 2.2U_0402_6.3V6M

PC856 PC871
2
1
2
1
2
1
+
330U_D3_2.5VY_R6M
VGA@ PC836
Size
Date:
Title
2
1
+
330U_D3_2.5VY_R6M
VGA@ PC837
2
1
+
330U_D3_2.5VY_R6M
VGA@ PC838
2
1
+
Document Number
330U_D3_2.5VY_R6M
VGA@ PC839
LA-B012P
Tuesday, August 05, 2014
1
1
Sheet
53
of
55
PWR_PROCESSOR DECOUPLING
Rev
1.0
A
B
C
D
5 4 3 2 1
D Power block D
CPU OTP
Page 44
Turn Off
B+
Input +3VALWP: TDC:5.4A
DC IN Switch Page 45 EC_ON
+5VALWP: TDC:5.6A
TPS51285BRUKR Page 46
C +3VALW +1.8VSP: TDC:1.5A PXS_PWREN C
SY8003DFC
Page 47
CHARGER
CC:0A~2A(3cell) or 3.9A(2cell)
CV:13.3V(3cell) / 9.1V(2cell) +3VALW +1.5VSP: TDC:1A SUSP#
ISL9520
APL5930
Page 45 Page 47
+3VALW +VGA_PCIEP: TDC:3A PXS_PWREN

Battery
SY8036LDBC
Page 52
+VGA_CORE
PXS_PWREN
B TDC: 31A B
ISL62771HRTZ-T
Page 52
+VCCIO: TDC:5A SYSON

SY8206DQNC Page 48
+CPU_CORE
VR_ON
TDC: 14A@15W /19A@28W +1.35VP/+0.675VSP: TDC:6A/0.7A SYSON
ISL95813HRZ-T RT8207MZQW
Page 50
Page 49
+1.35VGPUP: TDC:9A PXS_PWREN

TPS51212DSCR Page 51
A A

PWR_POWER BLOCK DIAGRAM
1.0
LA-B012P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
D
Item Page# Title Date Issue Description Solution Description Rev. D
Owner
1 44 DCIN/BATT CONN/OTP 13/10/24 Morris design change change PR16 from 100K to 10K 0.2
add PR37 10K
2 45 CHARGER 13/10/24 Morris design change change PC711 from 1000pF to 0.01uF 0.2
change PR711 from 49.9K to 51.1K
change PR713 from 10K to 499K
change PR724 from 100K to 499K
change PC721 from 0.047u to 0.22u
change PC722 from 0.1u to 1u
add PC732 100u
3 46 3.3VALWP/5VALWP 13/10/24 Morris design change for solve can't root issue change PC104 from 0.1u to 0.22u 0.2
change PC110 from 0.1u to 0.22u
change PR102 from 2.2K to 10K
add PR110 20K
4 50 VCORE 13/10/24 Morris adjust CPU parameter change PR507(15W@) from 90.9K to 169K 0.2
change PR519 from 1.91K to 10K
C C
change PR539 from 8.06K to 909
change PC515,PC516 from SF000005100 to SF000004M00
change PL502 from SH00000NM00 to SH00000PQ00
change PR535(15W@) from 340 to 210
change PR535(28W@) from 432 to 261
change PR507(28W@) from 113K to 205K
add PC522 82pF
add PR533 0-ohm
6 52 VGA_CORE/PCIE 13/10/24 Morris design change from vendor change LL change PR1040 from 1.24K to 825 0.2
7 53 PROCESSOR DECOUPLING 13/10/24 Morris adjust CPU parameter change PC924 from SGA20331E10 to SGA00009800 0.2
remove PC901,PC903,PC904,PC906,PC908,PC909,PC910,PC911,PC912,PC913,PC914,
PC915,PC917,PC919,PC921
8 45 CHARGER 13/10/28 Morris design change for plug out battery shut down issue change PC723 from 0.01uF to 0.47uF 0.2
change PR728 from 0 to 9.09K
B change PC728 from 4700pF to 2200pF B
change PC701 from 220pF to 1000pF
9 46 3.3VALWP/5VALWP 13/12/12 Morris design change from EE request add PR115 10K-ohm 0.3
10 50 VCORE 13/12/12 Morris design change from Intel recommend change PR519 from 10K to 1.5K 0.3
11 48 +VCCIO 13/12/13 Morris design change from EE request delete PR310 and add PR300 0-ohm 0.3
12 50 VCORE 14/01/20 Morris adjust CPU parameter change PR507(15W@) from 169K to 90.9K
1.0
change PR507(28W@) from 205K to 113K
13 53 PROCESSOR DECOUPLING 14/02/13 Morris design change from thermal request change PC836 PC837 PC838 PC839 from SGA20331E10 to SGA00006A00 1.0
A A

PWR-PIR
1.0
LA-B012P
5 4 3 2 1

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5 4 3 2 1

MODEL NAME : Maple

Dell / Compal Confidential

UMA / DIS AMD 25W/S3+DDR3x4

Security Classification Compal Secret Data Compal Electronics, Inc.

VRAM 128M*16 32bit

eDP Conn. eDP 8GB Max

USB 3.0 Port 1

Processor USB2.0 Port 2

Port 6 Card Reader

SATA HDD Conn. Port 0 SATA Rediver SATA3.0

HD Audio Audio Codec Headphone Jack /

SPI ROM SPI Int. Speaker R / L

ENE KBC PS/2

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

Board ID Table for AD channel

Lane 4 MINI Card (WLAN)

Lane 5 PEG (AMD JET/TOBAZ)

Security Classification Compal Secret Data Compal Electronics, Inc.

KB9012A4 100 ohm 3 4 3

Security Classification Compal Secret Data Compal Electronics, Inc.

UC1 I3R1@ UC2 I3R3@

DDI1_LANE_N0 C54 C45

UC9 QFSY@ UC10 QG22@ 1 OF 19 Rev1p2

<17> DDR_A_D[0..15] AH63 AU37 AY31 AM38

+1.35V +1.35V +1.35V

A confirm by intel request PDG P141 A

Security Classification Compal Secret Data Compal Electronics, Inc.

+RTCVCC High - Enable Internal VRs HIGH = ENABLED

EMI@ R3 1 2 33_0402_5% PCH_AZ_SYNC

Open Keep ME RTC Registers

R2334 1 2 1K_0402_1% 7 OF 19 Rev1p2

SML1 Bus : EC/Sensors

Issued Date 2014/01/20 Deciphered Date 2015/01/19 Title

DSWODVREN - On Die DSW VR Enable

0.047U_0402_16V4Z PCH_BATLOW# Need pull high to VCCDSW3_3 @ T106

Security Classification Compal Secret Data Compal Electronics, Inc.

RP54 GPIO66 GPIO86 GPIO15 GPIO81

Security Classification Compal Secret Data Compal Electronics, Inc.

PEG_CRX_GTX_N0 F10 AN8 USB20_JUSB1_N0

Security Classification Compal Secret Data Compal Electronics, Inc.

Place the PU VCCST_PG_EC B59 HSW ULT POWER F48

43_0402_1% CPU_PWR_DEBUG# H59 VSS VCC G27

+1.05VS_PCH T50 @ U59 G53

0_0402_1% AE23 VCCST VCC K23

VSSSENSE CAD Note: PD resistor on HW side

Security Classification Compal Secret Data Compal Electronics, Inc.

L11 2 C58 1 2 1U_0402_6.3V6K

0_0402_5% 2 @ 1 RC143 AH13 VRM/USB2/AZALIA VCC1_05 AG19 1 2

C78 1 2 22U_0603_6.3V6M Close to AC9/AA9/AE20/AE21

C82 1 2 22U_0603_6.3V6M Close to V8

+1.05VS_PCH C87 1 2 1U_0402_6.3V6K Close to J17

C88 1 2 1U_0402_6.3V6K Close to R21

C75 2 1 0.1U_0402_10V7K Close to AH14

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

CFG0 AC60 AV63 PAD~D T146 @

SLG3NB3374V is for DIS by output 24M1,25M1, 27M1, 32K1