Burr Brown Products PCM3002

from Texas Instruments

PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO

CODECS
FEATURES

APPLICATIONS
DVC Applications
Monolithic 20-Bit   ADC and DAC DSC Applications
16/20-Bit Input/Output Data Portable/Mobile Audio Applications
Software Control: PCM3002
Hardware Control: PCM3003
Stereo ADC: DESCRIPTION
– Single-Ended Voltage Input The PCM3002 and PCM3003 are low-cost,
– Antialiasing Filter single-chip stereo audio codecs (analog-to-digital and
– 64× Oversampling digital-to-analog converters) with single-ended analog
– High Performance voltage input and output.
THD+N: –86 dB The ADCs and DACs employ delta-sigma modulation
SNR: 90 dB with 64-times oversampling. The ADCs include a
digital decimation filter, and the DACs include an
Dynamic Range: 90 dB
8-times oversampling digital interpolation filter. The
Stereo DAC:
DACs also include digital attenuation, de-emphasis,
– Single-Ended Voltage Output
infinite zero detection, and soft mute to form a
– Analog Low-Pass Filter
complete subsystem. The PCM3002 and PCM3003
– 64× Oversampling operate with left-justified (ADC) and right-justified
– High Performance (DAC) formats, while the PCM3002 also supports
THD+N: –86 dB other formats, including the I2S data format.
SNR: 94 dB The PCM3002 and PCM3003 provide a power-down
Dynamic Range: 94 dB mode that operates on the ADCs and DACs indepen-
Special Features (PCM3002, PCM3003) dently.
– Digital De-Emphasis: 32 kHz, 44.1 kHz, The PCM3002 and PCM3003 are fabricated using a
48 kHz highly advanced CMOS process, and are available in
– Power Down: ADC/DAC Independent a 24-pin SSOP package. The PCM3002 and
Special Features (PCM3002) PCM3003 are suitable for a wide variety of
– Digital Attenuation (256 Steps) cost-sensitive consumer applications where good per-
– Soft Mute formance is required.
– Digital Loopback The PCM3002 programmable functions are controlled
– Four Alternative Audio Data Formats by software. The PCM3003 functions, which are
Sampling Rate: 4 kHz to 48 kHz controlled by hardware, include de-emphasis,
power-down, and audio data format selections.

Single 3-V Power Supply

Small Package: SSOP-24

Lch In Digital Digital Out

Delta-Sigma Decimation
Analog Front-End Serial Interface
Modulator Filter
Rch In and
* Mode Control
Digital In

Lch Out Low-Pass Filter Multilevel Digital Mode Control

Rch Out and Delta-Sigma Interpolation System Clock
Output Buffer Modulator Filter B0006-01
* PCM3002 Only

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not Copyright © 2000–2004, Texas Instruments Incorporated
necessarily include testing of all parameters.
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted
PCM3002 PARAMETER
PCM3003
DIGITAL INPUT/OUTPUT
Input Logic
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
VIH (1) (2) (3) www.ti.com
VIL (1) (2) (3)
IIN (2)
IIN (1) (3)
VOH (4) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
VOL (4)
VOL (5) circuits be handled with appropriate precautions. Failure to observe proper handling and installation
CLOCK FREQUENCY procedures can cause damage.
fs ESD damage can range from subtle performance degradation to complete device failure. Precision
Sampling
integrated frequency
circuits may be more susceptible to damage because very small parametric changes could
cause the device not256 tofSmeet its published specifications.
System clock frequency
ADC CHARACTERISTICS
Resolution
DC Accuracy
Gain mismatch, channel-
to-channel
Gain error
Gain drift
Bipolar zero error
Bipolar zero drift
Dynamic
Performance (8)
THD+N
Dynamic range
Signal-to-noise ratio
Channel separation
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Output Logic
(8)
2
VIN = –0.5 dB
VIN = –60 dB
A-weighted
A-weighted
86
86
84
–86
–28
90
90
88
–80
dB
dB
dB
dB
High-pass filter
bypassed (7)
High-pass filter bypassed (7)
±1
±2
±20
±1.7
±20
±3
±5
% of FSR
% of FSR
ppm of FSR/°C
% of FSR
ppm of FSR/°C
20
Bits
384 fS
Pins 7, 8, 17 and 18: RST, ML, 512MD,
fS and MC for the PCM3002; PDAD, PDDA, DEM1, and DEM0 for PCM3003 (Schmitt-trigger input
with 100-kΩ typical internal pulldown resistor)4 (6)
Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-trigger input)
1.024
Pin 16: 20BIT for PCM3003 (Schmitt-trigger1.536 input, 100-kΩ typical internal pulldown resistor)
Pin 12: DOUT 2.048
Pin 16: ZFLG for PCM3002 (open-drain output) 44.1
See Application Bulletin SBAA033 for information relating11.2896to operation at lower sampling frequencies.
High-pass filter for offset cancel 16.9344
fIN = 1 kHz, using the System Two™ audio measurement system by Audio Precision™ in rms mode with 20-kHz LPF, 400-Hz HPF used
22.5792
for performance calculation. 48
12.288
18.432
24.576
MHz
kHz
Output logic level
Input logic level
Input logic current
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted
PCM3002
PARAMETER
PCM3003
Digital Filter Performance
Pass band
www.ti.com
Stop band– OCTOBER 2000 – REVISED OCTOBER 2004
SBAS079A
Pass-band ripple
Stop-band attenuation
Delay time
HPF frequency response
Analog Input
Voltage range
Center voltage
Input impedance
Antialiasing filter frequency
response
DAC CHARACTERISTICS
Resolution
DC Accuracy
Gain mismatch, channel-
to-channel
Gain error
Gain drift
Bipolar zero error
Bipolar zero drift
Dynamic
Performance (9)
THD+N
Dynamic range
Signal-to-noise ratio
Channel separation
Digital Filter Performance
Pass band
Stop band
Pass-band ripple
Stop-band attenuation
Delay time
Analog Output
Voltage range
Center voltage
Load impedance
LPF frequency response
(9)
AC coupling
f = 20 kHz
10
–0.16
0.6 VCC
0.5 VCC
Vp-p
VDC
kΩ
dB
–35
11.1/fS
0.555 fS
±0.17
0.445 fS
Hz
Hz
dB
dB
s
VOUT = 0 dB (full scale)
VOUT = –60 dB
EIAJ, A-weighted
EIAJ, A-weighted
88
88
86
–86
–32
94
94
91
–80
dB
dB Precision in rms mode with 20-kHz LPF, 400-Hz HPF used
fOUT = 1 kHz, using the System Two audio measurement system by Audio
for performance calculation. dB
dB
±1
±1
±20
±2.5
±20
±3
±5
% of FSR
3
% of FSR
ppm of FSR/°C
% of FSR
ppm of FSR/°C
20
Bits
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted
PARAMETER
POWER SUPPLY REQUIREMENTS
VCC, VDD
Supply voltage
Supply current
–25°C to 85°C
0° C to 70°C (10)
Operation, VCC = VDD = 3 V
Power down, VCC = VDD = 3 V
Operation, VCC = VDD = 3 V
Power dissipation
TEMPERATURE RANGE
TA
Tstg
JA
Operation
Storage
Thermal resistance
–25
–55
100
85
125
°Χ
(10) Applies for voltages between 2.4 V and 2.7 V for 0°C to 70°C and 256 fS/512 °Χ
fS operation (384 fS not available)
(11) SYSCLK, BCKIN, and LRCIN are stopped. °Χ/Ω
Power down (11), VCC = VDD =
3V
PACKAGE/ORDERING INFORMATION 2.7
PRODUCT 2.4
PCM3002E 3
PCM3003E 3
PACKAGE 18
TYPE 50
24-pin SSOP 54
24-pin SSOP 150
PACKAGE 72
CODE 3.6
DB 3.6
DB 24
PACKAGE VDC
MARKING VDC
ABSOLUTE PCM3002E MAXIMUM RATINGS mA
Supply voltage VDD, VCC1, VCC2
PCM3003E ∝Α
Supply voltage differences ORDERING mW
GND voltage differences NUMBER ∝Ω
Digital input voltage PCM3002E CONDITIONS
Analog input voltage PCM3002E/2K PCM3002E/3003E
Power dissipation PCM3003E MIN
Input current (any pinsPCM3003E/2K
except supplies) TYP
Operating temperature TRANSPORT MAX
Storage temperature MEDIA UNITS
Lead temperature, soldering Rails
Package temperature (IR reflow, peak)
Tape and reel
Rails –0.3 V to 6.5 V
Tape and reel ±0.1 V
QUANTITY ±0.1 V
58 –0.3 V to VDD + 0.3 V, < 6.5 V
2000 –0.3 V to VCC1, VCC2 + 0.3 V, < 6.5 V
58 300 mW
2000 ±10 mA
–25°C to 85°C
–55°C to 125°C
260°C, 5 s
235°C

4
 PCM3002
PCM3003
www.ti.com
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range
MIN
Analog supply voltage, VCC1, VCC2 NOM MAX UNIT
Digital supply voltage, VDD 3 3.6 V
Analog input voltage, full scale (–0 dB) 2.7 3 3.6 V
Digital input logic family 2.7 1.8 Vp-p
Digital input clock frequency VCC = 3 V CMOS
Analog output load resistance System clock
Analog output load capacitance Sampling clock
Digital output load capacitance 8.192
Operating free-air temperature, TA 32 24.576 MHz
PCM3002 10 48 kHz
(TOP VIEW) 30 kΩ
10 pF
PIN ASSIGNMENTS—PCM3002 pF
NAME
AGND1
AGND2
BCKIN –25 85 °Χ
DGND PCM3003
DIN (TOP VIEW)
DOUT 24
LRCIN 23
MC 22
MD 21
ML VCC1 1 20 VCC2 VCC1 1 24 VCC2
RST 2 19 2 23
VCC1 AGND1 VCC1 AGND1
SYSCLK 3 18 3 22
VCC1
VINR 17
AGND2 VINR AGND2
VREF1 4 VCOM VREF1 4 21 VCOM
VCC2 5 16 5 20
VCOM VREF2 6 15 VOUTR VREF2
6 19
VOUTR
VDD VINL 14 VOUTL VINL VOUTL
7 7 18
(1) RST 13 MC PDAD DEM0
8 8 17
(2) ML 9 MD PDDA 9 16 DEM1
PIN SYSCLK 10 ZFLG SYSCLK 10 15 20BIT
23 LRCIN 11 DIN LRCIN 11 14 DIN
22 BCKIN 12 VDD BCKIN 12 13 VDD
11 DOUT DGND DOUT DGND
13 P0004-02

15
12
10
18
17
8
7
9
1, 2
24
21
14
I/O
–
–
I
–
I
O
I
I
I
I
I
I
–
–
–
–
ADC analog ground
DAC analog ground
Bit clock input (1)
Digital ground
Data input (1)
Data output
Sample rate clock input (fs) (1)
Bit clock for mode control (1) (2)
Schmitt-trigger input
Serial data for mode controlpulldown
(1) (2)
With 100-kΩ typical internal resistor
Strobe pulse for mode control (1) (2)
5
Reset, active LOW (1) (2)
System clock input (1)
ADC analog power supply
DAC analog power supply
ADC/DAC common
Digital power supply
DESCRIPTION