Esquema Eletrico CI S1a0071x
Esquema Eletrico CI S1a0071x
Esquema Eletrico CI S1a0071x
Data Sheet
(Rev. 1.0)
for S1A0071
Audio Processor
for Class-D Power AMP
CONTENT
1. INTRODUCTION .................................................................................................... 3
2. BLOCK DIAGRAM................................................................................................. 4
7. TEST CIRCUIT..................................................................................................... 13
9. APPLICATION NOTE........................................................................................... 15
1. INTRODUCTION
The S1A0071 is an Audio processor for Class D-type audio amplifier, will help you to make more
easier the class D type audio amplifier and sound system. This is designed by the Cool Power
TM
Processing (CPP ) technology. The CPP have a characteristic of high fidelity and high power
efficiency.
◎ OVERVIEW
○ Sound Processing : CPPTM (Cool Power Processing) Class-D Architecture
○ Audio Sound Processor : Voltage Amp, Current Amp, And Feed Back Amp
○ System Support Circuit : Protection, Mute, Digital Logic
○ High Speed Comparator, Logic Buffer include
◎ FEATURE
○ For Audio Power Amplifier
○ Operating Voltage ( Driver Supply ) : ± 5.0V ~ ± 6.0V
○ External MOSFET Supply Voltage Range : ± 10V ~ ± 45V Usable
○ Wide Output Power Compatibility : 10W ~ 200W
○ High Fidelity : 10W @ 4Ω, 0.01% THD+N
5W @ 8Ω, 0.008% THD+N
○ High Efficiency : 83% @ 70W, 4Ω, THD+N < 10%,VCCP= ±25V
: 91% @ 40W, 8Ω, THD+N < 10%,VCCP= ±25V
○ Wide Bandwidth : 1 ~ 80KHz @ 8Ω
○ Dynamic Range : 105dB @ 100W Amp
○ Damping Factor : more than 300
○ Output Noise Voltage : 120μV @ AES17, A-weighted Filter, Input Grounded
○ Very Low Pop Noise When Power on/off
○ Mute Function Without Pop Noise
○ Enable to Set Output Soft Clipping Level
○ Enable to Set P-MOS & N-MOS On-Time Delay Independently
○ Protections: Internal Thermal Protection
Output Over Current Protection
Output Short Protection (Output to VCCP, Output to GND, Output to VSSP)
○ Protection Operating Monitor Output Pin: Direct LED Drive Enable
○ 48TSSOP Package
2. BLOCK DIAGRAM
4. PIN DESCRIPTION
5. ELECTRIC CHARATERISTICS
ELECTRICAL CHARACTERISTICS
Ta = 25°C, Vi = 0.3Vrms, f = 1kHz, VCC = 5V, VSS = -5V, RL = 4Ω,
Vc = 1.0V, Power Supply Voltage (VCCP, VSSP) = ± 30V
6. Typical Performance
±VCCP = ±25V ±VCCP = ±30V ±VCCP = ±35V ±VCCP = ±40V ±VCCP = ±45V
±Vcc = ±5V ±Vcc = ±5V ±Vcc = ±5V ±Vcc = ±5V ±Vcc = ±5V
f = 1kHz f = 1kHz f = 1kHz f = 1kHz f = 1kHz
BW = 22Hz~ 20kHz BW = 22Hz~ 20kHz BW = 22Hz~ 20kHz BW = 22Hz~ 20kHz BW = 22Hz~ 20kHz
RL = 4Ω RL = 4Ω RL = 4Ω RL = 4Ω RL = 4Ω
AES 17FILTER AES 17FILTER AES 17FILTER AES 17FILTER AES 17FILTER
From the above measure data, the user can make an audio amplifier system with S1A0071 for several
conditions. For example, if user want to make a class D type audio amplifier with specification like as
0.1% 50W system and load impedance 4Ω. User just setup the power supply and small quality of
resistor and capacitor, FET drive and FET switch for this, and you can make a 0.1% 50W 2Channel as
faster and easily. If you want to make a audio amplifier like as THD+N <1%, 200W 2Channel system,
user can get the system quickly. Also user can make a 5.1Channel with S1A0071 3EA as easily.
Typical Performance
±VCCP = ±25V
±VCCP ±25V
=
±Vcc = ±5V
±Vcc ±5V
=
f = 1kHz
f =
1kHz
BW = 22Hz ~
BW =
22Hz
20kHz
20kHz
RL = 4Ω
RL = 8Ω
AES 17FILTER
AES 17FILTER
Typical Performance
±VCCP = ±25V ±VCCP = ±25V
±Vcc = ±5V ±Vcc = ±5V
Po = 10W Po = 5W
RL = 4Ω RL = 8Ω
BW = 22Hz ~ 30KHz
BW = 22Hz ~ 22KHz
BW = 22Hz ~ 30KHz
BW = 22Hz ~ 22KHz
Typical Performance
±VCCP = ±25V ±VCCP = ±25V
±Vcc = ±5V ±Vcc = ±5V
Po = 1W Po = 10W
f = 1kHz f = 1kHz
BW = 22Hz ~ BW = 22Hz ~
22kHz 22kHz
0dBr = 17V 0dBr = 17V
RL = 4Ω RL = 4Ω
Typical Performance
Po = 5W, RL = 8Ω
Po = 10W, RL = 4Ω
±VCCP = ±25V
RL = 8Ω ±Vcc = ±5V ±VCCP = ±25V
±Vcc = ±5V
AES 17FILTER
Po = 0W
RL = 4Ω THD+N < 10%
BW = 22Hz~22kHz
RL = 4Ω
PSRR +
PSRR -
7. TEST CIRCUIT
8. APPLICATION CIRCUIT
9. APPLICATION NOTE
Note 1
The OPT [Active high] controls the power on mute function [referred to Note 7]. User can prevent the
unstable operation by using this pin and use can use this signal to prevent the POP noise during the
power-on time.
Note 2
The OSCEN pin controls the direction of OSC pin because OSC has a bidirectional operation. The
S1A0071 has a built-in triangle oscillator, so user can selectable to use the internal oscillator or
external oscillator. If user wants to internal oscillator, the OSCEN pin connects to VCC then OSC is
output port and used to detect the internal oscillation waveform. If user want to make an amplifier with
three or more channels set, at this case, user muse be careful to make a system, specially the setting
of oscillator frequency, because when user can use the each independent internal oscillators
configuration, the system can be generated from mixed modulation resulting from the frequency
deviation between oscillators in each chip, respectively. In such case, the oscillator in one of the IC’s
must be MASTER, shared with the other IC’s oscillator signal, and the oscillator in the other IC’s must
disabled by the use of the OSCEN pin (SLAVE mode). Then, the OSCEN pin of MASTER ICs is
connected to VCC (or Open) and the OSCEN pin of the other IC (Slaves) must be grounded (GND),
and the SIO pins must be connected to each other. As you can see the Figure 1, the oscillator signal
of the MASTER IC provides the triangle wave to the Slave ICs.
OSCEN
OSCEN
SIO
SIO
SIO
VCC
heard any more. This operation can be use as protection condition. So MUΤΕ pin is also used for
external protection. S1A0071 has internal protection circuit. However, if user want to add a special
protection circuit to the set, the output of the added circuit which is active low is directed to the
Note 4
The internal gain of S1A0071 is 26dB. (Condition: R1 = R2)
When user wants to get a high gain system, User can do this by changing the values of R1 and R2.
In this case, the Total Gain can be obtained as follows:
R2
GAINtotal (dB ) = 20 × Log + 26
R1
If the values of R1 and R2 are very high, it will expect the DC offset and if the values of R1 and R2 are
very low, then the THD+N value is high on high power system. By an appropriate R1 and R2 selection,
you can minimize the DC offset and get the good the THD+N characteristics.
Note 5
In the application circuit, the resistor Rp connected to the PDCTR and the resistor Rn connected to
NDCTR pins. User can adjust these resistors values to control the ON time delays of P-MOSFET and
N-MOSFET. Because there is a turn-on delay time and rising time and falling time, turn-off delay time
of each MOSFET drive, so user must set the on time delay for each P-MOSFET and N-MOSFET to
prevent arm-short situation. Also more important, the Rp and Rn selection affect the sound quality and
amplifier efficiency, so user should be select appropriate value.
Designed rule of S1A0071, the gate off time minimized and the ON time can be variable so that user
can set the overlap time externally. The PDCTR pin and NDCTR pin voltages are generally set to that
of VB (pin 22) and the flowing current, controlled by the values of Rp and Rn connected externally, can
be used to delay the internal gate ON time. The recommended current range is 10Kohm to 200Kohm,
from which one can select the appropriate current according to the selected output MOSFET and
circuit configuration.
As the resistances increase, ON time is further delayed. Rp and Rn can set the ON time delays of P-
MOSFET and N-MOSFET, respectively.
160
140
120
Dead-Time[nS]
100
80
60
40
20
0
40 60 80 100 120 140 160 180 200 220 240
Rp&Rn (kΩ)
Note 6
The Vc ( DC Voltage of carrier frequency) sets the oscillation level of the triangle oscillator. The
internal oscillation frequency is set to about 450kHz, independent of the oscillation level, an important
factor that sets the conversion gain from the internal comparator to the speaker. Based on the input Vc,
the oscillation level is set to approximately ± Vc (Vp-p), and can be monitored at the SIO (Pin3).
It is acceptable to make Vc voltage from the external voltage source; however, we recommend making
the Vc voltage from the regulated voltage VB (Pin22) divided by Ra and Rb. If Vc is used with the
capacitor to prevent noise input, a circuit with better characteristics can be configured.
2 × VB × Rb
VC (VP − P ) = : VB = 3.05V with VCC = 5V, VSS = -5V
( Ra + Rb)
To get the high THD characteristics, the gain of S1A0071 is designed as 26dB and the application
circuit use the ± 30V for main power and the 0.8V for Vc. The ratio of main power divide Vc relate a
amplifier gain, so if user want to get the high power and increase the main power, then user must
re-setup the Vc values. We recommended as below value for user's application.
Note 7
When power is turned on, the circuit operates unstably, possibly generating noise. To prevent
this unstable situation, the S1A0071 use the CDLY pin (pin# 24), which can be connected to a
capacitor. This CDLY pin used to generate a slight time delay from power up to when the
circuit starts to operate normally. The CDLY pin drive’s capacity is about 1.0㎂ and the mute
mode sustains until the externally connected capacitor charges to a voltage equal about VB
(pin 22). The time delay can be calculated as follows:
VC × C 3× C
Tdly (sec) = + Ta = + Ta ≅ 3.0 E 6 × C (Ta « Tdly)
I 1.0μ
Ta is the internal processing time that used in the removal of circuit settling time and other
pop noises. Tdly also decides the protection restart time. Among the protection functions in
S1A0071, those that remove "causes" (Thermal Protection, Over Current Protection) oscillate
from normal operation → protection → normal operation → protection → … , generating
very fast blocking oscillation. The Tdly decides (delays) the repeat cycle of the oscillation,
which protects the circuit and controls unstable operations. Those protection functions
(Output DC Short) that do not remove "causes" are not affected by Tdly, and once the cause
has been removed, they return to normal operation.
Note 8
S1A0071 has a built-in limiting block at the input stage that remove noise signal that may be
generated by discontinuous feedback and also this limit block operate as a clipping circuit due
to over-input signal. When a specific voltage (± Vls) is applied to VLP and VLN, the soft
clipping function starts to operate on the input whose value lie outside the ± Vls range, on the
basis of the Pre Amp output with its gain set by R1 and R2. As a result, the entire circuit is
enabled to drive only the signals that lie within the operating range, thus maintaining a
continuous feedback loop which allows the circuit to output a soft clipped output waveform
even for an input lying outside the output dynamic range.
Vls must be set differently according to the MOSFET power supply voltage and power supply
impedance, and MOSFET ON resistance. If we assume that the power supply impedance is
ideal (= 0) and MOSFET ON resistor is ideal (0 Ohm), the appropriate values for Vls values on
the power supply voltage (VCCP, VSSP) would be as follows:
(This value is obtained by dividing MOSFET power supply voltage with Rx and Ry. Considering the
speaker load resistance and power supply impedance, Vls (soft clipping level) is generated. So,
VLN/VLP accepts this value, and then stable operation is expected.)
To decide on the actually appropriate Vls, you must monitor the output waveform at the set connected
to the power supply. You can set Rx and Ry to values that will make VLP and VLN generate maximum
waveforms, respectively; within the range that has no clipping distortion and other noises. If you don't
want to operate the soft clipping function, connect VLN and VLP pins to VCC and VSS.
♦ FET DRIVER
S1A0071 produces an output of 4.5Vp-p and low level is VSS. Any GATE BUFFER ICs can satisfy
these conditions, but they should be designed as FAIR to optimally use with S1A0051, a MOSFET
DRIVER
0.05
MIN
0.002
1.00 + 0.05
0.039 + 0.002
#1 #48
0.020
0.50
+ 0.003
- 0.001
+ 0.07
- 0.03
0.492 + 0.004
12.50 + 0.10
0.0078
0.20
TYP
0.020
0.50
#24 #25
1.20
MAX
0.047
6.10 + 0.10
0.005 + 0.003
0.240 + 0.004
+ 0.07
- 0.001
0.127 - 0.03
+0.15
8.10
0.60 -0.10 0.319
+0.006
0.024 -0.004