Ordering number: ENA1997

Bi-CMOS IC
LV4924VH Class-D Audio power Amplifier
Power cell BTL 10W×2ch
Overview
The LV4924VH is a 2-channel full-bridge driver for digital power amplifiers. It requires a PWM modulator IC in the
previous stage. This IC is a power cell that takes in PWM signals as an input and is used to form a digital amplifier system
for TVs, amusement equipment, and other such systems.

Features
• BTL output, class D amplifier system
• High-efficiency class D amplifier
• Muting function reduces impulse noise at power on / off
• Protection circuits incorporated for over-current, thermal, supply voltage drop, output offset detector
• Built-in bootstrap diodes

Specification
• Output 15W (VD=16V, RL=8Ω, fIN=1kHz, AES17, THD+N=10%)
• Output 10W (VD=13V, RL=8Ω, fIN=1kHz, AES17, THD+N=10%)
• Efficiency : 89% (VD=13V, RL=8Ω, fIN=1kHz, PO=10W)
• THD+N : 0.1% (VD=13V, RL=8Ω, fIN=1kHz, PO=1W, Filter: AES17)

Maximum Ratings / Absolute Maximum Ratings /Ta=25°C

Parameter Symbol Conditions Ratings Unit
Maximum supply voltage VD Externally applied voltage 22 V
Maximum PWM pin voltage VIN PWM_A1,PWM_A2,PWM_B1,PWM_B2 6 V
Maximum pull-up pin voltage Vpup max NPN Open collector pin 20 V
Allowable power dissipation Pd max Exposed Die-pad Soldered *1 4.6 W
Maximum junction temperature Tj max 150 °C
Operating temperature Topr -25 to 75 °C

Storage temperature Tstg -50 to 150 °C

*1 Customer bread board rev.1.0: 90.0mm × 70.0 mm × 1.6 mm (two-layer) Material: glass epoxy

Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment. The products mentioned herein
shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,
aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system,
safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives
in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any
guarantee thereof. If you should intend to use our products for new introduction or other application different
from current conditions on the usage of automotive device, communication device, office equipment, industrial
equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the
intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely
responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer ' s products or
equipment.

N1611 SY 20111031-S00002 No.A1997-1/15

 LV4924VH
Recommended Operating Range at Ta = 25°C
Ratings
Parameter Symbol Conditions Unit
min typ max
Recommended supply voltage VD Externally applied voltage 9 13 20 V
range
Recommended PWM pin voltage VIN PWM_A1,PWM_A2,PWM_B1,PWM_B2 0 3.3 5 V
Recommended pull-up supply Vpup NPN Open collector pin - - 18 V
voltage
Recommended load resistance RL Speaker load 4 8 - Ω

Electrical Characteristics Ta=25°C, VD=13V, RL=8Ω, L=22μH (TOKO: A7040HN-220M), C=0.33μF (Matsuo: 553M6302-334K)
Ratings
Parameter Symbol Conditions Unit
min typ max
Quiescent current ICCO STBY=H, MUTE=H, fIN=384kHz, Duty=50% 30 38 45 mA
Current at MUTE Imute STBY=H, MUTE=L, VIN=GND 2 4 6 mA
Standby current Ist STBY=L, MUTE=L, VIN=GND - - 10 μA
H input voltage VIH PWM_A, PWM_B, STBY, MUTE 2.3 - 5.5 V
L input voltage VI L PWM_A, PWM_B, STBY, MUTE 0 - 1.0 V
H input current I IH VIN=5V - - 60 μA
L input current IIL VIN=GND -20 - - μA
NPN Open collector output
Output pin leakage current IOFF - - 1 μA
OFF-stage 5.0V pull-up
NPN Open collector output
Output pin current IOL 0.5 - - mA
ON-stage, VOL=0.4V
*1
Power Tr ON resistance Rds ON Id=1A - 220 - mΩ
Turn ON delay time td ON fIN=384kHz, Duty=50% - 30 50 ns
Turn OFF delay time td OFF fIN=384kHz, Duty=50% - 30 50 ns
Rise-up time tr fIN=384kHz, Duty=50% - 5 20 ns
Fall time tf fIN=384kHz, Duty=50% - 5 20 ns
*1 : The maximum power transistor ON resistance(RDSON) is 270mΩ(design guarantee value).
Note : The value of these characteristics were measured in SANYO test environment. The actual value in an end system will vary depending on the printed
circuit board pattern, the components used, and other factors.

Electrical Characteristics
(Reference value: The table below shows the reference value when FPGA equivalent to the Sanyo reference model is used.)
Ratings
Parameter Symbol Conditions Unit
min typ max
Output 1 PO1 THD+N=10%, fIN=1kHz, AES17 - 10 - W
Output 2 PO2 VD=16V, THD+N=10%, fIN=1kHz, AES17 - 15 - W
Total harmonic distortion THD+N PO=1W, fIN =1kHz, AES17 - 0.1 - %
Note : The value of these characteristics were measured in SANYO test environment. The actual value in an end system will vary depending on the printed
circuit board pattern, the components used, and other factors.

Audio data PWM BD-mode

IIS
MCLK MCLK

BCLK BCLK

LRCLK FPGA LRCLK LV4924VH

SDATA SDATA

No.A1997-2/15
 LV4924VH
Package Dimensions
unit : mm (typ)
3417

TOP VIEW BOTTOM VIEW

15.0

36

(4.7)

7.6
5.6

(3.5)
0.5
12
1.625 0.22 0.2
0.65
(0.68)
1.7 MAX

SIDE VIEW
(1.5)

2.17
0.05

SANYO : HSSOP36(275mil)

Pin Assignment

BOOT_CH2_P
BOOT_CH2_N
BOOT_CH1_P

BOOT_CH1_N

OUT_CH2_P

OUT_CH2_P
OUT_CH2_N
OUT_CH1_P

OUT_CH1_P

OUT_CH2_N
OUT_CH1_N

OUT_CH1_N

VDDA2
VDDA1

PVD2
PVD1

PVD1

PVD2
36 35 34 33 32 31 30 29 28 GND 27 26 25 24 23 19 20 21 22

LV4924VH

1 2 3 4 5 6 7 8 9 GND 10 11 12 13 14 15 16 17 18
MUTE

SOS
STBY

NC1

NC2

PWM_B1
NC3

PWM_A1
NC4

PWM_B2

PWM_A2

NC5

NC6

NC7

NC8

NC9

NC10

NC11

Top view

No.A1997-3/15
 LV4924VH
Reference data for thermal design

Overall view of substrate

Mounted on a specified board (Customer bread board rev.1.0): 90.0mm × 70.0 mm × 1.6 mm (two-layer) Material: glass epoxy

Pd max-Ta

Pd max -- Ta
6
Specified board : 90.0 × 70.0 × 1.6mm3
Allowable power dissipation, Pd max -- W

glass epoxy
5
Exposed Die-Pad
Soldered
4.6

4
Exposed Die-Pad
Not Soldered
3.2
3
2.7

2
1.9

0
--25 0 25 50 75 100
Ambient temperature, Ta -- C

1. Data of the Exposed Die-Pad (heat spreader) substrate as mounted represents the value in the state where the exposed
Die-Pad surface is wet for 90% or more.
2. For the set design, derating design should be made while ensuring allowance.
Stresses to become an object of derating are the voltage, current, junction temperature, power loss and mechanical
stresses including vibration, impact and tension.
Accordingly, these stresses must be as low or small as possible in the design.
Approximate targets for general derating are as follows:
(1) Maximum value 80% or less for the voltage rating.
(2) Maximum value 80% or less for the current rating.
(3) Maximum value 80% or less for the temperature rating.

3. After set design, be sure to verify the design with the product.
Also check the soldered state of the Exposed Die-Pad, etc. and verify the reliability of the soldered joint.
If any void or deterioration is observed in these sections, thermal conduction to the substrate is deteriorated, resulting in
thermal damage of IC.

No.A1997-4/15
 LV4924VH
Block Diagram

GND

GND

Pin Equivalent Circuit

Pin No. Pin name I/O Description Equivalent Circuit
1 STBY I Standby mode control
PVD

GND

2 MUTE I Muting control PVD VDDA

GND

Continued on next page.

No.A1997-5/15
 LV4924VH
Continued from preceding page.
Pin No. Pin name I/O Description Equivalent Circuit
3 SOS I Internal protection circuit detection output (OR output of the PVD
thermal detection, over-current, voltage drop protection,
offset detection circuit) of an NPN open collector output type
3

GND

4 NC1 - Non connection

5 NC2 - Non connection
6 NC3 - Non connection
7 NC4 - Non connection
8 PWM_A1 I PWM input (plus input) of OUT_CH1_P
PVD VDDA
9 PWM_B1 I PWM input (negative input) of OUT_CH1_N
10 PWM_B2 I PWM input (negative input) of OUT_CH2_N
11 PWM_A2 I PWM input (plus input) of OUT_CH2_P

GND

FIN GND - ground

12 NC5 - Non connection
13 NC6 - Non connection
14 NC7 - Non connection
15 NC8 - Non connection
16 NC9 - Non connection
17 NC10 - Non connection
18 NC11 - Non connection
19, 20 PVD2 - Power pin
21, 22 OUT_CH2_P O Output pin, Channel 2 plus
PVD
26, 27 OUT_CH2_N O Output pin, Channel 2 minus
28, 29 OUT_CH1_N O Output pin, Channel 1 minus
33, 34 OUT_CH1_P O Output pin, Channel 1 plus

GND

23 BOOT_CH2_P I/O Bootstrap I / O pin, channel 2 plus

24 VDDA2 O Internal power supply decoupling capacitor connection
25 BOOT_CH2_N I/O Bootstrap I / O pin, channel 2 minus
30 BOOT_CH1_N I/O Bootstrap I / O pin, channel 1 minus
31 VDDA1 O Internal power supply decoupling capacitor connection
32 BOOT_CH1_P I/O Bootstrap I / O pin, channel 1 plus
35, 36 PVD1 - Power pin

No.A1997-6/15
 LV4924VH
Description of functions

System Standby
The built-in 5V regulator is turned ON / OFF by changing over "H" and "L" of "STBY". The regulator is turned OFF
with "STBY" at "L" and ON with "STBY" at "H".
This signal also causes initialization of the internal logic initialization with "L" and the normal mode with "H".

MUTE Function
The MUTE function is mainly for muting of the output and for reduction of pop noise at power ON.

Muting the output

The output PWM can be turned ON / OFF by changing over "H" and "L" of "MUTE". The PWM output is stopped
(putting all of PWM outputs at high impedance) with "MUTE" at "L" and enters the normal operation mode with
"MUTE" at "H".

Sequence at power ON
To reduce the pop noise, turn ON power supply while controlling in the following timing (PWM=BD mode).
In particular, all of inputs of PWM must be held at "L" at canceling of MUTE function.

* Please observe the following items for the destruction prevention of the output transistor.
(1) Under all conditions must control the period at the "H" level about the PWM input so as not to become more than
200μs when period of the "H" level MUTE and STBY signals both.

No.A1997-7/15
 LV4924VH
Sequence at power OFF
To reduce the pop noise, turn OFF power supply while controlling in the following timing (PWM=BD mode).

Protection Circuit
LV4924VH incorporates the over-current protection circuit, thermal protection circuit, supply voltage drop protection
circuit and output offset detection protection circuit. Activation of any one of these circuits causes the SOS output pin
to become active and thus "L".

Over-current protection circuit

This circuit is a protection circuit* to protect the output transistor from the over-current and compatible with any mode
of lightning, ground fault, and load short-circuit.
Protection is done when the detection current value (about 6A) set inside IC is reached, forcing the output transistor to
remain OFF for about 20μs. After forced OFF, the transistor returns automatically to the normal operation and performs
protection again if the over-current continues to flow.

Output Current

Control Self-recovery &

Operation Normal Operation

Internal Control Signal

* The over-current protection circuit functions only to avoid the abnormal state, such as output short-circuit, etc.,
temporarily, and does not guarantee to offer the protection to prevent damage to IC.

No.A1997-8/15
 LV4924VH
Thermal protection circuit
This circuit detects the temperature (150°C or more) inside LSI for protection. While this protection circuit is active,
the output Tr is turned OFF on both high- and low-sides, putting the output in the high-impedance state. This operation
is also provided with the hysteresis.

Supply voltage drop protection circuit

To avoid unstable operation at low voltages, this circuit monitors the PVD pin voltage and turns ON the amplifier when
this voltage exceeds the Attack voltage (VD = 7V typ.). In addition, to avoid unstable operation when the PVD pin
voltage has dropped because of certain reasons, the Recover voltage (VD = 6V typ.) is set. Both Attack and Recover
voltages have the hysteresis (about 1V) to prevent continuous ON / OFF operation of the supply voltage drop
protection circuit.

PVD Pin Voltage

Recovery Voltage

Internal
Control
Signal

Output offset detection protection circuit

This circuit is a protection circuit intended to alleviate burn of the loudspeakers when DC outputs to the BTL output for
a certain period or more.
The circuit detects the case in which each BTL input of each channel continues to disagree (for about 300ms), turns
OFF the output Tr on both high- and low-sides, and puts the output in the high-impedance state.

No.A1997-9/15
 LV4924VH
Application Circuit

GND

GND

* SOS of pin 3 is the open collector output.

Therefore, to monitor this output with CPU, it is necessary to pull up (resistor: R1) at power supply of CPU, etc.
When the output is not to be used (not to be monitored), it is not necessary to pull-up the resistor.

No.A1997-10/15
 LV4924VH
Characteristics Data: L=22μH (TOKO: A7040HN-220M), C=0.33μF (Matsuo: 553M6302-334K)
Ist -- VD Ipd -- Ta
0.3 0.3
V D =13V, RL=8
IN=Low, STBYB=Low
MUTEB=Low
Standby current, Ist - A

Standby current, Ist - A

0.2 0.2

0.1 0.1

0 0
0 2 4 6 8 10 12 14 16 18 20 22 24 -40 -20 0 20 40 60 80 100 120
Supply voltage, VD - V Ambient temperature, Ta - C
IMUTE -- VD IMUTE -- Ta
8 8
RL=8 , IN=Low V D =13V, RL=8
7 STBYB=High, MUTEB=Low 7 IN=0, STBYB=High
MUTEB=Low
Muting current, Imute - mA

Muting current, Imute - mA

6 6

5 5

4 4

3 3

2 2

1 1

0 0
4 6 8 10 12 14 16 18 20 22 -40 -20 0 20 40 60 80 100 120
Supply voltage, VD - V Ambient temperature, Ta - C
Icco -- VD Icco -- Ta
70 70
RL=8 VD=13V, RL=8
IN=Duty50%[0 to 3.3V] IN=Duty50%[0 to 3.3V]
60 60
STBYB=High, MUTEB=High STBYB=High, MUTEB=High
Quiescent current, Icco - mA

Quiescent current, Icco - mA

50 50

40 40

30 30

20 20

10 10

0 0
4 6 8 10 12 14 16 18 20 22 -40 -20 0 20 40 60 80 100 120
Supply voltage, VD - V Ambient temperature, Ta - C
VDD1,2 -- VD VDD1,2 -- Ta
6 6
RL=8

5 5

4 4
VDDA1,2[V]
VDDA1,2[V]

3 3

2 2

1 1
VD=13V
RL=8
0 0
4 6 8 10 12 14 16 18 20 22 -40 -20 0 20 40 60 80 100 120
Supply voltage, VD - V Ambient temperature, Ta - C
No.A1997-11/15
 LV4924VH
td ON -- VD td ON -- Ta
60 60
VD=13V
RL=8
50 50
Turn ON delay time, td ON - nsec

Turn ON delay time, td ON - nsec

40 40

30 30

20 20

10 10

0 0
8 10 12 14 16 18 20 22 -40 -20 0 20 40 60 80 100 120
Supply voltage, VD - V Ambient temperature, Ta - C
td OFF -- VD td OFF -- Ta
60 60
VD=13V
RL=8
Turn OFF delay time, td OFF - nsec

50 50

Turn OFF delay time, td OFF - nsec

40 40

30 30

20 20

10 10

0 0
8 10 12 14 16 18 20 22 -40 -20 0 20 40 60 80 100 120
Supply voltage, VD - V Ambient temperature, Ta - C
tr -- VD tr -- Ta
30 30
VD=13V
RL=8
Rise-up time, tr - nsec

Rise-up time, tr - nsec

20 20

10 10

0 0
8 10 12 14 16 18 20 22 -40 -20 0 20 40 60 80 100 120
Supply voltage, VD - V Ambient temperature, Ta - C
tf -- VD CH sep. -- Ta
30 30
VD=13V
RL=8

20 20
Full time, tr - nsec

Full time, tr - nsec

10 10

0 0
8 10 12 14 16 18 20 22 -40 -20 0 20 40 60 80 100 120
Supply voltage, VD - V Ambient temperature, Ta - C

No.A1997-12/15
 LV4924VH
Efficiency -- Power Pd - Power
100 4

80
3
Efficiency - %

60

Pd - W
2

40

1
20

0 0
0 2 4 6 8 10 0 2 4 6 8 10
Power - W/ch Power - W/ch
Efficiency -- Power Pd - Power
100 5

80 4
Efficiency - %

60 3
Pd - W

40 2

20
1

0 0
0 3 6 9 12 15 0 3 6 9 12 15
Power - W/ch Power - W/ch
Power@THD+N+1% -- VD Power@THD+N+1% -- Ta
32 32
fIN=1kHz VD=13V
THD+N=1% fIN=1kHz
28 28
2CH-Drive THD+N=1%
AES17 RL=6 2CH-Drive
AES17
Power@THD+N=1% - W

Power@THD+N=1% - W

24 24

20 RL=4 20

16 16
RL=4
RL=8
12 12
RL=6
8 8
RL=8
4 4

0 0
8 10 12 14 16 18 20 22 -40 -20 0 20 40 60 80 100 120
Supply voltage, VD - V Ambient temperature, Ta - C
Power@THD+N+10% -- VD Power@THD+N+10% -- Ta
44 44
fIN=1kHz VD=13V
40 THD+N=10% 40 fIN=1kHz
2CH-Drive THD+N=10%
36 36
AES17 RL=6 2CH-Drive
Power@THD+N=10% - W
Power@THD+N=10% - W

32 32 AES17

28 28
RL=4
24 24

20 20
RL=8 RL=4
16 16
RL=6
12 12

8 8
RL=8
4 4

0 0
8 10 12 14 16 18 20 22 -40 -20 0 20 40 60 80 100 120
Supply voltage, VD - V Ambient temperature, Ta - C

No.A1997-13/15
 LV4924VH
THD+N -- Frequency THD+N -- Ta
100 100
VD=13V VD=13V
Total harmonic distortion, THD+N -- %

RL=8 RL=8

Total harmonic distortion, THD+N -- %

PO=1W fIN=1kHz
2CH-Drive PO=1W
10 AES17 10 2CH-Drive
AES17

1 1

CH1 CH1
0.1 0.1
CH2 CH2

0.01 0.01
10 100 1000 10000 100000 -40 -20 0 20 40 60 80 100 120
Frequency - Hz Ambient temperature, Ta - C
THD+N -- Frequency THD+N -- Ta
100 100
VD=16V VD=16V
Total harmonic distortion, THD+N -- %

RL=8 RL=8

Total harmonic distortion, THD+N -- %

PO=1W fIN=1kHz
2CH-Drive PO=1W
10 AES17 10 2CH-Drive
AES17

1 1

CH1 CH1
0.1 0.1 CH2
CH2

0.01 0.01
10 100 1000 10000 100000 -40 -20 0 20 40 60 80 100 120
Frequency - Hz Ambient temperature, Ta - C
THD+N -- Power THD+N -- Power
100 100
VD=13V VD=16V
Total harmonic distortion, THD+N -- %
Total harmonic distortion, THD+N -- %

RL=8 RL=8
2CH-Drive 2CH-Drive
AES17 AES17
10 10

1 1

fIN=100Hz fIN=100Hz
fIN=1kHz fIN=1kHz
0.1 0.1
fIN=6.67kHz fIN=6.67kHz

0.01 0.01
0.0001 0.001 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100
Power - W Power - W

No.A1997-14/15
 LV4924VH

SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.

This catalog provides information as of November, 2011. Specifications and information herein are subject
to change without notice.

PS No.A1997-15/15