MCQ Unit 2

MCQ COMPUTER ORGANIZATION
Unit 2 & 3 7. Which register keeps the track of instruction

1. The load instruction is mostly used to designate stored in memory.
a transfer from memory to a processor register is A. AR (Address register)
known as B. XR (Index register)
A. Instruction register C. PC (Program counter)
B. Program counter D. AC (Accumulator)
C. Accumulator ANSWER: C
D. Memory address register
ANSWER: C 8. Load is a type of
A. Data transfer instruction
2. Intel i360,SPARC,IBM Rs. 16,000 are the B. Data processing instruction
examples of C. Program counter instruction
A. CISC processor D. None
B. RISC processor ANSWER: A
C. IBM processor
D. Intel processor 9. Assembler syntax for index addressing mode is
ANSWER: B A. Ri B. (Ri)
C. X(Ri) D. Ri+
3. A stack computer evaliates arithmatic and ANSWER: D
other expressions using a format known as
A. Stack notation 10. Intel i860,motorola M88100 and AMD 29000
B. Polish notation are example of
C. Either A or B A. CISC architecture B. RISC architecture
D. None of these C. Both A and B D. None
ANSWER: B ANSWER: B
4. Control unit design based on sequential logic 11. Width of fraction bit in case of IEEE standard
circuit is called as of single precision is
A. Microprogrammed control unit A. 8 bit B. 11 bit
B. Hardwired control unit C. 52 bit D. 23 bit
C. GCD processor ANSWER: D
D. None of these
ANSWER: B 12. The delay elements are used in
A. State table method
5. NDRO means B. Sequence counter method
A. The method of reading the memory destroys C. Both A and B
stored information D. Delay element method
B. The method of reading the memory does not effect ANSWER: D
the stored data
C. Both A & B 13. Characteristics of CISC are
D. None of these A. More addressing mode, large set of instruction,
ANSWER: B few GPR's
B. Less addressing mode, large set of instruction, few
6. Byte addresses can be assigned across words GPR's
according to lower byte addresses are used for the C. More addressing mode, few set of instruction, few
more significant bytes of the word called as GPR's
A. Little-endian B. Big-endian D. Less addressing mode, few set of instruction, more
C. Neither A nor B D. Can't say GPR's
ANSWER: B ANSWER: A
Mr. Ritesh S. Dayama

14. Instruction cache and data cache are not 21. Addressing mode is
splited in case of A. Specification of opcode
A. CISC architecture B. Specification of operand
B. RISC architecture C. Specification of function
C. Both A and B D. All the above
D. None ANSWER: B
ANSWER: A
22. If the effective address is EA= [Ri] then he
15. Store is a type of type of addressing mode is
A. Data transfer instruction A. Immediate
B. Data processing instruction B. Index
C. Program counter instruction C. Direct
D. None D. Indirect
ANSWER: A ANSWER: D
16. In move M, R instruction, M is the memory 23. Hardware control unit design method is
and R is the register. The type of addressing mode A. Stae table method
is B. Delay element method
A. Absolute B. Indirect C. Sequence counter method
C. Register D. Index D. All of above
ANSWER: C ANSWER: D
17. Instruction format is variable in case of 24. Bitwise AND operation is a type of
A. CISC architecture A. Data transfer instruction
B. RISC architecture B. Data processing instruction
C. Both A and B C. Program counter instruction
D. None D. None
ANSWER: A ANSWER: D
18. Width of exponent field in case of IEEE 25. The assembler syntax for register based
standard for double precision is indirect addressing mode is
A. 11 bit B. 8 bit A. (Ri)
C. 52 bit D. 23 bit B. X (Ri)
ANSWER: A C. Ri
D. (Ri)+
19. The design method, which makes use of ANSWER: A
sequential cirsuit design is called
A. Delay element method 26. Intel i486, Motorola MC 68040 and NS 32532
B. Sequence counter method are examples of
C. State table method A. CISC architecture
D. All B. RISC architecture
ANSWER: C C. Both A and B
D. None
20. Assembly language format LDX is ANSWER: A
A. Data transfer instruction
B. Data processing instruction
C. Program control instruction
D. Logical instruction
ANSWER: A

27. Width of exponent field in case of IEEE 34. According to what address generated by
standard for single precision is program tends to be localized and can be
A. 11 bit predictable
B. 8 bit A. Locality of reference
C. 52 bit B. Spatial locality
D. 23 bit C. Temperal locality
ANSWER: B D. All of above
ANSWER: D
28. Design approach used in hardwired control is
A. State table method 35. Which unit issue control single to datapath
B. Delay element method A. Datapath unit
C. Sequence counter method B. Control unit
D. All C. ALU
ANSWER: D D. None of these
ANSWER: B
29. Instruction cache and data cache are splited in
case of
A. CISC architecture
B. RISC architecture
C. Both A and B
D. None
ANSWER: B
30. Function of I/O control instruction is

A. Moves data from one location to another
B. For performing arithmatic operation
C. For performaing logical operations
D. Move data from CPU to I/O devices
ANSWER: D
31. How many instructions are executed per

machine cycle in RISC
A. 1 B. 2
C. 3 D. 4
ANSWER: A
32. How many bits are there in product if n is

number of bits input in Booth's algo-
multiplication.
A. n B. 2n
C. 3n D. n*n
ANSWER: A
33. How many bits are there in single precision

format of floating point number?
A. 30
B. 64
C. 32
D. 33
ANSWER: C

MCQ Unit 2

Uploaded by

Copyright:

Available Formats

MCQ Unit 2

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MCQ Unit 2

Uploaded by

Copyright:

Available Formats

MCQ COMPUTER ORGANIZATION

Unit 2 & 3 7. Which register keeps the track of instruction

Mr. Ritesh S. Dayama

Mr. Ritesh S. Dayama

30. Function of I/O control instruction is

31. How many instructions are executed per

32. How many bits are there in product if n is

33. How many bits are there in single precision

Mr. Ritesh S. Dayama

You might also like