Module I-Part-A LAB # 1: Introduction To Logic Gates

Module I-Part-A
LAB # 1:
Objective: Design of simple combinational circuits using Logic gates
Introduction to Logic Gates:
Good working knowledge of logic gates is essential as they are used in almost in all electrical
circuits in one form or the other.
This lab has the following objectives:
Understand how to use the breadboard to patch up, test your logic design and debug it.
Understand the use of logic gates such as AND, OR, NOT, NAND, NOR, XOR in design of simple
combinational circuits
Wiring Guidelines:
 Arrange the IC chips on the breadboard so that only short wire connections are needed.
 Try to keep the wire as short as possible to avoid a jungle of wires.
 Try to maintain a low wiring profile so that the pins of the chips can be reached and the chip
replaced, if necessary. The best connections are those that lie flat on the board.
 Put the wiring in a numeric order and identify them with different color to make debugging
convenient.
Pay extra attention to power and ground. If you find your chips are getting super-hot then
there is probably a short circuit. Turn off power immediately and wire them correctly.
The logic chips used in this class require a power source and ground. The power source (V CC) is +5V
and the ground is 0V, which can be drawn from the Digital Logic Trainer. Normally, pin 14 of the IC
chip is connected to +5V and pin 7 to ground.
Components:
 7400: Quad 2-input NAND gate
The NAND gate (NOT-AND) implies an AND function with a complemented output.
 7402: Quad 2-input NOR gate
The NOR gate (NOT-OR) implies an OR function with a complemented output.
 7486: Quad 2-input XOR gate
The XOR gate is another important function widely used because of some special arithmetic
properties. It is a 2-input gate (A and B) with an output AB’+A’B
One Important feature about NAND and NOR gates is that they both can be used as an
inverter and a buffer. For an input A, the inverter generates the complement of the input A’, and the
buffer generates the input as it is A’.
Prelab 1:
1. Design a combinational circuit that implements an exclusive-OR (XOR) function using
minimum number of NAND gates. Draw a schematic of the circuit.
2. Design a Logic ckt that accepts BCD (Binary-Coded-Decimal) inputs (D3 D2D1D0). The
output (Y) of this system is High when the inputs are 5,7,9. When the input is not 5,7,9
output is Low. Simplify the circuit using K-Map and draw the schematic using minimum
number of gates. Hint: Make use of don’t Cares to simplify the design. Draw the truth
table, K-Map and the schematic.
3. Two electives were being offered to students who were studying in their 3rd Semester of
B.Tech. Student A decides to take elective one if at-least one among Student B and
student C takes it. Design a logic circuit using only universal gates to indicate whether
Student A finally takes elective one or not, for any combination of electives opted by
Student B and Student C.
4. Draw the pin assignments and the truth table of the NAND gate from the Data book.
Dept. of E&C Engg., NITK Surathkal
5. Obtain an XOR chip from the Data book and draw the pin assignments and truth table.
Lab 1 :
1. Construct a XOR circuit that you designed in the prelab. Demonstrate the operations of the
circuit for all input combinations.
2. Implement the prelab question no-2 using basic gates.
3. Implement the prelab question no-3.
Post Lab1 :
A sealed tank in a chemical factory has mainly three sensors. A level sensor (L), A pressure
sensor (P), A temperature sensor (T). Three sensors are to be monitored by a safety system as
shown in the figure below:
 All the lamps are active LOW.

 OK is active when no sensor is active.
 ALERT is active when one sensor is active
 DANGER is active when two sensors are active
 CRITICAL is active when all are active.
 Both DANGER and CRITICAL use same lamp.
 DANGER is steady ON on the Red lamp, whereas CRITICAL is flashing at 3Hz.
Design a controller for the same. Draw the truth table, and the K-maps. Draw the circuit using
minimum number of gates.
Dept. of E&C Engg., NITK Surathkal

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Module I-Part-A

 All the lamps are active LOW.

Dept. of E&C Engg., NITK Surathkal

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