CMOS DIGITAL VLSI DESIGN

Combinational Logic Design-I

SUDEB DASGUPTA
DEPARMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

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 Outline
• Introduction
• Static & Dynamic Logic Design
• Choice of Pull-up and Pull-down Network
• Two Input NAND Gate
• Static Properties of Complementary CMOS Gates
• Propagation Delay of Complementary CMOS Gates
• Problems of Complementary CMOS Gates
• Design Techniques of Large Fan-in
• Recapitulation

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 Introduction
• In the combinational logic or non-regenerative circuits, the output at
any instant of time depends only on the signal present at its input.
• In contrast to this if the output depends on the current input data
along with the previous state of input then it is called as sequential or
regenerative logic.
Inputs Combinational
Output
Combinational Logic Circuit
Inputs Output
Logic Circuit
States
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 Static & Dynamic logic Design VDD
• Static Design-At every point of time,
I1
each gate output is either connected to I.2 PULL-UP
VDD or VSS via a low resistance path. .. NETWORK
In
• Dynamic Design-This relies on F(I1,I2...In)
temporary storage of signal values on
the capacitance of high-impedance I1 PULL-
circuit nodes. ..I2 DOWN
• Complementary Logic- This is a widely . NETWORK
In
used static logic, consists of pull-up
(PUN) and pull-down network (PDN). VSS
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 Choice of Pull Down Network
• What type of MOS is preferable for PDN?
out VDD VTP
out VDD 0

CL CL
VDD

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 Choice of Pull UP Network
• What type of MOS is preferable for PUN?

VDD VDD
0 VDD-VTn 0
out
out
CL
CL

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 Two-Input NAND Gate
VDD
• N-input logic implementation requires 2N
gates. A B
• NMOS in series forms an AND logic, while
in parallel they form an OR logic.
• Complementary CMOS logics are dual F
A
networks (De Morgan’s Theorem).
Internal
B
node
 Assignment-
Realize F=D+B.(A+C) using complementary CMOS design.
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 Static Properties of Complementary CMOS Gates

• The complementary CMOS

logic gates exhibits rail-to-rail
swing, with no static power Strong PUN
dissipation. VOH = VDD; VOL = GND
This difference
• The analysis of VTC is more is due to
dis(charging)
complicated as it depends on internal node
input pattern.
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

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 Propagation Delay of Complementary CMOS Gates
VDD
• Each transistor will replace by its equivalent
resistance and capacitance. Rp Rp
• We calculate simple RC delay as- A’ B’
0.69×(Rp or Rn) ×CL.
• The propagation delay depends on input pattern. Rn CL
A
Rn
CL
B
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.

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 Problems of Complementary CMOS Gates

1. The number of transistor required to implement an N fan-in gates is

2N.
2. The large number (2N) of transistors increases the overall
capacitance of the gate.
3. Propagation delay of the gates deteriorate as a function of fan-in.
4. The series connection of the transistor in either PUN or PDN
network causes an additional slowdown.
5. Therefore, the delay becomes a quadratic function of the fan-in.

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 Design Techniques of Large Fan-in
1. Transistor Sizing
• To reduce the delay and resistance of the device, the designer must
have to increase the sizes.
• However, increase in size increases the parasitic capacitors which
adds its effects in the preceding gate.
• If the load capacitor is dominated over the intrinsic capacitor then
widening the device only creates a self loading effect.
• Sizing is only effective when the load is dominated by the fan-out.

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 out
2. Progressive Transistor Sizing
• This technique reduces the CL
InN MN
dominant resistance while
keeping the capacitance in In3 C3
M3
bounds.
• Progressive scaling of transistor is
beneficial: M1>M2>M3>M4. In2 C2
M2
• The progressive scaling is easy in
schematic diagram but it is not as In1 M1
simple in layout. C1

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3. Input Reordering
• All the signals in the complex logic blocks might not appear at the
same time due to propagation delay or preceding logic gates.
• The signal, last to all the inputs which have a stable value can be
called as a critical signal an the path over which the ultimate speed of
the structure can be calculated is called critical path.
• Putting the critical path transistor closer to the output gives a higher
speed of operation.

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4. Logic Restructuring

• Manipulating the logic equation can reduce the fan-in requirement

and thus reduces the gate delay.

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 Recapitulation

• The most widely used logic style is static complementary CMOS.

• NMOS is a better choice for PDN and PMOS is a better choice for
PUN.
• Complementary Logic is a dual in nature.
• The propagation delay of the complex network follows the Elmore
Delay Rule.
• Progressive Transistor Sizing, Input Reordering and Logic
Restructuring are the design technique of large fan-in.

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Thank You

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