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    Explain Datapath in Pipeline or Pipelined Datapath?

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    Loganathan Rm
    The datapath of a pipelined processor is separated into five stages: instruction fetch (IF), instruction decode and register access (ID), execution (EX), memory access (MEM), and write back (WB). Instructions and data move through each stage in order from left to right. However, there are two exceptions: results are written back to the register file in the middle, and the next value of the program counter can be selected from the MEM stage. Pipelining registers are placed between each stage to retain an instruction's state as it moves through the pipeline. This allows subsequent instructions to begin execution before previous ones complete.

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    Explain Datapath in Pipeline or Pipelined Datapath?

    Uploaded by

    Loganathan Rm
    91 views4 pages
    The datapath of a pipelined processor is separated into five stages: instruction fetch (IF), instruction decode and register access (ID), execution (EX), memory access (MEM), and write back (WB). Instructions and data move through each stage in order from left to right. However, there are two exceptions: results are written back to the register file in the middle, and the next value of the program counter can be selected from the MEM stage. Pipelining registers are placed between each stage to retain an instruction's state as it moves through the pipeline. This allows subsequent instructions to begin execution before previous ones complete.

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    Explain Datapath in pipeline

    Original Title

    Data Path

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    The datapath of a pipelined processor is separated into five stages: instruction fetch (IF), instruction decode and register access (ID), execution (EX), memory access (MEM), and write back (WB). Instructions and data move through each stage in order from left to right. However, there are two exceptions: results are written back to the register file in the middle, and the next value of the program counter can be selected from the MEM stage. Pipelining registers are placed between each stage to retain an instruction's state as it moves through the pipeline. This allows subsequent instructions to begin execution before previous ones complete.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    91 views4 pages

    Explain Datapath in Pipeline or Pipelined Datapath?

    Uploaded by

    Loganathan Rm
    The datapath of a pipelined processor is separated into five stages: instruction fetch (IF), instruction decode and register access (ID), execution (EX), memory access (MEM), and write back (WB). Instructions and data move through each stage in order from left to right. However, there are two exceptions: results are written back to the register file in the middle, and the next value of the program counter can be selected from the MEM stage. Pipelining registers are placed between each stage to retain an instruction's state as it moves through the pipeline. This allows subsequent instructions to begin execution before previous ones complete.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 4

    2. Explain Datapath in pipeline or pipelined datapath?

    The data path is separated into five pieces, with each piece named corresponding to a stage
    of instruction execution:
    1. IF: Instruction fetch
    2. ID: Instruction decode and register fi le read
    3. EX: Execution or address calculation
    4. MEM: Data memory access
    5. WB: Write back

    Refer Above diagram, instructions and data move generally from left to right through the
    five stages as they complete execution.
    There are, however, two exceptions to this left -to-right flow of instructions:
    o The write-back stage, which places the result back into the register file in the
    middle of the data path.
    o The selection of the next value of the PC, choosing between the incremented
    PC and the branch address from the MEM stage.
    Data flowing from right to left does not affect the current instruction; these reverse data
    movements influence only later instructions in the pipeline.
    o The first right-to-left flow of data can lead to data hazards
    o The second right-to-left leads to control hazards.
    To retain the value of an individual instruction for its other four stages, the value read
    from instruction memory must be saved in a register. Similar arguments apply to every
    pipeline stage, so we must place registers wherever there are dividing lines between stages.
    The registers are named for the two stages separated by that register. For example, the
    pipeline register between the IF and ID stages is called IF/ID. Notice that there is no pipeline
    register at the end of the write-back stage.
    All instructions must update some state in the processor -the register file, memory, or the
    PC. Its contents must be saved in the pipeline register when an exception occurs, while the
    contents of the pipeline registers can be discarded. The registers can be referred from the below
    diagram.
    Consider load instruction abbreviation lw and how the operations of this instruction in
    a pipe line is done are as follows: (lw $s0, 32($t0))
    1. Instruction fetch: The top portion of Figure shows the instruction being read from
    memory using the address in the PC and then being placed in the IF/ID pipeline register. The
    PC address is incremented by 4 and then written back into the PC to be ready for the next clock
    cycle. This incremented address is also saved in the IF/ID pipeline register in case it is needed
    later for an branch instruction, such as beq.
    2. Instruction decode and register file read: The bottom portion of Figure shows the
    instruction portion of the IF/ID pipeline register supplying the 16-bit immediate field of the
    load instruction( here in our example is 32), which is sign-extended to 32 bits, and the register
    numbers to read the two registers ( $s0 and $t0). All three values are stored in the ID/EX
    pipeline register, along with the incremented PC address.
    3. Execute or address calculation: Figure shows that the load instruction reads the
    contents of register1 ($t0) and the sign-extended immediate (value 32) from the ID/EX
    pipeline register and adds them using the ALU. That sum is placed in the EX/MEM pipeline
    register.
    4. Memory access: The top portion of Figure shows the load instruction reading the data
    memory using the address from the EX/MEM pipeline register and loading the data into the
    MEM/WB pipeline register.
    5. Write-back: The bottom portion of Figure shows the final step: reading the data from
    the MEM/WB pipeline register and writing it into the register file ($s0) in the middle of the
    figure.
    The following figure shows the reading and writing operations done during a stage ( here
    instruction decode stage). It show that reading operation is performed from IF/ID register to
    get input for the stage and after completion of execution of that stage the results are written in
    ID/EX register.
    Note: The read and write operations are shaded differently.
    Similarly other stages follows with the same read / write operations with respect to
    the execution of each stage and pipelined buffers.

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