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Digital Circuits
Assignment- Week 4
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15
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QUESTION 1:
Consider a 4-bit adder with inputs A = {A3 A2 A1 A0} and B = { B 3 B 2 B 1 B 0}. For which of the following
input condition no carry-out would be generated. (Assume there is no carry input)
a. A = {1011}, B = {0101}
b. A = {1011}, B = {0001}
c. A = {1011}, B = {0100}
d. A = {1001}, B = {0101}

Correct Answer: a

Detailed Solution:

Carry out would be generated only for first option. Sum = 10000
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QUESTION 2:
Which one of the following expressions does NOT represent exclusive NOR of A and B?
a) AB+A’B’
b) A’ xor B
c) A xor B’
d) A’ xor B’
Correct Answer: d

Detailed Solution:

A xnor B = AB + A’B’

A’ xor B = (A’)’B + A’B’ = AB + A’B’

A xor B’ = A’B’ + (A’)’B = AB + A’B’

A’ xor B’ = (A’)’B’ + A’(B’)’ = AB’ + A’B

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QUESTION 3:
When two 8-bit numbers A7 … A0 and B7 … B0, in 2’s complement representation (with A0 and B0 as the
least significant bits), are added using ripple-carry adder. The sum bits obtained are S7 … S0 and the
carry bits are C7 … C0. An overflow is said to have occurred if
a) the carry bit C7 is 1
b) all the carry bits (C7, … , C0 ) are 1
c) (A7 . B7 . S7‘ + A7‘ . B7‘ . S7) is 1
d) (A0 . B0 . S0‘ + A0‘ . B0‘ . S0) is 1

Correct Answer: c

Detailed Solution:

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QUESTION 4:
The minimum number of 2-input NAND gates are required to realize a half adder is
a) 8
b) 5
c) 6
d) 4

Correct Answer: b

Detailed Solution:
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QUESTION 5:
For a logic family, given that

VOH is the minimum output high level voltage

VOL is the maximum output low level voltage

VIH is the minimum acceptable input high level voltage

VIL is the maximum acceptable input low level voltage

Then correct relation ship is

a) VIH > VOH > VIL > VOL

b) VOH > VIH > VIL > VOL
c) VOH > VIH > VOL > VLL
d) VOH < VIH < VIL < VOL
Correct Answer: B

Detailed Solution:
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QUESTION 6:
A logic gate noise margin parameters are:
VIH = 1.5v , VIL = 0.2v ,VOH = 1.8v ,VOL = 0.1v then identify the values of noise margin high (NMH) and noise
margin low(NML) respectively.

a) 0.3v, 0.5v
b) 1.3v,1.7v
c) 0.3v,0.1v
d) 0.1v,0.3v

Correct Answer: C

Detailed Solution:

NMH = VOH – VIH = 1.8v-1.5v=0.3v

NML = VIL – VOL = 0.2v-0.1v = 0.1v

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QUESTION 7:
The minimum number of 2-input NAND gates are required to realize a Full-adder is
a) 12
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b) 10
c) 9
d) 7

Correct Answer: C

Detailed Solution:

QUESTION 8:
In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by
a) M = XY, N = X xor Y
b) M = X’Y, N = X’ xor Y
c) M = X’Y, N = X xor Y
d) M = X’Y, N = (X xor Y)’

Correct Answer: c

Detailed Solution:

M = X’Y, N = X xor Y

QUESTION 9:
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If the output of a digital circuit makes a momentary transition to logic 1, while otherwise the output is
logic 0, it is called a
a) Static-1 Hazard
b) Static-0 Hazard
c) Dynamic Hazard
d) No Hazard

Correct Answer: b

Detailed Solution:

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QUESTION 10:

A full adder can be realized using

a) one half adder, two AND gates

b) two half adders, one OR gate
c) two half adders, one AND gate
d) two half adders, two AND gates

Correct Answer: b

Detailed Solution:

QUESTION 11:
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Which logic function is implemented by the CMOS complex logic structure shown in the figure?

a. AB +C’
b. (A+B)C
c. (AC+BC)’
d. (AB+C)’

Correct Answer: d

Detailed Solution:

Two NMOS in series corresponds to OR function: (AB)

NMOS in parallel corresponds to AND function: (AB+C)
CMOS structure implements inverting logic: (AB+C)’

QUESTION 12:
Consider the circuit shown below. Which of the following statements correctly describe the
output X?
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a. X is the generated carry-out bit

b. X is equal to logic 1 when addition is performed and X is equal to logic 0 when
subtraction is done.
c. X is equal to logic 1 if there is an overflow during either addition or subtraction.
d. X is equal to logic 0 if there is an overflow during either addition or subtraction.

Correct Answer: c

Detailed Solution:

X is equal to logic 1 if there is an overflow during either addition or subtraction.

QUESTION 13:
The product term to be included to remove possible static hazard for the function WX + W’Y’ is
a. WY’
b. XY’
c. W’X’
d. XY

Correct Answer: b

Detailed Solution:

QUESTION 14:
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Which of the following is not a property of CMOS logic gates?

a. High switching speed
b. Low static power consumption
c. High packing density
d. High noise margin

Correct Answer: a

Detailed Solution:

CMOS logic gates have generally low switching speed due to squared relationship of current
with voltage instead of exponential (like BJT)

QUESTION 15:
The number “00101110” when converted to BCD is
a. 01000110
b. 00100110
c. 01010100
d. Cannot be determined
Correct Answer: a

Detailed Solution:

00101110 is equal to 46 in decimal. 4 in binary is 0100 and 6 in binary is 0110.

Combined we get 01000110

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