UNIT-1

MICROCOMPUTER

Microcomputers are the computer which is of the smallest sized and they are also referred to
as the computer which is used by the person on daily basis. The personal or desktop computers
can also be used in place of the micro computers. This is the first form of computer which was
invented and till now they are being in use by people. Many people are using the micro
computers. The micro computers are known as micro due to the use of a micro processor in it
which as a result differentiates it from the other computers and its types. The microcomputers
had been designed in such a way that the person alone can use them and as the other name of
it which is the personal computer suggests that the computer can only be used by an individual
person at a time.
The micro computers can also be found in the form of notebook, workstations or personal
computers as well. They are being used by many people on a greater ratio. The micro processor
that is found in the central processing unit of the computer is known as the micro chips which
contains most of the information that is stored in it and even it is one of the most important
part of the computer too. The micro computers also contain other types of components as well
which are the random access memory where the information can be stored on the computer
for a longer time period and the other form of memory is the read only memory where the data
is stored for a limited time period ensuring that when the information is of no particular usage
it is deleted after the specific time. Another important component of the micro computer is the
motherboard which is mainly used for the purpose of the input and the out ports but in fact the
motherboard is the system which is composed of different circuits and port with a specific bus
system for the computer too.

The microcomputers had been designed in such a way that the person alone can use them and
as the other name of it which is the personal computer suggests that the computer can only be
used by an individual person at a time. The micro computers can also be found in the form of
notebook, workstations or personal computers as well. They are being used by many people on
a greater ratio. The micro processor that is found in the central processing unit of the computer
is known as the micro chips which contains most of the information that is stored in it and even
it is one of the most important part of the computer too.

MICROPROCESSOR

The entire CPU with timing and control functions on a single chip is known as
Microprocessor. Therefore a Microprocessor or MPU is an integrated circuit that contains many
processing capabilities of a large computer. It can process a multiple micro instructions.

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MICROPROCESSOR EVOLUTION

A common way of categorizing is by the number of bits that their ALU can work with at a
time. A Microprocessor with a 4 - bit ALU will be referred to as a 4-bit Microprocessor, regardless
of the number of address lines or the number of data bus lines that it has. The first
microprocessor was the Intel 4004 produced in 1971. This 4004 was a 4 - bit device intended to
be used with some other devices in making a calculator .Some logic designers, however, saw that
this device could be used to replace PC boards full of combinational and sequential logic devices.
Also, the ability to change the function of a system by just changing the programming, rather than
redesigning the hardware, is very appealing. It was these factors that pushed the evolution of
microprocessors.

In 1972 Intel comes out with the 8008 which was capable of working with 8-bit words. In
1974 Intel announced the 8080 which had a much larger instruction set than 8008. The 8080 is
referred to as a second-generation microprocessor.

Intel produced the 8080; Motorola came out with the MC 6800, another 8-bit general
purpose CPU. The 6800 had the advantage that it required only +5V supply rather than the -5V,
+5V and +12V supplies required by the 8080.

After Motorola came out with the MC6800, Intel produced the 8085, an upgrade of the
8080 that required only a +5V supply.

In 1978 Intel came out with the 8086 which is a full 16-bit processors have single
instructions for functions such as multiply and divide, which required a lengthy sequence of
instructions on the 8-bit processors.

Soon after Motorola came out with the 16-bit MC68000. The evolution contained on to
32-bit processors that work with gigabytes (109 bytes) or terabytes (1012 bytes) of memory.
Examples of these devices are the Intel 80386, the Motorola MC 68020, and the National 32032.

INTEL 8085
The 8085 was Intel’s immediate successor to the 8080. The main contributions of the 8085 are
reduction of the three-chip 8080 system to one chip and operation from a single +5V power
supply.

The 8085 is the 8-bit microprocessor and it is a 40 pin IC. The standard 8085 has a maximum clock
rate of 3MHz. The shortest instructions require four clock cycles, resulting in minimum instruction
times of 1.33 µs at 3 MHz.

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 THE INTEL 8086 MICROPROCESSOR

INTRODUCTION

The 8086 was the first 16-bit Microprocessor to be introduced by Intel Corporation. It is
designed to be upwardly compatible with the older 8080/8085 series of 8-bit microprocessors.
The upward compatibility allows programs written for the 8080/8085 to be easily converted to
run on the 8086.

The word 16-bit means that its arithmetic logical unit, internal registers, and most of its
instructions are designed to work with 16-bit binary words. The 8086 has a 16-bit data bus, so it
can read data form or write data to memory and ports either 16-bits or 8- bits at a time. The 8086
has a 20-bit address bus, so it can address any one of 220 or 1,048,576 memory locations. Each of
the 1,048,576 memory addresses of the 8086 represents a byte-wide location. Words will be
stored in two consecutive memory locations. If the first byte of a word is at an even address, the
8086 can read the entire word in one operation. If the first byte of the word is at an odd address,
the 8086 will read the first byte of the word in one operation, and the second byte in another
operation.

FEATURES OF 8086
•It is a 16-bit µp.

•8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).

•It can support up to 64K I/O ports.

•It provides 14, 16 -bit registers.

•It has multiplexed address and data bus which reduces the number of pins
needed, but does slow down the transfer of data (drawback).

•It requires single phase clock with 33% duty cycle to provide internal timing.

•8086 is designed to operate in two modes, Minimum and Maximum.

•It can prefetches upto 6 instruction bytes from memory and queues them in
order to speed up instruction execution.

•It requires +5V power supply.

•A 40 pin dual in line package

The Intel 8086 supports multiprogramming. In multiprogramming, the

code for two or more processes is in memory at the same time and is
executed in a time-multiplexed fashion.

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 The 8086 provides powerful instruction set with the following addressing
modes: Register, Immediate, Direct, Indirect through an index or base,
indirect through the sum of a base and an index register, relative and
implied.

The maximum internal clock of 8086 is 5 MHz. The other versions of 8086
with different .clock rates are 8086-1, 8086-2 and 8086-4 with maximum
internal clock frequency of 10MHz, 8MHz and 4MHz respectively.

ARCHITECTURE OF 8086

The term architecture, as used in microprocessor circuits, describes the functional components
that make up the MPU and the interaction between them. These include the temporary storage
devices known as registers, which are used to hold data, instructions, and status information.
There are also devices to perform arithmetic and logical operations. Control devices are used to
control the flow of information through the MPU.

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 Fig.1 8086 Internal Block Diagram

As shown by the block diagram in fig.1, the 8086 MPU is divided into two independent functional
parts known as the Execution unit (EU) and the Bus interface unit (BIU).

Execution unit (EU)

The EU is where the actual processing of data takes place inside the 8086 MPU. It is here
that the arithmetic and logic unit (ALU) is located, along with the registers used to manipulate
data and store immediate results. The EU accepts instructions and data that have been fetched
by the BIU and then processes the information. Data processed by the EU can be transmitted to
the memory or peripheral devices through the BIU. EU has no direct connection with the outside
world and relies solely on the BIU to feed it with instructions and data as indicated in fig.2

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 Fig.2 BIU/EU DATA FEED

Bus Interface Unit (BIU)

The BIU is made up of the address generation and bus-control unit, the instruction queue, and
the instruction pointer. It has the task of making sure that the bus is used to its fullest capacity in
order to speed up operations. This function is carried in two ways. First, by fetching the
instructions before they are needed by the execution unit and storing them in the instruction
queue, the 8086 MPU is able to increase computing speed. Second, by taking care of all bus-
control functions, the EU is free to concentrate on processing data and carrying out the
instructions. The instruction pointer contains the location or address of the next instruction to
be executed.

Inside the EU

The EU is made up of two parts known as the ALU and the general registers. It is here that
instructions are received, decoded and executed from the instruction queue portion of BIU. The
instructions are taken from the top of the instruction queue on the first-in, first-out, or FIFO,
basis.

ALU

The ALU is the calculator part of the execution unit. It consists of electronic circuitry that
performs arithmetic operations or logical operations on the binary represented electrical signals.
The control system for the execution unit can also be thought of as part of ALU. It provides a path
for the flow of instructions into the ALU, the general registers, and the flag register.

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FLAG REGISTER

A flag is a flip-flop which indicates some condition produced by the execution of an

instruction or controls certain operations of the EU. The Flag Register is a special register
associated with the ALU. A 16-bit flag register in the EU contains nine active flags. Fig.3 shows the
location of the nine flags in the flag register.

Fig.3 8086 Flag register bit pattern

Six flags are status flags- AF, CF, OF, SF, PF and ZF. The remaining three flags are control flags -DF,
IF, and TF. Table 1 presents a flag summary and highlights key concerns.

Table 1:

Flag Summary:

Status flag Description

AF (auxiliary flag) Indicates if the instruction generated a carry out the 4 LSBs.

CF (carry flag) Indicates if the instruction generated a carry out the MSB.
Indicates if the instruction generated a signed result that is
OF (overflow flag)
Out of range.
SF (sign flag) Indicates if the instruction generated a negative result.

PF (parity flag) Indicates if the instruction generated a result having an even

ZF (zero flag) Indicates if the instruction generated a zero result

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 DF(direction flag) Controls the direction of the string manipulation instructions.

IF( interrupt-enable flag ) Enables or disables external interrupts.

TF(trap flag) Puts the processor into a single-step mode for program debugging

AF (auxiliary flag). If this flag is set, there has been a carry out or borrow of the 4 least
significant bits. This flag is used during decimal arithmetic instructions.
CF (carry flag). If this flag is set, there has been a carry out or overflow of the most
significant bit. It is used by instructions that add and subtract multi byte numbers.
OF (overflow flag). If this flag is set, an arithmetic overflow has occurred; that is, a
significant digit has been lost because the size of the result exceeded the capacity of its
destination location.
SF (sign flag). Since negative binary numbers are represented in the 8086/8088 in
standard 2s complement notation. SF indicates the sign of the result ( 0 = positive, 1=
negative).
PF (party flag). If this flag is set, the result has even parity, an even number of 1s. This flag
can be used to check for transmission errors.
ZF (zero flag). If this flag is set, the result of the operation is 0.
DF (direction flag). Setting DF causes string instructions to auto-decrement (count
down); that is, to process strings from the high address to the low address, or from right
to left. Clearing DF causes string instructions to auto-increment (count up), or process
strings from left to right.
IF (interrupt-enable flag) Setting IF allows the MPU to recognize external (maskable)
interrupt requests. Clearing IF disables these interrupts. IF has no effect on either
nonmaskable external or internally generated interrupts.
TF (trap flag). Setting TF puts the processor into single-step mode for debugging. In
this mode the MPU automatically generates an internal interrupt after each instruction,
allowing a program to be inspected as it executes instruction by instruction.

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General Purpose Registers

EU has eight general purpose registers labeled AH, AL, BH, BL, CH, CL, DH and DL. These
registers are a set of data registers, which are used to hold intermediate results. The H represents
the high- order or most- significant byte and the L represents the low- order or least-significant
byte. Each of these registers may be used separately as 8-bit storage areas or combined to form
one 16-bit (one word) storage area.

The acceptable register pairs are AH and AL, BH and BL, CH and CL and DH and DL. The AH-AL pair
is referred to as the AX register, the BH-BL pair is referred to as the BX register, the CH-CL pair is
referred to as the CX register, and the BH-BL pair is referred to as the DX register.

The AL register is also called as the accumulator. For 16-bit operations, AX is called the
accumulator.

The 8086 register set is very similar to those of earlier generation 8080 and 8085
microprocessors. Many programs written for the 8080 and 8085 could easily be translated to run
on the 8086.

Stack Pointer Register

A Stack is a section of memory set aside to store addresses and data while a subprogram
is being executed. An entire 64 K bytes segment is set aside as stack in 8086 MPU. The upper 16
bits of the starting address for this segment is kept in the stack segment register. The Stack
Pointer (SP) register contain the 16-bit offset from the start of the segment to the memory
location where a word was most recently stored on the Stack. The memory location where a
word was most recently stored is called the top of Stack.

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The physical address for a stack read or for a stack write is produced by adding the contents of
the stack pointer register to the segment base address in SS. To do this the contents of the Stack
segment register are shifted four bit positions left and the contents of SP are added to the shifted
result. In the figure 5000 H in SS is shifted left four bit positions to give 50000H. When FFEOH in
the SP is added to this, the resultant physical address for the top of the stack will be 5FFEOH. The
physical address can be represented either as a single number 5FFEOH or it can be represented in
SS: SP form as 5000: FFEOH.

Pointer and Index Registers

In addition to the Stack Pointer register, SP, the EU contains a 16-bit base pointer (BP) register.
It also contains a 16-bit Source index (SI) register and a 16-bitdestination index (DI) register.
These three registers can be used for temporary storage of data just as the general purpose
registers. However, their main use is to hold the 16-bit offset of a data word in one of the
segments. That is, the pointer and index registers are usually used to point to or index to an
address in memory. When used in this manner, these registers are address registers that
designate a specific location in the memory that may be frequently used by the program. The
addresses contained in these registers can be combined with information from the BIU to
physically locate the data in the memory.

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The Bus Interface Unit

The BIU sends out addresses, fetches instructions from memory, reads data from ports
and memory. In other words the BIU handles all transfers of data and addresses on the buses for
the execution unit. The BIU can be thought of as three functional blocks; Bus control, Instruction
queue and Address control.

But control

The bus-control unit performs the bus operations for the MPU. It fetches and transmits
instructions, data and control signals between MPU and the other devices of the system.

Instruction Queue

The instruction queue is used as a temporary memory storage area for data instructions
that are to be executed by the MPU. The BIU, through the bus-control unit, prefetches
instructions and stores them in the instruction queue. This allows the execution unit to perform
its calculations at maximum efficiency. Because the BIU and EU essentially operate
independently, the BIU concentrates on loading instructions into the instruction queue. This
usually takes more time to do than the calculations performed by the execution unit. In effect,
the BIU and the EU work in parallel. The instruction queue is a first- in, first- out (FIFO) memory.
This means that the first instruction loaded into the instruction queue by the bus control unit will
be the first instruction to be used the ALU.

ADDRESS CONTROL

The address-control unit is used to generate the 20-bit memory address that gives the physical
or actual location of the data or instruction in memory. This unit consists of the instruction
pointer, the segment registers and the address generator as shown in fig 5.

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Instruction Pointer

The Instruction Pointer (IP) is a 16- bit register that is used to point to, or tell the MPU,
the instruction to execute next. Therefore, the instruction pointer is used to control the sequence
in which the program is executed. Each time the execution unit accepts an instruction, the
instruction pointer, is incremented to point to the next instruction in the program.

SEGMENT REGISTERS

There are four segment registers. They are the code segment (CS), the data segment
(DS), the stack segment (SS), and the extra segment (ES). These registers are used to define a
logical memory space or memory segment that is set aside for a particular function.

The CS registers points to the current code segment. Instructions are fetched from this
segment. The DS register points to the current data segment. Program variables and data are held
in this area. The SS register points to the current stack segment, stack operations are performed
on locations in the SS segment. The ES register points to the current extra segment, which is also
used for data storage. Each of the segment registers can be up to 64 kilo bytes long. Each

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segment is made up of an uninterrupted section of memory locations. Each segment can be
addressed separately using the base address that is contained in its segment register. The base
address is the starting address for that segment.

ADDRESS GENERATOR

The address-generator unit is used with the segment registers to generate the 20- bit
physical address required to identify all the possible memory addresses. The 20 address lines give
a maximum physical memory size of 20 address locations, or 1,048,576 bytes of memory. But all
the registers in the MPU are only 16 bits wide. The physical address is obtained by shifting the
segment base value four bit positions (one hexa decimal position) and adding the offset or logical
address of the segment.

Addressing Modes of 8086:

Addressing mode indicates a way of locating data or operands. Depending up on the data type
used in the instruction and the memory addressing modes, any instruction may belong to one or
more addressing modes or same instruction may not belong to any of the addressing modes.

The addressing mode describes the types of operands and the way they are accessed for
executing an instruction. According to the flow of instruction execution, the instructions may be
categorized as

1. Sequential control flow instructions and

2. Control transfer instructions.

Sequential control flow instructions are the instructions which after execution, transfer control to
the next instruction appearing immediately after it (in the sequence) in the program. For example
the arithmetic, logic, data transfer and processor control instructions are Sequential control flow
instructions.

The control transfer instructions on the other hand transfer control to some predefined address
or the address somehow specified in the instruction, after their execution. For example INT, CALL,
RET & JUMP instructions fall under this category.

The addressing modes for Sequential and control flow instructions are explained as follows.

1. Immediate addressing mode:

In this type of addressing, immediate data is a part of instruction, and appears in the form of
successive byte or bytes.

Example: MOV AX, 0005H.

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 In the above example, 0005H is the immediate data. The immediate data may be 8-bit or 16-bit
in size.

2. Direct addressing mode:

In the direct addressing mode, a 16-bit memory address (offset) directly specified in the
instruction as a part of it.
Example: MOV AX, [5000H].

3. Register addressing mode:

In the register addressing mode, the data is stored in a register and it is referred using the
particular register. All the registers, except IP, may be used in this mode.

Example: MOV BX, AX

4. Register indirect addressing mode:

Sometimes, the address of the memory location which contains data or operands is determined
in an indirect way, using the offset registers. The mode of addressing is known as register indirect
mode.

In this addressing mode, the offset address of data is in either BX or SI or DI Register. The
default segment is either DS or ES.

Example: MOV AX, [BX].

5. Indexed addressing mode:

In this addressing mode, offset of the operand is stored one of the index registers. DS & ES are
the default segments for index registers SI & DI respectively.

Example: MOV AX, [SI]

Here, data is available at an offset address stored in SI in DS.

6. Register relative addressing mode:

In this addressing mode, the data is available at an effective address formed by adding an 8-bit or
16-bit displacement with the content of any one of the register BX, BP, SI & DI in the default
(either in DS & ES) segment.

Example: MOV AX, 50H [BX]

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7. Based indexed addressing mode:

The effective address of data is formed in this addressing mode, by adding content of a base
register (any one of BX or BP) to the content of an index register (any one of SI or DI). The default
segment register may be ES or DS.

Example: MOV AX, [BX][SI]

8. Relative based indexed:

The effective address is formed by adding an 8 or 16-bit displacement with the sum of contents of
any of the base registers (BX or BP) and any one of the index registers, in a default segment.

Example: MOV AX, 50H [BX] [SI]

For the control transfer instructions, the addressing modes depend upon whether the destination
location is within the same segment or in a different one. It also depends upon the method of
passing the destination address to the processor. Basically, there are two addressing modes for
the control transfer instructions, viz. intersegment and intrasegment addressing modes.

If the location to which the control is to be transferred lies in a different segment other than the
current one, the mode is called intersegment mode. If the destination location lies in the same
segment, the mode is called intrasegment mode.

Addressing Modes for control transfer instructions:

1. Intersegment
a. Intersegment direct
b. Intersegment indirect
2. Intrasegment
a. Intrasegment direct
b. Intrasegment indirect

1. Intersegment direct:

In this mode, the address to which the control is to be transferred is in a different

segment. This addressing mode provides a means of branching from one code segment to
another code segment. Here, the CS and IP of the destination address are specified directly in the
instruction.

Example: JMP 5000H, 2000H;

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Jump to effective address 2000H in segment 5000H.

2. Intersegment indirect:

In this mode, the address to which the control is to be transferred lies in a different
segment and it is passed to the instruction indirectly, i.e. contents of a memory block containing
four bytes, i.e. IP(LSB), IP(MSB), CS(LSB) and CS(MSB) sequentially. The starting address of the
memory block may be referred using any of the addressing modes, except immediate mode.

Example: JMP [2000H].

Jump to an address in the other segment specified at effective address 2000H in DS.

3. Intrasegment direct mode:

In this mode, the address to which the control is to be transferred lies in the same segment in
which the control transfers instruction lies and appears directly in the instruction as an immediate
displacement value. In this addressing mode, the displacement is computed relative to the
content of the instruction pointer.

The effective address to which the control will be transferred is given by the sum of 8 or 16 bit
displacement and current content of IP. In case of jump instruction, if the signed displacement
(d) is of 8-bits (i.e. -128<d<+127), it as short jump and if it is of 16 bits (i.e. -32768<d<+32767), it is
termed as long jump.

Example: JMP SHORT LABEL.

4. Intrasegment indirect mode:

In this mode, the displacement to which the control is to be transferred is in the same
segment in which the control transfer instruction lies, but it is passed to the instruction directly.
Here, the branch address is found as the content of a register or a memory location.

This addressing mode may be used in unconditional branch instructions.

Example: JMP [BX]; Jump to effective address stored in BX.

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Instruction set of 8086
The Instruction set of 8086 microprocessor is classified into 7, they are:-

1) Data transfer instructions

2) Arithmetical & logical instructions
3) Program control transfer instructions
4) Machine Control Instructions
5) Shift / rotate instructions
6) Flag manipulation instructions
7) String instructions

Data Transfer instructions

Data transfer instruction, as the name suggests is for the transfer of data from
memory to internal register, from internal register to memory, from one register to another
register, from input port to internal register, from internal register to output port etc

1. MOV instruction
It is a general purpose instruction to transfer byte or word from register to
register, memory to register, register to memory or with immediate addressing.

General Form:

MOV destination, source

Here the source and destination needs to be of the same size, that is both 8 bit or
both 16 bit

MOV instruction does not affect any flags.

Example:-

MOV BX, 00F2H ; load the immediate number 00F2H in BX register

MOV CL, [2000H] ; Copy the 8 bit content of the memory location, at a
displacement of 2000H from data segment base to
the CL register

MOV [589H], BX ; Copy the 16 bit content of BX register on to the

memory location, which at a displacement of 589H
from the data segment base.

MOV DS, CX ; Move the content of CX to DS

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2. PUSH instruction

The PUSH instruction decrements the stack pointer by two and copies the word
from source to the location where stack pointer now points. Here the source must of
word size data. Source can be a general purpose register, segment register or a
memory location.

The PUSH instruction first pushes the most significant byte to sp-1, then the least
significant to the sp-2.

Push instruction does not affect any flags.

Example:-

PUSH CX ; Decrements SP by 2, copy content of CX to the stack ( figure

shows execution of this instruction)

PUSH DS ; Decrement SP by 2 and copy DS to stack

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3. POP instruction

The POP instruction copies a word from the stack location pointed by the stack
pointer to the destination. The destination can be a General purpose register, a segment
register or a memory location. Here after the content is copied the stack pointer is
automatically incremented by two.

The execution pattern is similar to that of the PUSH instruction.

Example:

POP CX ; Copy a word from the top of the stack to CX and

increment SP by 2.

4. IN & OUT instructions

The IN instruction will copy data from a port to the accumulator. If 8 bit is read
the data will go to AL and if 16 bit then to AX. Similarly OUT instruction Is used to copy data
from accumulator to an output port.

Both IN and OUT instructions can be done using direct and indirect addressing modes.

Example:-

IN AL, 0F8H ; Copy a byte from the port 0F8H to AL

MOV DX, 30F8H ; Copy port address in DX

IN AL, DX ; Move 8 bit data from 30F8H port

IN AX, DX ; Move 16 bit data from 30F8H port

OUT 047H, AL ; Copy contents of AL to 8 bit port 047H

MOV DX, 30F8H ; Copy port address in DX

OUT DX, AL ; Move 8 bit data to the 30F8H port

OUT DX, AX ; Move 16 bit data to the 30F8H port

5. XCHG instruction
The XCHG instruction exchanges contents of the destination and source. Here
destination and source can be register and register or register and memory location, but
XCHG cannot interchange the value of 2 memory locations.

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 General Format

XCHG Destination, Source

Example

XCHG BX, CX ; exchange word in CX with the word in BX

XCHG AL, CL ; exchange byte in CL with the byte in AL

XCHG AX, SUM[BX] ; here physical address, which is DS+SUM+[BX]. The

content at physical address and the content of AX are
interchanged.

Arithmetic and Logic instructions

The arithmetic and logic logical group of instruction include,

1. ADD instruction
Add instruction is used to add the current contents of destination with that of
source and store the result in destination. Here we can use register and/or memory locations.
AF, CF, OF, PF, SF, and ZF flags are affected

General Format:-

ADD Destination, Source

Example:-

1) ADD AL, 0FH ; Add the immediate content, 0FH to the content of AL and store the
result in AL
2) ADD AX, BX ; AX <= AX+BX
3) ADD AX,0100H – IMMEDIATE
4) ADD AX,BX – REGISTER
5) ADD AX,[SI] – REGISTER INDIRECT OR INDEXED
6) ADD AX, [5000H] – DIRECT
7) ADD [5000H], 0100H – IMMEDIATE
8) ADD 0100H – DESTINATION AX (IMPLICT)
2. ADC: ADD WITH CARRY
This instruction performs the same operation as ADD instruction, but adds the carry flag
bit (which may be set as a result of the previous calculation) to the result. All the
condition code flags are affected by this instruction. The examples of this instruction
along with the modes are as follows:

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 Example:

1. ADC AX,BX – REGISTER

2. ADC AX,[SI] – REGISTER INDIRECT OR INDEXED
3. ADC AX, [5000H] – DIRECT
4. ADC [5000H], 0100H – IMMEDIATE
5. ADC 0100H – IMMEDIATE (AX IMPLICT)

3. SUB instruction

SUB instruction is used to subtract the current contents of destination with that of
source and store the result in destination. Here we can use register and/or memory locations.
AF, CF, OF, PF, SF, and ZF flags are affected

General Format:-

SUB Destination, Source

Example:-

1) SUB AL, 0FH ; subtract the immediate content, 0FH from the content of AL and
store the result in AL
2) SUB AX, BX ; AX <= AX-BX
3) SUB AX,0100H – IMMEDIATE (DESTINATION AX)
4) SUB AX,BX – REGISTER
5) SUB AX,[5000H] – DIRECT
6) SUB [5000H], 0100H – IMMEDIATE

4. SBB: SUBTRACT WITH BORROW

The subtract with borrow instruction subtracts the source operand and the borrow flag
(CF) which may reflect the result of the previous calculations, from the destination
operand. Subtraction with borrow, here means subtracting 1 from the subtraction
obtained by SUB, if carry (borrow) flag is set.
The result is stored in the destination operand. All the flags are affected (condition
code) by this instruction. The examples of this instruction are as follows:
1) SBB AX,0100H – IMMEDIATE (DESTINATION AX)
2) SBB AX,BX – REGISTER
3) SBB AX,[5000H] – DIRECT
4) SBB [5000H], 0100H – IMMEDIATE

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 5. CMP: COMPARE
The instruction compares the source operand, which may be a register or an immediate
data or a memory location, with a destination operand that may be a register or a
memory location. For comparison, it subtracts the source operand from the destination
operand but does not store the result anywhere. The flags are affected depending upon
the result of the subtraction. If both of the operands are equal, zero flag is set. If the
source operand is greater than the destination operand, carry flag is set or else, carry
flag is reset. The examples of this instruction are as follows:

1) CMP BX,0100H – IMMEDIATE

2) CMP AX,0100H – IMMEDIATE
3) CMP [5000H], 0100H – DIRECT
4) CMP BX,[SI] – REGISTER INDIRECT OR INDEXED
5) CMP BX, CX – REGISTER

6. INC & DEC instructions

INC and DEC instructions are used to increment and decrement the content of
the specified destination by one. AF, CF, OF, PF, SF, and ZF flags are affected.

Example:-

INC AL ; AL<= AL + 1

INC AX ; AX<=AX + 1

DEC AL ; AL<= AL – 1

DEC AX ; AX<=AX – 1

7. AND instruction
This instruction logically ANDs each bit of the source byte/word with the
corresponding bit in the destination and stores the result in destination. The source can be an
immediate number, register or memory location, register can be a register or memory
location.

The CF and OF flags are both made zero, PF, ZF, SF are affected by the operation and AF is
undefined.

22
General Format:-

AND Destination, Source

Example:-

AND BL, AL ;suppose BL=1000 0110 and AL = 1100 1010 then after the operation BL would
be BL= 1000 0010.

AND CX, AX ;CX <= CX AND AX

AND CL, 08 ;CL<= CL AND (0000 1000)

8. OR instruction
This instruction logically ORs each bit of the source byte/word with the
corresponding bit in the destination and stores the result in destination. The source can be an
immediate number, register or memory location, register can be a register or memory
location.

The CF and OF flags are both made zero, PF, ZF, SF are affected by the operation and AF is
undefined.

General Format:-

OR Destination, Source

Example:-

OR BL, AL ;suppose BL=1000 0110 and AL = 1100 1010 then after the operation BL would
be BL= 1100 1110.

OR CX, AX ;CX <= CX AND AX

OR CL, 08 ;CL<= CL AND (0000 1000)

9. NOT instruction
The NOT instruction complements (inverts) the contents of an operand register or a
memory location, bit by bit. The examples are as follows:
1) NOT AX (BEFORE AX= (1011)2= (B) 16 AFTER EXECUTION AX= (0100)2= (4)16).
2) NOT [5000H]

23
 10. XOR instruction
The XOR operation is again carried out in a similar way to the AND and OR operation.
The constraints on the operands are also similar. The XOR operation gives a high output,
when the 2 input bits are dissimilar. Otherwise, the output is zero. The example
instructions are as follows:

1) XOR AX,0098H
2) XOR AX,BX
3) XOR AX,[5000H]

SHIFT / ROTATE INSTRUCTIONS

Shift instructions move the binary data to the left or right by shifting them within
the register or memory location. They also can perform multiplication of powers of 2 +n and
division of powers of 2-n.

There are two type of shifts logical shifting and arithmetic shifting, later is used
with signed numbers while former with unsigned.

Fig.1 Shift operations

Rotate on the other hand rotates the information in a register or memory either
from one end to another or through the carry flag.

24
 Fig.2 Rotate operations

1. SHL/SAL instruction
Both the instruction shifts each bit to left, and places the MSB in CF and LSB is
made 0. The destination can be of byte size or of word size, also it can be a register or a
memory location. Number of shifts is indicated by the count.

All flags are affected.

General Format:-

SAL/SHL destination, count

Example:-

MOV BL, B7H ; BL is made B7H

SAL BL, 1 ; shift the content of BL register one place to left.

Before execution,

CY B7 B6 B5 B4 B3 B2 B1 B0

0 1 0 1 1 0 1 1 1

       

25
 After the execution,

CY B7 B6 B5 B4 B3 B2 B1 B0

1 0 1 1 0 1 1 1 0

2. SHR instruction
This instruction shifts each bit in the specified destination to the right and 0 is
stored in the MSB position. The LSB is shifted into the carry flag. The destination can be of
byte size or of word size, also it can be a register or a memory location. Number of shifts is
indicated by the count.

All flags are affected

General Format:-

SHR destination, count

Example:-

MOV BL, B7H ; BL is made B7H

SHR BL, 1 ; shift the content of BL register one place to the right.

Before execution,

B7 B6 B5 B4 B3 B2 B1 B0 CY

1 0 1 1 0 1 1 1 0

       
After execution,

B7 B6 B5 B4 B3 B2 B1 B0 CY

0 1 0 1 1 0 1 1 1

3. ROL instruction

This instruction rotates all the bits in a specified byte or word to the left some
number of bit positions. MSB is placed as a new LSB and a new CF. The destination can be of
byte size or of word size, also it can be a register or a memory location. Number of shifts is
indicated by the count.

All flags are affected

General Format:-

ROL destination, count

26
 Example:-

MOV BL, B7H ; BL is made B7H

ROL BL, 1 ; rotates the content of BL register one place to the left.

Before execution,

CY B7 B6 B5 B4 B3 B2 B1 B0

0 1 0 1 1 0 1 1 1

        (B7)

After the execution,

CY B7 B6 B5 B4 B3 B2 B1 B0

1 0 1 1 0 1 1 1 1

4. ROR instruction
This instruction rotates all the bits in a specified byte or word to the right some
number of bit positions. LSB is placed as a new MSB and a new CF. The destination can be of
byte size or of word size, also it can be a register or a memory location. Number of shifts is
indicated by the count.

All flags are affected

General Format:-

ROR destination, count

Example:-

MOV BL, B7H ; BL is made B7H

ROR BL, 1 ; shift the content of BL register one place to the right.

Before execution,

B7 B6 B5 B4 B3 B2 B1 B0 CY

1 0 1 1 0 1 1 1 0

(B0)        

After execution,

B7 B6 B5 B4 B3 B2 B1 B0 CY

27
 1 1 0 1 1 0 1 1 1

5. RCR instruction

This instruction rotates all the bits in a specified byte or word to the right some
number of bit positions along with the carry flag. LSB is placed in a new CF and previous carry
is placed in the new MSB. The destination can be of byte size or of word size, also it can be a
register or a memory location. Number of shifts is indicated by the count.

All flags are affected

General Format:-

RCR destination, count

Example:-

MOV BL, B7H ; BL is made B7H

RCR BL, 1 ; shift the content of BL register one place to the right.

Before execution,

B7 B6 B5 B4 B3 B2 B1 B0 CY

1 0 1 1 0 1 1 1 0

(CY)        

After execution,

B7 B6 B5 B4 B3 B2 B1 B0 CY

0 1 0 1 1 0 1 1 1

Program control transfer instructions

There are 2 types of such instructions. They are,

ii. Unconditional transfer instructions – CALL, RET, JMP

iii. Conditional transfer instructions – J condition
1. CALL instruction

The CALL instruction is used to transfer execution to a subprogram or procedure.

There are two types of CALL instructions, near and far.

28
 A near CALL is a call to a procedure which is in the same code segment as the
CALL instruction. 8086 when encountered a near call, it decrements the SP by 2 and copies
the offset of the next instruction after the CALL on the stack. It loads the IP with the offset of
the procedure then to start the execution of the procedure.

A far CALL is the call to a procedure residing in a different segment. Here value
of CS and offset of the next instruction both are backed up in the stack. And then branches to
the procedure by changing the content of CS with the segment base containing procedure
and IP with the offset of the first instruction of the procedure.

Example:-

Near call

CALL PRO ; PRO is the name of the procedure

CALL CX ; Here CX contains the offset of the first instruction of the

procedure, that is replaces the content of IP with the
content of CX

Far call

CALL DWORD PTR[8X] ; New values for CS and IP are fetched from four memory
locations in the DS. The new value for CS is fetched from
[8X] and [8X+1], the new IP is fetched from [8X+2] and
[8X+3].

2. RET instruction
RET instruction will return execution from a procedure to the next instruction
after the CALL instruction in the calling program. If it was a near call, then IP is replaced with
the value at the top of the stack, if it had been a far call, then another POP of the stack is
required. This second popped data from the stack is put in the CS, thus resuming the
execution of the calling program.

A RET instruction can be followed by a number, to specify the parameters

passed.

RET instruction does not affect any flags.

General format:-

RET

29
Example:-

p1 PROC ; procedure declaration.

MOV AX, 1234h ;

RET ; return to caller.

p1 ENDP

3. JMP instruction
This is also called as unconditional jump instruction, because the processor
jumps to the specified location rather than the instruction after the JMP instruction. Jumps
can be short jumps when the target address is in the same segment as the JMP instruction or
far jumps when it is in a different segment.

General Format:-

JMP <target address>

Example:-

MOV AL,05H ;

JMP label1 ; jump over to label

MOV AL, 00H ;

label1: MOV [2000H], AL ;

RET ;

4. Conditional Jump (J cond)

Conditional jumps are always short jumps in 8086. Here jump is done only if the
condition specified is true/false. If the condition is not satisfied, then the execution proceeds
in the normal way.

There are many conditional jump instructions like

JC : Jump on carry (CF=set)

JNC : Jump on non carry (CF=reset)

JZ : Jump on zero (ZF=set)

JNO : Jump on overflow (OF=set)

Etc

30
5. Iteration control instructions
These instructions are used to execute a series of instructions some number of
times. The number is specified in the CX register, which will be automatically decremented in
course of iteration. But here the destination address for the jump must be in the range of -
128 to 127 bytes.

Instruction here are:-

LOOP : loop through the set of instructions until CX is 0

LOOPE/LOOPZ : here the set of instructions are repeated until CX=0 or ZF=0

LOOPNE/LOOPNZ : here repeated until CX=0 or ZF=1

MACHINE CONTROL INSTRUCTIONS

1. HLT instruction
The HLT instruction will cause the 8086 microprocessor to fetching and executing
instructions.

The 8086 will enter a halt state. The processor gets out of this Halt signal upon an interrupt
signal in INTR pin/NMI pin or a reset signal on RESET input.

General form:-

HLT

2. WAIT instruction
When this instruction is executed, the 8086 enters into an idle state. This idle
state is continued till a high is received on the TEST input pin or a valid interrupt signal is
received. Wait affects no flags. It generally is used to synchronize the 8086 with a peripheral
device(s).

3. ESC instruction
This instruction is used to pass instruction to a coprocessor like 8087. There is a 6
bit instruction for the coprocessor embedded in the ESC instruction. In most cases the 8086
treats ESC and a NOP, but in some cases the 8086 will access data items in memory for the
coprocessor

4. LOCK instruction
In multiprocessor environments, the different microprocessors share a system
bus, which is needed to access external devices like disks. LOCK instruction is given as prefix in
the case when a processor needs exclusive access of the system bus for a particular
instruction. It affects no flags.

31
Example:-

LOCK XCHG SEMAPHORE, AL : The XCHG instruction requires two bus

accesses. The lock prefix prevents another
processor from taking control of the system
bus between the 2 accesses

5. NOP instruction
At the end of NOP instruction, no operation is done other than the fetching and
decoding of the instruction. It takes 3 clock cycles. NOP is used to fill in time delays or to
provide space for instructions while trouble shooting. NOP affects no flags.

Flag manipulation instructions

1. STC instruction

This instruction sets the carry flag. It does not affect any other flag.

2. CLC instruction

This instruction resets the carry flag to zero. CLC does not affect any other flag.

3. CMC instruction
This instruction complements the carry flag. CMC does not affect any other flag.

4. STD instruction
This instruction is used to set the direction flag to one so that SI and/or DI can be
decremented automatically after execution of string instruction. STD does not affect any
other flag.

5. CLD instruction
This instruction is used to reset the direction flag to zero so that SI and/or DI can
be incremented automatically after execution of string instruction. CLD does not
affect any other flag.

6. STI instruction
This instruction sets the interrupt flag to 1. This enables INTR interrupt of the
8086. STI does not affect any other flag.

7. CLI instruction
This instruction resets the interrupt flag to 0. Due to this the 8086 will not
respond to an interrupt signal on its INTR input. CLI does not affect any other
flag.

32
 STRING INSTRUCTIONS
1. MOVS/MOVSB/MOVSW
These instructions copy a word or byte from a location in the data segment to a
location in the extra segment. The offset of the source is in SI and that of destination is in DI.
For multiple word/byte transfers the count is stored in the CX register.

When direction flag is 0, SI and DI are incremented and when it is 1, SI and DI are
decremented.

MOVS affect no flags. MOVSB is used for byte sized movements while MOVSW is
for word sized.

Example:-

CLD ; clear the direction flag to auto increment SI and DI

MOV AX, 0000H ;

MOV DS, AX ; initialize data segment register to 0

MOV ES, AX ; initialize extra segment register to 0

MOV SI, 2000H ; Load the offset of the string1 in SI

MOV DI, 2400H ; Load the offset of the string2 in DI

MOV CX, 04H ; load length of the string in CX

REP MOVSB ; decrement CX and MOVSB until CX will be 0

2. REP/REPE/REP2/REPNE/REPNZ
REP is used with string instruction; it repeats an instruction until the specified
condition becomes false.

REP => CX=0

REPE/REPZ => CX=0 OR ZF=0

REPNE/REPNZ => CX=0 OR ZF=1

3. LODS/LODSB/LODSW
This instruction copies a byte from a string location pointed to by SI to AL or a
word from a string location pointed to by SI to AX.LODS does not affect any flags. LODSB
copies byte and LODSW copies word.

33
Example:-

CLD ; clear direction flag to auto increment SI

MOV SI, OFFSET S_STRING ; point SI at string

LODS S_STRING ;

4. STOS/STOSB/STOSW
The STOS instruction is used to store a byte/word contained in AL/AX to the
offset contained in the DI register. STOS does not affect any flags. After copying the content
DI is automatically incremented or decremented, based on the value of direction flag.

Example:-

MOV DL, OFFSET D_STRING ; assign DI with destination address.

STOS D_STRING ; assembler uses string name to determine byte or

word, if byte then AL is used and if of word size, AX
is used.

5. CMPS/CMPSB/CMPSW
CMPS is used to compare the strings, byte wise or word wise. The comparison is
effected by subtraction of content pointed by DI from that pointed by SI. The AF, CF, OF,
PF, SF and ZF flags are affected by this instruction, but neither operand is affected.

Example

MOV SI, OFFSET F_STRING ; point first string

MOV DI, OFFSET S_STRING ; point second string

MOV CX, 0AH ; set the counter as 0AH

CLD ; clear direction flag to auto increment

REPE CMPSB ; repeatedly compare till unequal or counter =0

34
 PIN DIAGRAM OF 8086 MICROPROCESSOR

The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40
pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor
configuration to achieve high performance. The pins serve a particular function in minimum
mode (single processor mode) and other function in maximum mode configuration
(multiprocessor mode).
The minimum mode is selected by applying logic 1 to the MN / input pin. This is a single
microprocessor configuration.

The maximum mode is selected by applying logic 0 to the MN / input pin. This is a multi
micro processors configuration.

The figure.1 below shows the pins/signals of 8086 processor. Here the pins within the brackets
(minimum mode pins) are minimum mode pins.

FIG.1 PIN DIAGRAM OF 8086 MICROPROCESSOR

35
Signal description:

The 8086 signals can be categorized in three groups.

The first are the signal having common functions in minimum as well as maximum
mode.
The second are the signals which have special functions for minimum mode.
Third are the signals which have special functions for maximum mode.

 The following signal descriptions are common for both modes:

Vcc: It requires +5V single power supply for the operation of the internal circuit.

GND: ground for the internal circuit.

AD15-AD0: These are the time multiplexed memory I/O address and data lines. These lines serve
two functions. The 16 data bus lines D0 through D15 are actually multiplexed with address lines
A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus
during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0
LSB. When acting as a data bus, they carry read/write data for memory, input/output data for
I/O devices, and interrupt type codes from an interrupt controller.

A19/S6, A18/S5, A17/S4, and A16/S3: These are the time multiplexed address and status lines.
During T1 these are the most significant address lines for memory operations. During I/O
operations, these lines are low. During memory or I/O operations, status information is
available on those lines for T2, T3, Tw and T4.
The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. The
status is displayed on S5 pin.
The S4 and S3 combinedly indicate which segment register is presently being used for memory
accesses as in below fig.
The last status bit S6 is always at the logic 0 level.
The address bits are separated from the status bit using latches controlled by the ALE signal.

/S7: The bus high enable is used to indicate the transfer of data over the higher order
(D15-D8) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used

36
to derive chip selects of odd address memory bank or peripherals. is low during T1 for
read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher
byte of data bus.

(Read): This signal on low indicates the peripheral that the processor is performing s
memory or I/O read operation. is active low and shows the state for T2, T3, and Tw of any
read cycle. The signal remains tristated during the hold acknowledge.
READY: This is the acknowledgement from the slow device or memory that they have completed
the data transfer. This signal is provided by an external clock generator device and can be
supplied by the memory or I/O subsystem to signal the 8086 when they are ready to permit the
data transfer to be completed.
NMI-Non maskable interrupt: This is an edge triggered input which causes a type2 interrupt.
The NMI is not maskable internally by software. A transition from low to high initiates the
interrupt response at the end of the current instruction.

INTR: INTR is an input to the 8086 that can be used by an external device to signal that it needs
to be serviced. Logic 1 at INTR represents an active interrupt request. When an interrupt
request has been recognized by the 8086, it indicates this fact to external circuit with pulse to
logic 0 at the output.

TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will
continue, else the processor remains in an idle state.

CLK: Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. Its an asymmetric square wave with 33% duty cycle.

RESET: This input causes the processor to terminate the current activity and start execution
from FFFF0H.

MN/ : The logic level at this pin decides whether the processor is to operate in either
minimum or maximum mode.

 The following pin functions are for the minimum mode operation of 8086:

M/ : This is a status line logically equivalent to S2 in maximum mode. The logic level of M/
tells external circuitry whether a memory or I/O transfer is taking place over the bus. When it is
low, it indicates the processor is having an I/O operation, and when it is high, it indicates that the
processor is having a memory operation.

37
 : The signal write indicates that a write bus cycle is in progress. The 8086 switches
to logic 0 to signal external device that valid write or output data are on the bus.

: (Interrupt Acknowledge)-This signal is used as a read strobe for interrupt acknowledge

cycles. i.e. when it goes low, the processor has accepted the interrupt.

ALE – Address Latch Enable: This output signal indicates the availability of the valid address on
the address/data lines, and is connected to latch enable input of latches. This signal is active
high and is never tristated.

DT/ – Data Transmit/Receive: This output is used to decide the direction of data flow through
the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high
and when the processor is receiving data, this signal is low.

– Data Enable: This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transreceivers (bidirectional buffers) to separate the data from the
multiplexed address/data signal.

HOLD and HLDA: The direct memory access DMA interface of the 8086 minimum mode consist
of the HOLD and HLDA signals. When the HOLD line goes high, it indicates to the processor that
another master is requesting the bus access. The processor, after receiving the HOLD request,
issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after
completing the current bus cycle.

The following pin functions are applicable for maximum mode operation of 8086 :
, , and – Status Lines: These are the status lines which reflect the type of operation,
being carried out by the processor.

38
LOCK: This output pin indicates that other system bus master will be prevented from gaining
the system bus, while the LOCK signal is low.

QS1, QS0 – Queue Status: These lines give information about the status of the code-prefetch
queue. Two new signals that are produced by the 8086 in the maximum-mode system are
queue status outputs QS0 and QS1. Together they form a 2-bit queue status code, QS1QS0.
Following table shows the four different queue status.

RQ0/0GT, RQ1/GT1 – Request/Grant: These pins are used by the other local bus master in
maximum mode, to force the processor to release the local bus at the end of the processor
current bus cycle. Each of the pin is bidirectional with RQ/GT0 having higher priority than
RQ/GT1.

TIMINGS:

Timing plays a crucial role, not only in sports like cricket but also in digital electronic
equipments like microprocessors. Timing and Timing diagram plays a vital role in
microprocessors. The timing diagram is the diagram which provides information about the
various conditions of signals such as high/low, when a machine cycle is being executed. Without
the knowledge of timing diagram it is not possible to match the peripheral devices to the
microprocessors. These peripheral devices includes memories, ports etc. Such devices can only
be matched with microprocessors with the help of timing diagram.

Before dealing with timing diagram, we have to make ourselves familiar with certain terms.

Machine cycle: A basic microprocessor operation such as reading a byte from memory or
writing a byte to a port is called a machine cycle (Bus cycle). A machine cycle consists of at least
4 clock cycles/ clock states (T-states) for accessing the data.

Instruction cycle: The time a microprocessor requires to fetch and execute an entire instruction
is referred to as an instruction cycle. An instruction cycle consists of one or more machine
cycles.

39
T-state: T-state is nothing but one subdivision of the operation performed in one clock period.
These subdivisions are internal state of the microprocessor synchronized with system clock.

So, an instruction cycle is made up of machine cycles, and a machine cycle is made up of states.
The time for the state is determined by the frequency of the clock signal.

GENERAL BUS OPERATION:

The 8086 has a combined address and data bus commonly referred as a time
multiplexed address and data bus. The main reason behind multiplexing address and data over
the same pins is the maximum utilization of processor pins and it facilitates the use of 40 pin
standard DIP package. The bus can be demultiplexed using a few latches and transreceivers,
when ever required. Basically, all the processor bus cycles consist of at least four clock cycles.
These are referred to as T1, T2, T3, and T4. The address is transmitted by the processor during
T1. It is present on the bus only for one cycle.

The above figs shows the signal activities on the 8086 microcomputer buses during
simple read and write operations. The first line look at is the clock waveform, CLK, at the top.
This represent s the crystal controlled clock signal sent to the 8086 from an external clock
generator device such as the 8284. One clock cycle of this clock is called a state. The time
interval labeled T1 in the figure is an example of a state. Different versions of the 8086 have
maximum clock frequencies of between 5 MHz and 10 MHz, so the minimum time for one sate
will be between 100 and 200ns, depending on the part use and the crystal used.

The negative edge of this ALE pulse is used to separate the address and the data or
status information. In maximum mode, the status lines , and are used to indicate the
type of operation. Status bits S3 to S7 are multiplexed with higher order address bits and the
BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.

40
 Fig. General bus operation timing diagram

8086 Bus activities during a Read machine cycle:

Fig above (left half portion) shows the timing diagram of 8086 read machine cycle with
WAIT state. The clock (CLK) signal is obtained from the clock-generator 8284. Each cycle of the
clock is referred to as a state. Minimum number of states to access a data is four. They are T1,
T2, T3, and T4 states.

During T1 state of a read machine cycle an 8086 first asserts the M/ IO signal. It will
assert this signal high if it is going to read from memory during memory read cycle and it will
assert M/ IO low if it is going to do a read from an Input port during its read cycle. The timing
diagram in fig shows two lines for the M/ IO signal, because the signal may be going LOW or
going HIGH for a read cycle. The point where the two lines cross indicate the time at which the
signal becomes valid for this machine cycle.

After asserting M/ IO , the 8086 sends out a high on the address latch enable signal, ALE.
The microprocessor sends out on AD0-AD15, A16 through A19 and BHE lines, and the address
of the memory location that it wants to read. Since the latches are enabled by ALE being high,

41
this address information passes through the latches to their outputs. The 8086 then makes the
ALE output low. This disables the latches (8282) and holds the address information latched on
the latch outputs. The address information latched on the latch outputs can now be used to
select the desired memory or port location.

In the timing diagram, the first point at which the two (AD 0 – AD15) cross represents the
time at which the 8086 has put a valid address on these lines. Two lines DO NOT indicate that
all 16 lines are going high or going low at this point. The crossed lines indicate the time at
which a valid address is on the bus.

Since the address information is now held on the latch, the 8086 does not need to send
it out any more. As shown in fig. 12 the 8086 floats the AD0 - AD15 lines so that they can be
used to input data from memory or from a port. At about the same time the 8086 also remove
the BHE and A16-A19 information from the upper lines and sends out some status information
on these lines.

The 8086 is now ready to read data from the addressed memory locations or port.
During T2-state the 8086 asserts its RD signal low. This signal is used to enable the addressed
memory device or port device.

At the end of T3 state the microprocessor makes the RD signal high and reads the data
available on the data bus, provided the READY input signal is high. It is the duty of the external
circuit to see that valid data is made available on the data bus.

If the READY input pin is not high at the sampled time in a machine cycle, the 8086 will
insert one or more WAIT states between T3 and T4 states in that machine cycle. An external
hardware device is set up to pulse READY low before the rising edge of the clock in T2 state.
After the 8086 finishes T3 of the machine cycle, it enters a WAIT state.

If the READY input is still low at the end of a WAIT state, then the 8086 will insert
another WAIT state. The 8086 will continue inserting WAIT states until the READY input is
sampled high again. If the READY input is sampled high again during T3 or during the WAIT
state, the microprocessor comes out of the WAIT state and will initiate T4 of the machine cycle.

The DEN signal is used to enable bi-directional buffers on the data bus. The data enable
signal, DEN, from the 8086 will enable the data buffer when it is asserted LOW. The data
transmit / receive signal DT/ R from the 8086 is used to specify the direction in which the
buffers are enabled. When DT/ R is asserted high, the buffers will, if enabled by DEN, transmit
data from the 8086 to Memory or I/O ports. When DT/ R is asserted low, the buffers, if
enabled by DEN, will allow data to be received from Memory or I/O ports of the 8086. DT/ R is

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asserted during T1 of the machine cycle. The DEN is asserted after the 8086 finishes using the
data bus to send the lower 16 address bits

8086 Bus activities during write machine cycle:

The 8086 write operation is very similar to the read cycle. During T1 of a write machine
cycle the 8086 asserts M/ IO low if the write is going to a port and it asserts M/ IO high if the
write is going to memory. At about the same time the 8086 raises ALE high to enable the
address latches. The 8086 then assert BHE and on the lines AD0 - AD19, it output the address
that it will be writing to. When writing to a port, line A16 - A19 will always be low, because the
8086 only sends out 16-bits port addresses. The 8086 brings ALE low again to latch the address
on the outputs of the latches. In addition to holding the address, the latches also function as
buffers for the address lines. After the address information is latched, the 8086 remove the
address information from AD0 - AD15 and outputs the desired data on these lines.

If the READY input is sampled LOW by the 8086 before or during T2 of the machine cycle,
the 8086 will insert a WAIT state after T3. If the READY input is sampled high before the end of
the WAIT state, the 8086 will go on with state T4 as soon as it completes the WAIT state. The
8086 will continue to insect wait states for as long as the READY is sampled low just before
the end of each WAIT state.

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 MINIMUM MODE 8086 SYSTEM AND TIMINGS

Fig: Minimum mode 8086 system

.In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/ pin to logic 1. In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the minimum mode system. The
remaining components in the system are latches, transreceivers, clock generator, memory and
I/O devices. Some type of chip selection logic may be required for selecting memory or I/O
devices, depending upon the address map of the system.
•Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for
separating the valid address from the multiplexed address/data signals and are controlled by
the ALE signal generated by 8086.

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.Transreceivers are the bidirectional buffers and sometimes they are called as data amplifiers.
They are required to separate the valid data from the time multiplexed address/data signals.
They are controlled by two signals namely, and DT/ . The DT/ signal indicates the
direction of data, i.e. from or to the processor. The system contains memory for the monitor
and users program storage.
•Usually, EPROM is used for monitor storage, while RAM for user’s program storage. A system
may contain I/O devices.
•The working of the minimum mode configuration system can be better described in terms of
the timing diagrams rather than qualitatively describing the operations.
•The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in
two parts, the first is the timing diagram for read cycle and the second is the timing diagram for
write cycle.

Read Cycle:
The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M /
signal. During the negative going edge of this signal, the valid address is latched on the local
bus.
•The and A0 signals address low, high or both bytes. From T1 to T4, the M/ signal
indicates a memory or I/O operation.
•At T2, the address is removed from the local bus and is sent to the output. The bus is then
tristated. The read ( ) control signal is also activated in T2.
•The read ( ) signal causes the address device to enable its data bus drivers. After goes
low, the valid data is available on the data bus.
•The addressed device will drive the READY line high. When the processor returns the read
signal to high level, the addressed device will again tristate its bus drivers. CS logic indicates
chip select logic and ‘e’ and ‘o’ suffixes indicate even and odd address memory banks.

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 Fig. Read cycle timing diagram for minimum mode operation

Write Cycle:
•A write cycle also begins with the assertion of ALE and the emission of the address. The M/
signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address
in T1, the processor sends the data to be written to the addressed location.
•The data remains on the bus until middle of T4 state. The becomes active at the beginning
of T2 (unlike is somewhat delayed in T2 to provide time for floating).
•The and A0 signals are used to select the proper byte or bytes of memory or I/O word to
be read or write.

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 Fig. Write cycle timing diagram for minimum mode operation

The M/ , and signals indicate the type of data transfer as specified in table below.

MAXIMUM MODE 8086 SYSTEM AND TIMINGS

When the 8086 is set for the maximum-mode configuration, it provides signals for
implementing a multiprocessor / coprocessor system environment. By multiprocessor
environment we mean that one microprocessor exists in the system and that each processor is
executing its own program. Usually in this type of system environment, there are some system
resources that are common to all processors. They are called as global resources. There are also
other resources that are assigned to specific processors. These are known as local or private
resources. Coprocessor also means that there is a second processor in the system. In this two
processor does not access the bus at the same time. One passes the control of the system bus
to the other and then may suspend its operation. In the maximum-mode 8086 system, facilities

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are provided for implementing allocation of global resources and passing bus control to other
microprocessor or coprocessor.

Fig: Maximum mode 8086 system

•In the maximum mode, the 8086 is operated by strapping the MN/ pin to ground. In this
mode, the processor derives the status signal , , . Another chip called bus controller
derives the control signal using this status information. In the maximum mode, there may be
more than one microprocessor in the system configuration. The components in the system are
same as in the minimum mode system.
•The basic function of the bus controller chip IC8288 is to derive control signals like and
(for memory and I/O devices), , DT/ , ALE etc. using the information by the processor
on the status lines.
•The bus controller chip has input lines , , and CLK. These inputs to 8288 are driven by
CPU.

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•It derives the outputs ALE, , DT/ , , , , , and .
The AEN, IOB and CEN pins are specially useful for multiprocessor systems.
•AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the
MCE/PDEN output depends upon the status of the IOB pin.
•If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as
peripheral data enable used in the multiple bus configurations.
• pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an
interrupting device.
• , are I/O read command and I/O write command signals respectively. These
signals enable an IO interface to read or write the data from or to the address port.
•The , are memory read command and memory write command signals
respectively and may be used as memory read or write signals.
•All these command signals instructs the memory to accept or send data from or to the bus.
•For both of these write command signals, the advanced signals namely and
are available.
•Here the only difference between in timing diagram between minimum mode and maximum
mode is the status signals used and the available control and advanced command signals.
•R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on
the ALE and apply a required signal to its DT / R pin during T1.
•In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or
IORC. These signals are activated until T4. For an output, the AMWC or AIOWC is activated from
T2 to T4 and MWTC or IOWC is activated from T3 to T4.
•The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
•If reader input is not activated before T3, wait state will be inserted between T3 and T4.

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