EE 457

Digital Integrated Circuits

Lecture 01: Introduction

Dr. Bruce Kim

Note: Do not disseminate this lecture note without consent.

(Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.)

Course Details:
• Required Textbook
Digital Integrated Circuits: A Design Perspective by Jan Rabaey, 2nd
Edition, Prentice-Hall
• Instructor: Prof. Bruce C. Kim
Phone: 212-650-5446
Office Hours: ST-630, Monday, & Wed. 2PM-3:00PM or by
appointment

2
 Course Objective
 This course is intended for undergraduate students who want to
learn integrated circuit design, CMOS process and VLSI circuit
simulations.
 This course will expose you to software tools for circuit analysis
and chip layout design.
 Course prerequisites
 EE 241, Electronics I.

Grading Policy
 Final grades will be determined on the basis of the following
100% total scale.
 The final grade will be based on the overall points from all of the
categories.
 A standard 10 point scale will be used.
 The final grades may be scaled.
 Any questions about grading must be brought to the attention of
the instructor within 1 week of the date the material was returned.
After this time, no grades will be changed.

4
 Grading
 Grade Scale: There is no concrete set percentage assigned to each
grade. However, a standard 10 point scale will be used as a guide. A
student who receives below 60% gets a final grade of “F” in the
course. The final grades will be distributed by the instructor’s
discretion.

Categories EE457
Exam 20%
HW’s 20%
Project #1 10%
Project #2 15%
Project #3 15%
Final Project 20%

Course Structure
• Learning Electric Layout Tool & LT SPICE Simulations
• Lectures:
 2 weeks on the CMOS inverter
 4 weeks on static and dynamic CMOS circuits
 1 week on R, C, and L parasitic effects
 2 weeks on CMOS sequential circuits
 2 weeks on design of dynamic CMOS, routing, clocking, layouts, etc.
 1 week on CMOS memory design
 2 weeks on design for test, packaging, scaling, trends
 1 week on cyber security hardware
 1 week exam

6
 Attendance Policy
 Your attendance is mandatory.
 Missing more than two classes could result in receiving a grade of
“WU”.
 You must sign both attendance sheets to get full attendance credit.
 Subtract 1% for missing more than 4 lectures
 Add 1% for a perfect attendance.

Policy of Missed Exams & Coursework

• Policy on Missed Exams:
• If you are sick, you must provide doctor’s note. You
must provide proof of special circumstances. A
student must get instructor’s permission before the
test is given.
• Class Make-Up:
• Due to attending research meetings, conferences and
site visits for my research, there may be a conflict
with the class schedule. I will announce any class
conflicts due to travel in class and Blackboard.
8
 Special Notes
• Cell phones: Turn off your cell phone and no
texting allowed.
• Laptops: Do not use your laptops to see my
notes and no reading emails.

Any Questions?

10
 Electric Download Link
• Electric download link:
http://cmosedu.com/cmos1/electric/electric.htm

• Electric lecture videos – Prof. David Baker

http://cmosedu.com/videos/electric/electric_vid
eos.htm

• LTSpice Download link

http://www.linear.com/designtools/software/#LTspice

11

Vacuum Tube

12
 First Computer
• ENIAC
Eckert and Mauchly

• 1st working electronic

computer (1946)
• 18,000 Vacuum tubes
• 1,800 instructions/sec
• 3,000 ft3

13

IBM Computer

14
 Transistor History
• Transistor –William Shockley, Walter Brattain, John Bardeen
(Bell Labs) in 1947
• Bipolar transistor – Schockley in 1949
• First bipolar digital logic gate – Harris in 1956
• First monolithic IC – Jack Kilby in 1959
• First commercial IC logic gates – Fairchild 1960
• TTL – 1962 into the 1990’s
• ECL – 1974 into the 1980’s

15

16
 Infancy of Transistors and ICs

Point-Contact Transistor, 1947

Silicon-based Junction Integrated Circuit (IC), 1958
Bell Labs (William Shockley,
Transistor, 1954 Texas Texas Instruments (Jack
Walter Brattain*, John
Instruments (Gordon Teal) Kilby*) & Fairchhild
Bardeen**)
Semiconductor (Robert Noyce)

Planar Transistor, Monolithic Risitor-Transistor Logic, Metal Oxide Semiconductor,

1959 Fairchild 1961 1968
Semicondcutor (Jean Fairchild Semiconductor (Robert
Noyce) Fairchild Semiconductor
Hoerni)
Source: SIA
17

MOSFET Technology
• CMOS – 1980’s, but plagued with manufacturing
problems
• PMOS in 1960’s (calculators)
• NMOS in 1970’s (4004, 8080) – for speed
• CMOS in 1980’s – preferred MOSFET technology
because of power benefits
• BiCMOS, Gallium-Arsenide, Silicon-Germanium

18
 Moore’s Law

• In 1965, Gordon Moore predicted that the number of transistors

that can be integrated on a die would double every 18 months
(i.e., grow exponentially with time).
• Amazingly visionary – million transistor/chip barrier was crossed
in the 1980’s.
 2300 transistors, 1 MHz clock (Intel 4004) - 1971
 16 Million transistors (Ultra Sparc III)
 42 Million, 2 GHz clock (Intel P4) - 2001
 140 Million transistor (HP PA-8500)

19

Moore’s Law in Microprocessors

Transistors on lead microprocessors double every 2 years

1000

2X growth in 1.96 years!

100
Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
Courtesy, Intel 20
 Intel 4004 Microprocessor
• Introduced in 1971
• 1 MHz clock rate
• 5V VDD
• 10 micron technology
• 5K transistors

Source: J. Rabaey et al
21

Intel Pentium (IV) Microprocessor

Source: J. Rabaey et al
22
 Intel Pentium 5 vs. Pentium 6

P5 P6 (Pentium Pro)
Introduced P5 introduced in 1994 P6 introduced in 1996

Clock Rate 75 to 100 MHz 150 to 200 MHz

Size 91 mm2 196 mm2
Number of Transistors 3.3M transistors 5.5M transistors

Cache 1M in cache external cache

Technology 0.35 micron 0.35 micron
Drive Voltage 3.3volt VDD 3.3volt VDD
Power Consumption >20W typical >20W typical

23

Evolution in DRAM Chip Capacity

human memory
100000000
human DNA
64,000,000

10000000
4X growth every 3 years! 16,000,000 0.07 m
4,000,000
0.1 m
K b it c a p a c ity /c h ip

1000000 1,000,000
0.13 m
256,000 0.18-0.25 m
book
100000
64,000
0.35-0.4 m
16,000
10000 0.5-0.6 m
4,000 encyclopedia
0.7-0.8 m
1000 1,000 2 hrs CD audio
1.0-1.2 m 30 sec HDTV
256
100 1.6-2.4 m
64
page
10
1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

Year
24
 Die Size Growth
Die size grows by 14% to satisfy Moore’s Law

100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year
Courtesy, Intel 25

Clock Frequency
Lead microprocessors frequency doubles every 2 years

10000

1000 2X every 2 years

Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Courtesy, Intel 26
 Power Dissipation
Lead Microprocessors power continues to increase
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Power delivery and dissipation will be prohibitive

Courtesy, Intel 27

Design Productivity Trends

10,000 100,000
Logic Transistor per Chip (M)

1,000 Logic Tr./Chip 10,000

Tr./Staff Month.
(K) Trans./Staff - Mo.

100 1,000
Complexity

Productivity

10 58%/Yr. compounded 100

Complexity growth rate

1 10

x x
0.1 1
xx 21%/Yr. compound
x x x
x Productivity growth rate
0.01 0.1

0.001 0.01
1989

2003

2005
1991
1993

1995
1997

1999

2001
1985

1987

2007
1981

1983

2009

Complexity outpaces design productivity

Courtesy, ITRS Roadmap 28

 Fundamental Design Metrics
• Functionality
• Cost
NRE (fixed) costs - design effort
RE (variable) costs - cost of parts, assembly, test
• Reliability, robustness
Noise margins
Noise immunity
• Performance
Speed (delay)
Power consumption; energy
• Time-to-market

29

Cost of Integrated Circuits

• NRE (non-recurring engineering) costs
• Fixed cost to produce the design
design effort
design verification effort
mask generation
• Influenced by the design complexity and designer productivity
• More pronounced for small volume products
• Recurring costs – proportional to product volume
• silicon processing
also proportional to chip area
• assembly (packaging)
• test
fixed cost
cost per IC = variable cost per IC + -----------------
volume
30
 Silicon Wafer
Single die

Wafer

Package

From http://www.amd.com

31

Recurring Costs
cost of die + cost of die test + cost of packaging
variable cost = ----------------------------------------------------------------
final test yield
cost of wafer
cost of die = ------------------------------------------
dies per wafer × die yield

die yield = (1 + (defects per unit area × die area)/)-

32
 Yield Example
• Example
 wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,
 = 3 (measure of manufacturing process complexity)

 252 die/wafer (remember, wafers round & dies square)

die yield = (1 + (1 × 2.5)/3)-3 = 0.16

 die yield of 16%
 252 x 16% = only 40 dies/wafer are good!

33

Cost Calculations
cost of wafer
cost of die = ------------------------------------------
die per wafer × die yield

• Die cost is strong function of die area

 proportional to the third or fourth power of the die area

• Given 252 die/wafer, 16% die yield, and $100 for 12” wafer
• Find die cost

$100
cost of die = ------------------------------------------ = $2.48
252× 0.16
• If die yield increased to 80%, then each die will cost $0.50

34
 ITRS Technology Roadmap
Year 1999 2002 2005 2008 2011 2014
Feature size (nm) 180 130 100 70 50 35
Mtrans/cm2 7 14-26 47 115 284 701
Chip size (mm2) 170 170-214 235 269 308 354
Signal pins/chip 768 1024 1024 1280 1408 1472
Clock rate (MHz) 600 800 1100 1400 1800 2200
Wiring levels 6-7 7-8 8-9 9 9-10 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6
High-perf power (W) 90 130 160 170 174 183
Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4
For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999
doubling every two years)

http://www.itrs.net/ntrs/publntrs.nsf

35

Why Scaling?
 Technology shrinks by ~0.7 per generation
 With every generation can integrate 2x more functions on a chip;
chip cost does not increase significantly
 Cost of a function decreases by 2x
 But …
 How to design chips with more and more functions?
 Design engineering population does not double every two years…
 Hence, a need for more efficient design methods
 Exploit different levels of abstraction

36
 Design Abstraction Levels

SYSTEM

MODULE
+

GATE

CIRCUIT
Vin Vout

DEVICE
G
S D
n+ n+

37

Abstraction level – Double Stage Opamp

Circuit level schematic

Device Layout
38
 Design Challenges
 Microscopic issues  Macroscopic issues
 ultra-high speeds  time-to-market
 power dissipation and supply  design complexity
rail drop (millions of gates)
 growing importance of  high levels of abstractions
interconnect  reuse and IP, portability
 noise, crosstalk  systems on a chip (SoC)
 reliability, manufacturability  tool interoperability
 clock distribution

39

MOS Symbols
Analog and RF
Digital

Source - CMOS design, Razavi 40

MOS Transistor Structure

Polysilicon Aluminum

41

Device Fabrication

42
 Why Silicon

= 5.4x10-8 cm

43

Doping (Adding Impurities)

• To change the conductivity of a semiconductor

44
 Adjusting Conductivity
• Donors (Phosphorus) increases increases electron- movement.
• Acceptors (Boron) increases hole+ movement.

45

Silicon Dioxide
• Under exposure to oxygen, a silicon surface oxidizes to form silicon
dioxide (SiO2). Native silicon dioxide is a high-quality electrical insulator
and can be used as a barrier material during impurity implants or diffusion,
for electrical isolation of semiconductor devices, as a component in MOS
transistors, or as an interlayer dielectric in multilevel metallization
structures such as multichip modules. The ability to form a native oxide
was one of the primary processing considerations which led to silicon
becoming the dominant semiconductor material used in integrated circuits
today. (900-1200 degrees C)

46
 Photolithography
• Positive and negative photoresists

Polymized where
Soluble where exposed to UV
exposed to UV

47

Photolithography

48
 Diffusion
• In integrated circuit fabrication, diffusion is used to introduce
dopants in controlled amounts into the semiconductor substrate. In
particular, diffusion is used to:
form the base and emitter in bipolar transitors
form integrated resistors
form the source/drain regions in MOS transistors
dope polysilicon gates in MOS transistors

Negative sign for flow into

decreasing concentration.

J=Particle flux, C=concentration of solute, D=diffusion coefficient, x=distance

49

Diffusion Equipment
• Boron furnace set to 600 degrees C.

50
 Sample Process
Si Chemical etch

SiO2

etch
Photoresist

SiO2
mask

51

NMOS Fabrication Process

metal
Si P substrate etch
Si
Si n+
Oxide 3
Si etch
2 Si Metal contacts
1
Si etch etch
doping Si n+
Si n+
Thin oxide
Si
Insulating
Si n+ oxide
Polysilicon
Si

52
Cross Section of CMOS Technology

53

Accumulation

54
Depletion

55

Inversion

56
 Transistor in Linear Mode
Assuming VGS > VT
VGS
VDS
S G
D ID

n+ - V(x) + n+

The current is a linear function of both VGS and VDS

57

Current Equations
• NMOS Drain current equations:
Linear Region

Saturation Region

58
Transistor in Saturation Mode
Assuming VGS > VT
VGS VDS > VGS - VT
VDS
S G
D ID

n+ - V -V + n+
GS T

Pinch-off

The current remains constant (saturates).

59

I-V Plot (NMOS)

6
X 10-4 VDS = VGS - VT VGS = 2.5V
5

4
VGS = 2.0V
3
Linear Saturation
2 VGS = 1.5V
1 VGS = 1.0V
0
0 0.5 1 1.5 2 2.5
cut-off
VDS (V)

NMOS transistor, 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

60
 I-V Plot (PMOS)
 All polarities of all voltages and currents are reversed
-2 VDS (V) -1 0
0

VGS = -1.0V -0.2

VGS = -1.5V -0.4

-0.6
VGS = -2.0V

-0.8
VGS = -2.5V
X 10-4
-1
PMOS transistor, 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V 61

NMOS Schematic - Electric

62
 NMOS – SPICE Code

Comments
and SPICE
start up code

NMOS netlist

63

LTSpice Output Waveform

64
 Electric Download Link
• Electric download link:
http://cmosedu.com/cmos1/electric/electric.htm

• Electric lecture videos – Prof. David Baker

http://cmosedu.com/videos/electric/electric_vid
eos.htm

• LTSpice Download link

http://www.linear.com/designtools/software/#LTspice

65