This document outlines 3 optional homework problems for an electronics engineering course. Problem 1 involves designing a dynamic NMOS gate circuit and cascading two gates. Problem 2 examines a cascaded dynamic NAND3 circuit with a logic glitch and proposes changing the clocking scheme to solve it, requiring LTSpice simulation. Problem 3 involves designing and simulating a 6-transistor SRAM circuit. Students can earn up to 5 extra credit points on their midterm for completing all problems.
This document outlines 3 optional homework problems for an electronics engineering course. Problem 1 involves designing a dynamic NMOS gate circuit and cascading two gates. Problem 2 examines a cascaded dynamic NAND3 circuit with a logic glitch and proposes changing the clocking scheme to solve it, requiring LTSpice simulation. Problem 3 involves designing and simulating a 6-transistor SRAM circuit. Students can earn up to 5 extra credit points on their midterm for completing all problems.
This document outlines 3 optional homework problems for an electronics engineering course. Problem 1 involves designing a dynamic NMOS gate circuit and cascading two gates. Problem 2 examines a cascaded dynamic NAND3 circuit with a logic glitch and proposes changing the clocking scheme to solve it, requiring LTSpice simulation. Problem 3 involves designing and simulating a 6-transistor SRAM circuit. Students can earn up to 5 extra credit points on their midterm for completing all problems.
This document outlines 3 optional homework problems for an electronics engineering course. Problem 1 involves designing a dynamic NMOS gate circuit and cascading two gates. Problem 2 examines a cascaded dynamic NAND3 circuit with a logic glitch and proposes changing the clocking scheme to solve it, requiring LTSpice simulation. Problem 3 involves designing and simulating a 6-transistor SRAM circuit. Students can earn up to 5 extra credit points on their midterm for completing all problems.
Note: This is optional HW. If you do all of it, I will give you 5 points on your midterm exam.
Problem 1: (40 points)
Construct a dynamic NMOS gate for the function f AB CD. 1) Draw a circuit schematic in Electric, 2) do a layout in electric and run IRSIM for verification, 3) do a truth table and compare your results with IRSIM. Cascade two of this complex gate in series making domino logic. Draw a circuit in Electric, but do not run simulation.
Problem 2: (40 points)
Consider the cascaded dynamic NAND3 circuit shown below. The circuit has a logic glitch problem. What happens to the behavior of the logic cascade if we change the clocking scheme so that (clock) is applied to the first stage, but (inverted clock) is applied to the second stage? Does this solve the glitch problem? Run LTSPICE using the models you used previously. Verify your results using the LTPICE. Assume transistor size ratio as (W/L)n = (3/2) and (W/L)p = (5/2). First verify the glitch problem using LTPICE. Then change your clocking as described to see if it took care of the problem. Hand in your LTPICE codes and waveforms for verification. Please label waveforms for easy identifications. Do only 2 or 3 waveforms. Make inputs to high logic states.
Vdd=5V
B1 A1 Vout,1 Vout,2
10fF 10fF A2 B2
A3 B3
I have attached some results below. You should try to get results similar to them below. Problem 3: (40 points)
Draw a schematic of 6-transistor SRAM and do layout using Electric. Run IRSIM to see if your design is working.
1) Hand in schematic 2) Hand in Layout 3) Hand in IRSIM simulation
