cHIPSET AND CONTROLLER
cHIPSET AND CONTROLLER
cHIPSET AND CONTROLLER
Characteristic that sets one chipset apart from another is whether it has one, two, or more chips in the set. The two-chip chipset, which contains what is called the north bridge and the south bridge, is the most common, but some manufacturers, such as SiS and VIA, produce mostly single chipsets today.
The south bridge includes the controllers for the peripheral devices and any controllers not essential to the PCs basic functions, such as the EIDE (Enhanced Integrated Device Electronics) controller and the serial port controllers.
The south bridge is typically only one chip and is common among all variations in a chipset family and even between manufacturers, such as the SiS 5513 and the Intel PIIX south bridge chips.
CONTROLLER CHIPS
Generally, a chipset does not incorporate all of the controllers used to direct the actions of every peripheral device on the PC. In addition to the chipset, there are at least two, and possibly more, controllers mounted directly on the motherboard. In most cases, the motherboard will have at minimum a keyboard controller and an I/O controller (a.k.a. the Super I/O controller). Some expansion cards, such as video adapters, sound cards, network interface cards (NICs), and SCSI (Small Computer System Interface) adapters, have built-in controller chips. Fundamentals of computer Hardware: C Kuranga 2
A controller chip controls the transfer of data to and from a peripheral device, such as a disk drive, the monitor, the keyboard, or a printer. All of these devices depend on a device controller to interact with the CPU and the rest of the PC. On a PC, a controller is typically a single chip that either mounts directly on the motherboard or on a card that is inserted in an expansion slot on the motherboard.
Because they control the flow of data to and from peripheral devices, controllers must be matched to the bus architecture of the PC.
Keyboard Controller
The keyboard controllers name describes what it doesit controls the keyboard. More specifically though, it controls the transfer of data from the keyboard to the PC. The keyboard controller on the motherboard interacts with a controller located inside the keyboard over a serial link built into the connecting cable and connector. When the keyboard controller receives data from the keyboard, it checks the datas parity, translates the scan code, places the data in its output buffer, and notifies the processor that the data is in its buffer. The keyboard controller is quite common on most older PCs, but newer PCs either include this control function in the chipset or in the Super I/O chip. The functions performed by the keyboard controller, or its equivalent, are as follows: a) Keyboard control and translation When a key is pressed on the keyboard, a scan code is sent from the controller inside the keyboard to PCs keyboard controller, which then signals the processor through IRQ1 (interrupt request 1). The keyboard controller then translates the scan code into the character it represents and places it on the bus to move it to the appropriate location in memory.
b) Support for the PS/2 mouse On those systems that have an integrated PS/2 connector on the motherboard, the keyboard controller supports its functions. This port is most commonly used to connect a PS/2-style mouse. c) Access to the HMA Although the support for the High Memory Area of system memory (RAM) is now incorporated into the system chipset on most newer PCs, access to this part of memory is controlled through the keyboard controller.
Each device controller must be matched to the bus interface with which it is to interact.
CHIPSETS
One of the fundamental design facts of a PC is that its microprocessor is always faster than the peripheral devices to which it must communicate. This fact has forced designers to develop interfaces that serve as buffers between the slower devices and the faster CPU to match up their speeds and help with the timing of the operations. The very first PCs had an individual chip to control each of the various operations. It was common for an early PC to have the following separate chips: the processor and math coprocessor. b) Clock generator This chip controls the timing of the PCs operations. c) Bus controller chip This chip controls the flow of data on the motherboards buses. d) DMA controller This chip controls the processes that allowed peripheral devices to interact with memory without involving the processor. e) Programmable peripheral interface (PPI) This chip supervises some of the simpler peripheral devices. f) Floppy disk controller (FDC) This chip controls the PCs diskette and tape drives. g) CRT controller This chip facilitates the PCs display. h) UART (universal asynchronous receiver transmitter) This chip is used to send and receive synchronous serial data. a) Math coprocessor interface This chip controls the flow of data between
Chipset Functions
A chipset integrates a number of VLSI (very large scale integration) chips that provide much of the PCs functionality. Each of the chips integrated into the chipset at one time could have easily been a stand-alone chip, but by combining them together into a single chip, Fundamentals of computer Hardware: C Kuranga 5
the controllers and devices combined into the chipset can share common actions, reduce the physical space required on the motherboard, and reduce costall very important considerations in todays PC market.
Chipset Characteristics
The characteristics of a chipset can be broken down into six categories: host, memory, interfaces, arbitration, south bridge support, and power management. Each of these categories defines and differentiates one chipset from another. The characteristics defined in each of these categories are as follows: a) Host This category defines the host processor to which the chipset is matched along with its bus voltage, usually GTL+ (Gunning Transceiver Logic Plus) or AGTL+ (Advanced Gunning Transceiver Logic Plus), and the number of processors the chipset will support. b) Memory This category defines the characteristics of the DRAM support included in the chipset, including the DRAM refresh technique supported, the amount of memory support (in megabits usually), the type of memory supported, and whether memory interleave, ECC (error-correcting code), or parity is supported. c) Interfaces This category defines the type of PCI interface implemented and whether the chipset is AGP-compliant, supports integrated graphics, PIPE (pipelining), or SBA (side band addressing). d) Arbitration This category defines the method used by the chipset to arbitrate between different bus speeds and interfaces. The two most common arbitration methods are MTT (Multi-Transaction Timer) and DIA (Dynamic Intelligent Arbiter). e) South bridge support All Intel chipsets and most of the chipsets for all other manufacturers are two processor sets. In these sets, the north bridge is the main chip and handles CPU and memory interfaces among other tasks, while the south bridge (or the second chip) handles such things as the USB and IDE interfaces, the RTC (real-time clock), and support for serial and parallel ports.
f) Power management All Intel chipsets support both the SMM (System Management Mode) and ACPI (Advanced Configuration and Power Interface) power management standards.
adapters. The IrDA port on your system is that small red window on the front or side of notebook and some desktop computers. h) Keyboard controller A chipset may include the keyboard controller, and many of the newer ones do. The keyboard controller is the interface between the keyboard and the processor. See the previous section for more information on this device. i) PS/2 mouse controller When IBM introduced the PS/2 system, the controller for the mouse was included in the keyboard controller. This design has persisted and usually wherever the keyboard controller is, so is the PS/2 mouse controller. j) This device provides the interface between the PS/2 mouse and the processor. k) Secondary (Level 2, or L2) cache controller Secondary (L2) cache is located on the motherboard, a daughterboard, or as on the Pentium Pro, in the processor package, and caches the primary memory (RAM), the hard disk, and the CD-ROM drives. The secondary cache controller controls the movement of data to and from the L2 cache and the processor. l) CMOS SRAM The PCs configuration settings are stored in what is called the CMOS memory. The chipset contains the controller used to access and modify this special SRAM area.
NEW DEVELOPMENTS
Intel now includes a bus architecture, called Intel Hub Architecture, to enhance the interface between the elements of the chipset. Before this, chipsets used the PCI bus as the interface between the north bridge (host, memory, and AGP) and the south bridge (PCI and IDE controllers). Because the south bridge was a PCI device and the PCI controller at the same time, some efficiency (and one PCI slot) was lost. Its latest chipset, the 850 series, is built on IHA technology. The hub architecture dedicates a high-speed data bus between redesigned north and south bridges, now designated as the Memory Controller Hub (MCH) and the I/O Controller Hub (ICH). The ICH is not a PCI device and a PCI slot is freed up. The dedicated link allows these two hubs to transfer data much faster, as much as 266MBps over 8 bits.
Acer Labs has recently announced its ALiMAGiK 1 chipset to support the AMD Slot A/Socket A processor family. A parallel chipset family, the AladdinPro 5, supports the Intel Slot 1/Socket 370 processor family. What is remarkable about these chipset families is that they are designed to handle DDR (Double Data Rate DRAM) and SDR (Single Data Rate) memory architectures on desktopand mobile platforms, both of which were not previously supported together. DDR has a relatively small market share at present, but many experts expect it to grow to about half of the motherboard market in the next five years. In fact, VIA has also committed to using only DDR in its emerging chipsets and its newest chipset, the Apollo KT266, provides support for DDR SDRAM. The Apollo KT266 also features a new architecture enhancement, similar to Intels IHA, which it calls V-Link Architecture. The V-Link architecture has replaced the PCI link that is used to connect the north and south bridges of many chipsets.