VALLURUPALLI NAGESWARA RAO VIGNANA JYOTHI

INSTITUTE OF ENGINEERING AND TECHNOLOGY

Vignana Jyothi Nagar, Pragathi Nagar, Nizampet (S.O), Hyderabad – 500 090, TS, India.

FORMAT FOR SUBMISSION OF PROPOSAL FOR

SEED FUNDING

1. Broad Subject : Communications

2. Area of Specialization : VLSI
3. Duration : 3 Years
4. Principal Investigator
i. Name : Dr.Pinninti Kishore
ii. Sex : Male
iii. Date of Birth : 16-06-1982
iv. Qualification :Ph.D
v. Designation :Assistant Professor
vi. Department : ECE
5. Teaching and Research Experience of Principal Investigator:
(a) Teaching experience: UG:13Years
PG:-
(b) Research experience:-
(c) Publication:
Papers Published (Enclose list along with number of present citations): 31

Books Published:01
(d) Research Projects (Enclose List if any):
Completed: 01
Ongoing:-
Applied:01
(e) Consultancy (Enclose List if any):
Completed:01
Ongoing:-
Applied:-
(f) Research Guidance :
Number of PhD Students: -

Number of PG & UG Students:

-
 Proposed Research Work

6 (i) Project Title: Design and Development of D-band Low Noise Amplifier for
Military and Surveillance applications
(ii) Introduction:
 Origin of the research problem:
In today’s world, development of Millimetre wave technology has been accelerated for security
check in recent decades due to its ability of imaging the non-metallic explosive or weapons under
the clothes of human being without intrusive detection.

Millimetre wave receivers as a class are an essential part of every Millimetre wave based
subsystem, particularly radiometers, radar, and radios. However, several applications use a highly
sensitive Millimetre wave receiver to achieve the ultimate primary function of the system.
As an illustration, principal examples of such applications are:

 Electronic Warfare (EW), Electronic Support Measure (ESM)

 Electronic Surveillance & Electronic Intelligence( ELINT)
 Direction Finding/Radar Threat Warning Systems
 Compliance measurement (Communication, Safety, Regulatory)
 Radio astronomy, Plasma Physics, Molecular Chemistry (Spectrometers)

However, the equivalent power of a received signal is too small to be discriminated from the
noise by the detector. Detection of this weak signal possess strict requirements on the sensitivity of
the receiver. So, the first block in the RF system which is a Low Noise Amplifier (LNA) plays a
crucial role to boost the received weak signal to above the intrinsic noise power. Thus, the entire
performance of the receiver is purely dependent on high performance LNA.

In military and surveillance applications, it is necessary to achieve better spatial resolution and
more compact scanners, increasing the frequency above 100 GHz is required. So, based on the
current research going on across the globe it is observed that most of the research is focused in D-
Band which is typically in the range of 110-150GHz.However, bandwidth of the system is chosen
based on the application. This project is primarily focusing on millimetric wave imaging for which
center frequency is chosen at 140GHz.

To meet this requirement, traditionally microwave and millimeter wave LNAs were designed in
advanced and more expensive elements of III-V technologies. There are two different approaches
being used for fabrication process of LNAs namely, MMIC (Monolithic Microwave Integrated
Circuit) and RFIC(Radio Frequency Integrated Chip). However, MMIC process technology is better
suitable for high power and high bandwidth applications.

RFIC design is based on CMOS and SiGe-BiCMOS technologies and, have the following
advantages over MMIC :

 Integrates much more functionality on a die

 Interface very well with digital blocks, smaller and more power efficient
 Allows System On Chip(SOC) solutions
 Implementing digital blocks
 Better gains and lower thermal issues
 Cost benefit of shifting as much of the transmitter & receiver as possible to a single
technology

Between CMOS and SiGe-BiCMOS technologies, the latter one is more suitable because it has
the advantages of low Noise Figure (NF) and better power delay product in comparison with CMOS
technology. Hence, In this project we have chosen SiGe-BiCMOS technology to design the LNA at
140GHz frequency.
Keywords:
 Receiver, Low Noise Amplifier (LNA), MMIC (Monolithic Microwave Integrated Circuit),
RFIC(Radio Frequency Integrated Circuit), SiGe(Silicon Germanium),BiCMOS(Bipolar CMOS).

 Interdisciplinary relevance: -
 Review of Research and Development in the Subject:
International Status:

Rainer Weber et.al [2017] have presented the development of a wideband low noise amplifier MMIC in the
D-band with a smart combination of coplanar transmission lines and active devices to minimize noise figure.
The identical three-stage LNA has been realized in metamorphic HEMT technologies with 100 nm and 50
nm gate length. The 50nm LNA MMIC achieves a linear gain of 30.8 dB together with a bandwidth of 67
GHz up to 164 GHz and a noise figure of 3 dB. It is also observed from the results that the performance of
100 nm LNA is slightly worse.
Çagri Ulusoy et.al[2015] have proposed a D-band low-noise amplifier with gain boosting was implemented
in a 130nm SiGe BiCMOS technology, occupying 0.4mm of IC area. The circuit consists of two stages of
cascode amplifiers with inductive common base termination, which improves the gain by increasing the
output impedance. The measurements show more than 20 dB gain from 110 to 140 GHz, consuming 12mW
of total dc power from a single voltage supply of 2.0 V. The measured noise figure is within 5.5 to 6.5 dB
in the same frequency range.
Patricia V. Larkoski et.al[2013] have reported the S-parameter and noise measurements
for three different InP 35nm gate-length High Electron Mobility Transistor (HEMT) Low Noise Amplifier
(LNA) designs operating in the frequency range centered on 140 GHz. It was observed from the results that
when packaged in a WR-6.1 waveguide housing, the LNAs have an average measured Noise Figure(NF)
of 3.0 dB – 3.6 dB over the 122 – 170 GHz band. One LNA was cooled to 20 K and a record low noise
temperature of 46 K, or 0.64 dB noise figure, was measured at 152 GHz. These amplifiers can be used to
develop receivers for instruments that operate in the 130 – 170 GHz atmospheric window, which is an
important frequency band for ground-based astronomy and millimeter-wave imaging applications.
Alex Bessemoulin et.al[2014], presented the performance of a first pass design W-band low noise amplifier
MMIC, based on coplanar waveguide (CPW) technology, and utilizing 100nm gate-length GaAs pseudo
orphic power HEMTs. With a chip size of less than 1.4 mm2, this two-stage LNA achieves an average small
signal gain of 12dB between 80 and 100GHz. The measured noise figure averages 5dB up to 94GHz. To the
author’s knowledge, this performance is one of the very few reported for W -band LNAs fabricated in
commercially available foundry process. It is also comparable to the best results reported with more
advanced InP or Metamorphic HEMT low noise technologies.
Wang Yawei1 et.al[2013], introduced the design of a four-stage W-band broadband Low Noise Amplifier
(LNA) using Monolithic Microwave Integrated Circuit (MMIC). The LNA uses CPW as the input and output
port and has a low noise figure using GaAs MHEMT technology. In order to reduce the chip size and circuit’s
complexity, single bias voltage supply is used in this design. The LNA has attained gain more than 19dB
over the frequency range 90 ~ 113GHz and the noise figure lower than 3.2dB.
There is a significant focus in evaluating good image quality for developing millimeter-wave cameras to
detect concealed weapons under clothing. Recently, U.S. military has shown their interest in imaging
through fog or dust, enabling “all-weather” vision. Thus in international level, the major challenge lies in
the availability of a low-cost imaging sensor with sufficient sensitivity is very critical to the successful
deployment of this millimeter wave technology. Not only in millimeter wave imaging, but also for secured
data communication is becoming a viable method for viewing objects that are otherwise obscured. It is
observed few attempts in evaluating and proposing architecture for highly sensitive LNA design, many of
these are in very early stages of development. There are various issues to consider like.
 Noise performance
 Stability
 Power consumption
 Impedance matching
 Bandwidth
It is thus suggested that further proposed architectures for the LNA design should take into account to
overcome these challenging issues and also factor security and privacy aspects in defining the right topology
to address the various problems.
National Status:
V. P. Bhale et al.[2014] proposed a design and optimization of 3GHz single ended Radio Frequency
LNA for wireless applications using 0.18µm CMOS technology. The designed Low Noise Amplifier
achieved a power gain of 14.49 dB and a minimum Noise Figure of 1.897 dB is achieved. It dissipates 11.7
mW of power out of 1.8 V supply. This work shows that the optimization of RF Circuits is possible with
real coded genetic algorithm. It is found that real coded Multi-Objective Genetic Algorithm has many
advantages over binary coded genetic algorithm.

Ravinder Kumar et.al[2012] have proposed a single stage LNA design with high gain and low noise
using inductive source degeneration topology for frequency range of 3 GHz to 7 GHz and also use the active
biasing devices. A range of devices like inductors and capacitors are used to achieve 50 Ω input impedance
with a low noise factor. The design process is simulated process is using Advance Design System (ADS)
and implemented in TSMC 0.18 µm CMOS technology. A single stage low noise amplifier has a measured
forward gain 25.4 dB and noise figure 2.2 dB at frequency 5.0 GHz.

V. Vaithianathan et.al[2012] have done the work on design of low power, high gain, low noise amplifier
with improved noise figure and input matching for ultra wide band applications. In this work, two low noise
amplifiers (LNAs), one without feedback and another one with active shunt partial feedback, were proposed
for ultra wide band (UWB) applications. Both the proposed LNAs were designed using 90 nm CMOS
technology and their performance parameters are analyzed by using post layout simulation. The proposed
LNA without feedback achieves a power gain (S21) of 16.4 dB over the band of 3 – 10.4 GHz with NF
(Noise Figure) in the range of 4.9 – 5.2 dB. This high NF has been reduced to 2.4 – 2.7dB by employing
active shunt partial feedback. The proposed LNA with active shunt partial feedback achieves a power gain
of 15 dB over the band of 2 – 12 GHz. The input matching (S11) and output matching (S22) are less than
10 dB while maintaining the reverse isolation (S12) is less than -60 dB for both of the proposed circuits.
Both circuits, with and without active shunt partial feedback, maintain better linearity with in-band third
order input intercept point (IIP3) of -1 dBm and – 4.242dBm, respectively and consume 3.643 mW and
2.862 mW of power while operating at 1 V power supply.
In India the security sector is facing tremendous pressure in offering cost effective remote security
services. In order to solve these problems technology must be leveraged with effective deployments to offer
secure data. So, this project aim to find a feasible solution with respect to cost and size by using the SiGe
technology.

 Significance of the study

Its potential contribution to knowledge in the field of social relevance or national
importance.

 It was observed that the present research in India being at very early stage in D- Band. It could
be because of development over head and lack of skilled man power. So we, as an academic
institute, with research orientation see an unique advantage in taking up this challenging task.
 Till now, most of the receiver systems built not beyond 60 GHz (5G Communication) frequency.
The project aimed to design a LNA at 140GHz frequency, this being very new frequency band
in India left unexplored. So, the proposed project itself is unique with respect to frequency.
 It is observed that in abroad lot of research is going on this frequency band, but less number of
research groups in India have started to carryout research in this area. This itself speaks about
the team is also unique working in such high frequency.
 The design will have less power dissipation in compared with other designs.
 As the wave length is very low, So the size of system is very small.
 Higher bandwidths can be achieved without much of difficulty.
 For Military applications, size of the system is very important. RFIC gives very small form
factor to the system.
 As an extension to this, there is a future scope to build system around the silicon on the same
technology.

(iii) Objectives:
 To design and develop a Low Noise Amplifier which is the most critical part of any receiver
system
 To avoid the risk factors in increasing the frequency of operation of LNA.
 The proposed design is to be done at 140GHz frequency and entire unit shall be very small
compared to similar components at other frequencies.
 To avoid the risk factor comes in routing or inter connection of components within the module.
 The proposed design shall be a big challenge as very few devices or components are modeled at
D-band frequency.

(iv) Methodology
Fig.1 shows the flow of the proposed project plan.
The major steps in this work plan are
 Defining the specifications of the proposed LNA design
 Preparation schematic for the defined target specifications which includes choice of
layers and circuit design with necessary parameters.
 Simulation is to be done to verify functionality of the design and so as to generate the
netlsit of the design.
 Layout of simulated design and parasitic extraction is carried out
  Electro Magnetic Co-Simulation is performed to estimate the cross talk between the
multiple layers in the layout and emulate the interference in real time. This is very
crucial for calculating the performance of a system under real time environment.
 Finally, Graphic Database System (GDS) file will be created and can be used for IC
fabrication.

Fig 1. Flow chart of work plan

 Specifications:
The proposed methodology will be evaluated for the design of a LNA with the following design
specifications.

Sl. No Parameter Target Specification

1 Operating frequency 140GHz
2 Noise Figure 15dB
3 Input Return loss (S11) <-10 dB
4 Power Gain (S21) 10 to 11 dB
5 Output return loss (S22) <-10 dB

 Choice of devices:

This proposal initially starts with selecting the best device/transistor to define the amplifier
topology which best suits the design requirements. As this is a high frequency design, the
parameters found in the device data sheet typically are:
 Scattering(S),
 MAG (Maximum Available Gain),
 Rollet factor (k).
These parameters allow a first feasibility analysis of the design with a specific transistor.

 Bias circuit design:

After the transistor is selected and the bias operating point is to be chosen, the next step will be the
design of bias stage. The bias circuit design must be simultaneously ensure that a stable operating
point and a certain isolation of the RF stage. Current mirror technique will be used in determining
bias operating point.
 Evaluating stability zones and Maximum Available Gain:

The analysis of the transistor stability as well as Maximum Available Gain (MAG) will be carried
out in this part. If the conditions of stability of transistor will not satisfy, the stability conditions of
the transistor must be considered in the design of the matching networks, to avoid possible
oscillations.

 First evaluation of S-parameters, constant gain and noise circles:

This part begins with a selection process of the operating point according to the intersection
between the constant gain circles and the constant noise figure circles, with better S-parameters to
find out the points at which they are best satisfied with required specifications.

 Analysis of the VSWR circles for each of the points that meet the conditions of gain and noise:

The systematic analysis of the design requirements will be carried out in part, in terms of
impedance matching at the input and output of the amplifier.

 Design of optimum input and output matching network:

At this stage, the values of the reflection coefficients at the input and the output will be considered
to design LNA with their corresponding input and output matching couplers.

 Layout of LNA (Extraction of parasitic i.e., LVS, DRC)

The designed LNA architectures will be simulated to verify its functionality and later will be analyzed
using Layout and parasitic extractions.

 Electro Magnetic (EM) analysis of LNA :

EM simulation of LNA will be carried out for final LNA architecture design to verify all required
parametric analysis.

 Co simulation :

Upon EM simulation we perform co-simulation of schematic with the EM response (results). So,
this makes sure all real time affects are taken care.

 Cascading of stages :
Single stage LNA may not be able to supply the required amount of gain for which we may have to
add multiple stages. So, we cascade 2-3 stages in cascade maintaining proper matching between the
adjacent stages.

(v) Year-wise Plan of work and targets to be achieved.

T0+ T0+3
S.No T0+3 T0+6 T0+9 T0+12 T0+15 T0+18 T0+21 T0+24 T0+27 T0+30
33 6
Design
1
Methodology
2 Schematic Design
3 Layout Design
4 Co-simulation
5 GDS generation
(vi) Expected Outcome of the project:
Patents: NIL
Papers: 03
Funding from various agencies: Rs.50,00,000/-
Product / Incubation:-
Societal Impact: This Project can be used for military and Surveillance
applications
Consultancy:-
Collaboration with Industry: MMRFIC TECHNOLOGIES
Collaboration with other Institutes:
Student Projects (UG/PG):-02 PG Projects

7 Financial Assistance required

SNO Item Description Estimated Expenditure in

INR
1 Software 2,00,000/-
2 Equipment 60,000/-
3 Field Work and Travel 20,000/-
4 Research Assistant -
6 Paper Publications 20,000/-
7 Others
Total:Rs.3,00,000/-

8 Any Co-Investigator/s (If any, give the data of Co-PI/s in the format of 4 &5):-

Signature of Principal Investigator Signature of HOD