2017

Student Design
Competition
Winners
IMS 5G Mobile Communications
Receiver Module

Decreasing
Size, Increasing
Battery Life
Markus Heinrichs,
Niklas Bärk, and
Rainer Kronberger

W
ith t he i nt roduct ion of cloud-
based services, online social net-
works, and multimedia streaming
over the past decade or so, the de­­­
mand for high-bandwidth mobile
communications has increased rapidly. At the same
time, consumers expect long battery life for their hand-
held devices. Fifth-generation (5G) wireless broad-
band will provide bandwidth of multiple gigabits per
second, requiring wider bands at higher frequency
ranges than today’s communication systems use.
Cellular broadband, Wi-Fi, Bluetooth, and global
positioning systems are included in most modern hand-
helds. It is a challenge for manufacturers to fit all
these modules into the small space available. Con-
sequently, tradeoffs in the performance of wireless
Image licensed by Ingram Publishing

Markus Heinrichs (markus.heinrichs@th-koeln.de), Niklas Bärk (niklas.baerk@th-koeln.de),

and Rainer Kronberger (rainer.kronberger@th-koeln.de) are with the University of Applied Sciences, Cologne, Germany.

Digital Object Identifier 10.1109/MMM.2017.2779683

Date of publication: 7 February 2018

March/April 2018 1527-3342/18©2018IEEE 77

Sharing antennas and low- Technology’s Advanced Design System (ADS) to eva­­
luate the performance of different topologies and
noise amplifiers for multiple transistors. This saved significant time during the
communication standards is one development process, as it reduced the number of phys-
of the preferred ways to reduce the ical prototypes necessary.
The transistor models contained in an ADS library
physical space required and to provided by the manufacturer were used for this pur-
extend battery life. pose. All the passive components, including the inductors
and capacitors, were simulated using the S-parameters
provided by the manufacturers, as the influence of para-
communication devices must be accepted. Sharing sitics varies greatly over the wide frequency range. Addi-
antennas and low-noise amplifiers (LNAs) for multiple tionally, all transmission lines and vias were included in
communication standards is one of the preferred ways the simulations. During the simulations, it became clear
to reduce the physical space required and to extend that many of the best-practice methods and approaches
battery life. Although these various applications place from the literature could not be applied to the design
different demands on the amplifiers (for example, in because those refer to amplifiers with lower bandwidth.
terms of frequency and bandwidth), most require high While working on the design, it turned out to be more
linearity and low noise. promising to optimize toward a lower dc power con-
sumption rather than increasing the OIP3 to achieve a
IMS2017 LNA Student Design Competition good FOM [1].
The objective of “5G Mobile Communications Receiver
Module” Student Design Competition (SDC) held dur- LNA Circuit
ing the IEEE Microwave Theory and Techniques Soci- A single-stage approach with a bipolar transistor in a
ety (MTT-S) 2017 International Microwave Symposium grounded emitter circuit was selected as the amplifier
(IMS2017) and sponsored by MTT Technical Coordi- topology. A bipolar transistor was preferred over a field-
nating Committees 6, 14, 16, and 20 was to design a effect transistor (FET) because good matching across the
broadband, high-linearity, low-power receiver module wide band of 4 GHz is essential. It is difficult to achieve
for multistandard use. The module was intended to this using an FET because of its high input impedance,
operate at frequencies between 2 and 6 GHz. which must be transformed to match 50 Ω over the whole
Entries for the competition were required to ful- bandwidth [2]. From the bipolar transistors available, the
fill specific minimum requirements. The noise figure Infineon BFP840ESD, a silicon-germanium-carbon tran-
had to be below 1.5 dB with a minimum gain of 13 dB, sistor with a transition frequency of 80 GHz, was chosen
as well as a 1-dB compression point of at least 0 dBm, [3]. This device offers sufficient gain and a good noise fig-
across the full frequency range. The guidelines speci- ure over the full range between 2 and 6 GHz.
fied that the circuit operate from a single adjustable dc Fulfilling the gain requirement of 13 dB at 6 GHz
supply, providing a maximum voltage of 5 V. can be challenging when using a single-stage design. In
At the start of the IMS2017 competition, two fre- addition, the OIP3 of 21 dBm at 2 GHz is high enough
quencies between 2 and 6 GHz were selected by roll- to perform well in the competition, and, according to
ing a six-sided die: 5 and 6 GHz were selected. At these the data sheet, the transistor offers a 1-dB compression
frequencies, the performance of the amplifier was inves- point of 4 dBm. The grounded emitter topology pro-
tigated in detail. vides high gain [4], which was one key requirement to
Judging of the competition was based on a figure of enter the competition. The single-stage design supports
merit (FOM) defined by the third-order output inter- the demand for low power consumption while avoid-
cept point (OIP3) and the dc power. The noise figure ing the need for interstage matching, which would be
was set to 1.5 dB for all competitors, fulfilling the mini- difficult to optimize over the broad frequency range of
mum requirements 4 GHz (Figure 1).
The circuit was built on a Rogers RO4003C sub-
OIP3 low [mW]
FOM low = , strate with a thickness of 0.508 mm and 17-µm copper
Pdclow [mW] · NF [dB]
cladding. Matching the circuit was difficult due to the
OIP3 high [mW] wide frequency range, and ideal matching could not be
FOM high = ,
Pdchigh [mW] · NF [dB] achieved for all frequencies. Using transmission lines
FOM low + FOM high and a small coupling capacitor of 2.2 pF at the input,
FOM = .
2 the input impedance was matched to the transistor’s
optimum noise impedance as best as possible over the
Design Process and Simulations wide frequency range. The matching at the output was
During the development of the circuit, a significant num- improved by using another series-coupling capacitor
ber of simulations were performed using Keysight of 10 pF.

78 March/April 2018
 V_BE

100 nF 100 nF

4.7 kΩ V_CE
100 pF
100 nF 100 nF

6 nH
100 pF 100 pF

27 nH

27 nH RF-OUT
BFP840ESD

W = 1 mm 10 pF W = 1.15 mm
L = 2.1 mm L = 31.63 mm
RF-IN 2.2 pF W = 0.5 mm
W = 1.15 mm
L = 5.7 mm L = 1 mm

Figure 1. The RF circuit of the single-stage LNA in grounded-emitter topology.

The bias voltages were applied through inductors

at the base and the collector of the transistor. The use
of transmisson lines for RF decoupling, e.g., a m/4
impedance transformer, was not possible due to the
wide frequency range of the amplifier. To achieve good
RF decoupling over a wide bandwidth, two different RF Circuit
inductors with different self-resonant frequencies
were used in the base biasing network. In addition, a
series resistor of 4.7 kΩ was added to improve the
LNA’s stability. Bias Circuit
The input voltage was filtered by a ferrite bead and
several capacitors of different values to achieve good
decoupling. The VBE and VCE were regulated by two
ADP171 low-noise linear voltage regulators from Ana-
Figure 2. The wide-band LNA module for 5G and
log Devices and could be adjusted by two trimming
multistandard use with frequencies of 2–6 GHz.
potentiometers. The VCE was regulated to compensate
for cable losses and power supply inaccuracies. As low
dc power consumption is important for a good FOM, filters, which provided additional decoupling. The
the voltage dropout across the regulator had to be kept PCBs were produced in the faculty workshop as well,
to a minimum. As the ADP171 offers low dropout volt- using a laser cutter that allowed for fast production of
age, operates at low input voltages, and has very low the prototypes.
output noise, it was chosen for the LNA design.
The amplifier was placed in a custom aluminium Tuning
housing (Figure 2), specifically designed for this con- Making adjustments solely to the bias point did not
test and manufactured in the University of Applied lead to the desired adaptation to the simulation. To
Sciences, Cologne, faculty workshop. This case pro- improve the circuit’s performance, the other compo-
vides shielding and allows the RF printed circuit nents had to be tuned.
board (PCB) to be isolated from the bias circuit, which First, the capacitor at the input was altered, lead-
reduces the influence of outside noise. RF absorbers ing to the conclusion that a reduced value offers bet-
were placed at the top and bottom of the housing to ter matching, thus improving gain on the one hand
avoid wave propagation inside the LNA housing. Con- and noise figure on the other. The influence of the two
nections between the two PCBs were made using EMI inductors on the base bias was then examined in detail.

March/April 2018 79
While working on the design, it compression point with the integrated 1-dB compres-
sion point trace function. The minimum 1-dB compres-
turned out to be more promising to sion point measured was 3.2 dBm at 2 GHz (Figure 3).
optimize toward a lower dc power For the measurement of the OIP3, which was one
consumption rather than increasing of the main evaluation criteria, two signal generators
were combined to generate a signal with two tones:
the OIP3 to achieve a good FOM. one 10 MHz above and the other 10 MHz below the
center frequency being studied. The generators were
Some combination of values of inductors appeared to precisely adjusted to output a –20-dBm carrier, which
form resonant circuits, directly resulting in amplifier is essential to obtain accurate results. The amplifier
instability. Consequently, the inductor’s values had to prototype output signal was measured with the test
be tuned to avoid resonances. At the same time, care signal applied to the input. The resulting OIP3 varied
was taken so that the changes did not degrade the per- between 20.0 and 32.3 dBm, depending on the fre-
formance of the matching circuit. Although making quency (Figure 4). At the selected frequencies (5 and
adjustments to the components on the output had little 6 GHz), the achieved OIP3 was 32.3 and 28.8 dBm,
influence on the performance, the series capacitor at while consuming a dc power of 17.6 mW. This results
the output was tuned for minor improvements regard- in an overall FOM of 46.7.
ing matching. When comparing the LNA design to commercial
While tuning the circuit components, the noise fig- amplifier modules, it was difficult to find modules
ure was constantly monitored to avoid any degrada- fulfilling all minimum requirements for entering the
tion of noise matching. As the FOM was defined by competition, such as the Macom MAAL-011078 and
dc power consumption and the OIP3, both of which the Qorvo QPL9503 do. At the frequencies selected
depend on the bias point of the transistor, the opti- for the contest, the FOM for the MAAL-011078 is 3.6,
mization of the FOM was achieved almost entirely by and the QPL9503 achieves an FOM of 6.9. However,
tuning the dc bias voltages. one should remember that these devices are not spe-
cifically optimized to meet the requirements of the
Amplifier Measurements contest. Both have a higher OIP3 and gain than the
The measurements were carried out with the test and design we present here, but they also have a signifi-
measurement equipment available in the RF lab at the cantly higher dc power consumption, with 150 mW for
University of Applied Sciences, Cologne. The gain of the MAAL-011078 and 325 mW for the QPL9503 [5], [6].
the amplifier was measured using a vector network
analyzer (VNA). This gain decreases toward higher Transistor Measurements
frequencies and has its minimum value of 14.2 dB at The prototype of the LNA showed some significant
6 GHz, therefore achieving the required gain of 13 dB. differences compared to the simulations. To improve
The noise figure was evaluated with a spectrum ana- future simulations, the causes for the deviations were
lyzer having a calibrated noise source using the examined in detail. The 1-dB compression point is
Y-factor method. The measured values for the noise one of the parameters that differed the most from the
figure ranged from 1.20 dB at 2 GHz to the maximum of simulation results. As the 1-dB compression point is
1.37 dB at 5.7 GHz (Figure 3). mainly influenced by the active component, our inves-
The 1-dB compression point was measured with a tigation focused on the transistor. To verify the tran-
VNA using a power sweep and by determining the sistor model used for the simulation, measurements

8 40
7 NF 35
NF (dB)/P1 dB (dBm)

6 P1 dB
30
OIP3 (dBm)

5 25
4 20
3 15
2 10
OIP3 High
1 5 OIP3 Low
0 0
2 3 4 5 6 2 3 4 5 6
f (GHz) f (GHz)

Figure 3. The noise figure (NF) and 1-dB compression Figure 4. The OIP3 at –20-dBm input power and with
point ^P1 dB h . 20-MHz tone spacing.

80 March/April 2018
of the S-parameters and the 1-dB compression point of The single-stage design supports the
the BFP840ESD were conducted [7]. For this purpose,
a transmission-reflection-line (TRL) calibration kit demand for low power consumption
was manufactured on the same substrate used for the while avoiding the need for interstage
amplifier (Figure 5). matching, which would be difficult
The minimum and maximum frequency at which a
line can be used for calibration purposes is limited by to optimize over the broad frequency
the wavelength on the substrate. Lines shorter than 20° range of 4 GHz.
or greater than 160° can cause singularities during cali-
bration, which would lead to incorrect and unusable
results [8]. To avoid this problem, multiple lines of dif- simulations performed earlier. The deviation of the
ferent length were manufactured. For the transistor test S 21, for example, was mostly below 1 dB (Figure 6).
fixture, the same footprint was used as in the amplifier
design. To reduce the influence of the pads, the dimen- Transistor Modeling
sions were kept as small as possible. The calibration kit After the measurements, the mismatches between the
was designed in such a way that the calibrated refer- manufacturer’s model and the measured transistors,
ence plane was exactly at the transistor’s pads. as well as their causes, were examined. The most sig-
To ensure reasonable confidence in the validity of the nificant differences were found with S 21, which was
measurement results, five samples of the BFP840ESD about 2-dB lower than the manufacturer stated, with
were measured. Two different measurements at differ- the 1-dB compression point being 6-dB higher, as the
ent bias points were taken, one at the bias point used in data sheet specifies. One possible reason for this could
the competition (VCE = 1.8 V, IC = 9.4 mA) and the other be a different emitter negative feedback caused by the
at VCE = 1.8 V and IC = 10 mA, as the S-parameters and ground connection of the emitter on the test board
P1 dB at this bias point are well documented in the tran- being more inductive than that in the manufacturer’s
sistor’s data sheet and could be used for later compari- transistor model. This assumption was verified using
sons. The transistor was biased using the integrated another ADS simulation.
bias networks of the VNA. An equivalent circuit model was developed, which
The five measured samples of the BFP840 were was optimized to adapt the measured transistor param-
very similar to each other in terms of 1-dB compres- eters to the manufacturer’s model. In this way, the
sion point as well as S-parameters. The measurement influence of different parasitics could be shown, and
results were then included in the ADS simulation of equivalent component values determined.
the amplifier instead of the manufacturer’s model. The Capacitors between the transistor’s pins represent
results were much closer to the real amplifier than the the coupling between the legs, as capacitors to ground

25

20
|S21| (dB)

15

10
2 3 4 5 6
f (GHz)

S21 Measured
S21 Simulated with Manufacturer’s Model
S21 Simulated with Measured
Transistor Parameters

Figure 6. A comparison of the small signal gain of

the measured LNA (red), the simulation using the
Figure 5. The TRL calibration kit and transistor test manufacturer’s transistor model (blue), and the simulation
fixture on Rogers RO4003C substrate. using measured transistor parameters (green).

March/April 2018 81
An inductor was added to each of the Conclusions
The amplifier developed for the IMS2017 SDC fulfills
pins, representing the lead inductance many of the requirements for multistandard use. Its
and the connection to ground, low power consumption makes it suitable for imple-
respectively. mentation in battery-powered devices. The physical
size of the amplifier is currently limited by the hous-
ing, but it could easily be decreased to fit into mobile
represent parasitic ground capacitance [9], [10]. In addi- devices. Apart from applications related to mobile
tion, an inductor was added to each of the pins, rep- broadband, it could also be used as a broadband
resenting the lead inductance and the connection to amplifier for general-purpose applications in the lab,
ground, respectively (Figure 7). as it offers a good noise figure and linearity over a
Using the optimization feature of ADS, the compo- wide frequency range.
nent’s values were tuned to reduce the differences in Investigation of the differences between the transis-
the S-parameter DS between the measured transistor tor models and the actual circuit led to the realization
model and the model provided by the manufacturer: that the manufacturer’s transistor models are very use-
ful for getting a general overview of the circuit’s perfor-
DS = / |S ij, datasheet - S ij, measured| . mance, but they cannot be true for all possible designs
i, j and substrates. If very accurate results are required or
if the performance requirements of the developed
The inductance between the emitter and ground was circuit are very high, it is useful to determine the tran-
calculated to be 89-pH higher in the measured model. sistor’s S-parameters using a test fixture built on the
For this application, the difference has a significant same substrate as the planned design.
influence on the circuit’s behavior.
At the base and collector, similar inductor values Acknowledgments
were calculated; however, their influence on the cir- We thank the organizers, SDC chairs, sponsoring IEEE
cuit’s performance is not as significant as at the emit- committees, and all the other people who allowed us to
ter. The reference plane for the measurement was take part in this competition. The competition and the
calibrated to be at the transistor’s pads, so the parasitic exchange with other students at IMS2017 were a great
inductance should be very low. pleasure for us. In addition, we thank Aaron Finken-
Consequently, a reason had to be determined for thei and his team from the workshop for supplying us
these differences. Engineers from Infineon offered with fast PCB prototypes and the housing, as well as
their help in analyzing the differences and showing assisting in all mechanical work. Finally, we thank the
how they arose. The solution turned out to be rather engineers at Infineon for their immediate and exten-
simple: at Infineon, the transistors are measured in sive information regarding the transistor models.
a different test fixture under different conditions.
The transistor’s emitters are directly pinched onto References
a massive brass block, which has a different ground [1] C. Stedler, M. Kuntšev, and R. Kronberger, “Broadband, rugged,
high-linearity low-noise amplifier module,” IEEE Microwave Mag.,
inductance than the microstrip test board, as pads
vol. 15, no. 1, pp. 80–85, Feb. 2014.
and vias do not need to be taken in account. For [2] M. Kuntšev, “Development and optimization of a noise parameter
this specific application, the measurement using a test bench for amplifier components with high input impedance,”
microstrip test set is closer to reality because consid- M.S. thesis, RF Lab, Cologne Univ. Applied Sciences, Germany,
2013.
ering the influence of the PCB is crucial for obtain- [3] “Robust low noise silicon germanium bipolar RF transistor,” Infi-
ing realistic results. neon Technologies, Germany, BFP840ESD, 2013.
[4] I. Bahl, Fundamentals of RF and Microwave Transistor Amplifiers. New
York: Wiley, 2009.
[5] “Low noise amplifier 700 MHz–6 GHz,” rev. v3, M/A-COM Tech-
nology Solutions, Lowell, MA, MAAL-011078.
[6] “Ultra low-noise, flat gain LNA,” Qorvo, Greensbro, NC, QPL9503,
2017.
[7] “Measure 3 types of parameter and you will define a small signal
RF-transistor: S-parameters, noise figure and intermodulation,”
Infineon, Germany, Application Note No. 008, 2006.
[8] M. Hiebel, Fundamentals of Vector Network Analysis, 5th ed. Germa-
ny: Rohde & Schwarz, 2007, pp. 97–98.
[9] G. Snawadzki, A. Lewandowski, G. Avolio, and D. Schreurs,
“1.3 GHz power amplifier design using a measurement-based
transistor package mode,” in Proc. 20th Int. Conf. Microwaves Radar
and Wireless Communications, Poland, 2014.
[10] “Parasitic capacitance in bipolar junction transistors,” Infineon,
Figure 7. Transistor equivalent circuit model including
Germany, Application Note No. 024, 2006. 
parasitics for S-parameter correction.

82 March/April 2018