Unit 5

DSD with Verilog HDL
Unit V
References:
1. 1.Stephen Brown, ZvonkoVranesic, “Fundamentals of
Digital Logic with
Verilog Design,” 3/e, Tata McGraw Hill, 2008.
2. Michael John Sebastian Smith, Application Specific Integrated
Circuits, 3/e, Pearson Education Asia, 2001.
3. 3.Digital logic circuit analysis and design by Vector & Nelson
Syllabus
□ Introduction to ASIC’s: Full-
custom,standard-
cell and Gate array based ASICs.
□ SPLDs: PROM, PAL, GAL, PLA.
FPGA and CPLD simplified
architecture and applications.
□ ASIC/FPGA Design flow, CAD
tools. Combinational circuit Design
with Programmable logic
Devices (PLDs).
Introduction to ASIC
□ An ASIC (“a-sick”) is an application-specific
integrated circuit
□ A silicon chip or integrated circuit (IC) is
called a die
□ A gate equivalent is a NAND gate F = (AB)’
or four transistors
□ Flip flop contains 4 two input NAND gate
□ A 100 k gate IC contains 100,000 two
input NAND gate
□ (a) a pin grid array(PGA) package
□ made from ceramic or plastic
material
□ (b) The silicon die size varies few mm
to 1 inch
History of integration
□ SSI, ~10 gates per chip (60’s)- gates
□ MSI, ~100–1000 gates per chip
(70’s)- mux or decoder or comparator
□ LSI,~1000–10,000 gates per
chip(80’s)
□ VLSI, ~10,000–100,000 gates per
chip(90’s)
□ Ultralarge scale integration (ULSI,
~1M–10M gates per chip
History of technology
□ Bipolar technology
□ Transistor–transistor logic (TTL)
□ metal-oxide-silicon (MOS) technology
because it was difﬁcult to make
metal-gate n-channel MOS
□ complementary MOS (CMOS) greatly
reduced power
□ Example : TSMC CMOS 180nm
Technology
Types of ASICs
Full-Custom ASICs: Possibly all logic cells and all mask layers
customized
Semi-Custom ASICs: all logic cells AND gate OR gate MUX or FF
are pre-designed and some (possibly all) mask layers customized
□ ICs are made on a wafer. Circuits are
built up with successive mask layers.
The number of masks used to deﬁne
the interconnect.
□ First half-dozen or so layers define
transistors and other half-dozen or so
define Interconnect
Types of ASICs – Cont’d
❑Full-Custom ASICs
❖ Include some (possibly all) customized logic cells
❖ Have all their mask layers customized
❖ Full-custom ASIC design makes sense only
✔ When no suitable existing libraries exist or
✔ Existing library cells are not fast enough or
✔ The available pre-designed/pre-tested cells consume too much
power that a design can not allow
✔ The available logic cells are not compact enough to fit
✔ ASIC technology is new or/and so special that no cell library
exits.
❖ Offer highest performance and lowest cost (smallest die
size) but at the expense of increased design time,
complexity, higher design cost and higher risk.
❖ Some Examples: Microprocessor, High-Voltage Automobile
Control Chips, Analog to Digital Communication Chips and Sensors
❑ Semi-Custom ASICs
❖ Standard-Cell based
ASICs (CBIC-
“sea-bick”)
✔ Use logic blocks from
standard cell libraries,
other mega-cells,
full-custom blocks,
system-level
macros(SLMs),
functional standard
blocks (FSBs), cores etc.
✔ Get all mask layers
customized- transistors
and interconnect
✔ Manufacturing lead time
is around 8 weeks
✔ Less efficient in size and
performance but lower in
design cost
❑ Semi-Custom ASICs –
Cont’d
❖ Standard-Cell based
ASICs (CBIC-
“sea-bick”) – Cont’d
Cont’d
❖ Gate Array based
ASICs
12
❑ Semi-Custom ASICs – Cont’d
❖ Gate Array based ASICs -
Cont’d
UNIT 5 13
Cont’d
❖ Programmable ASICs
✔ PLDs - PLDs are low-density
devices which contain 1k – 10 k
gates and are available both in
bipolar and CMOS technologies
[PLA, PAL or GAL]
✔ CPLDs or FPLDs or
FPGAs - FPGAs combine
architecture of gate arrays with
programmability of PLDs.
✔User Configurable
✔ Contain Regular Structures
- circuit elements such as
AND, OR, NAND/NOR gates,
FFs, Mux, RAMs,
✔Allow Different
Programming
Technologies
✔ Allow both Matrix and
Row-based Architectures
PLDs
□ No customized mask layers or logic cells
□ Fast design turnaround
□ A single large block of programmable
interconnect
□ A matrix of logic macrocells that usually consist
of programmable array logic followed by a
flip-flop or latch
Types of PLDs
□ Simple PLD
□ Complex PLDS
Simple PLD
□ OR gates can produce an output that is a
function of the two input variables, A and B.
□ Each output function is programmed with
the fuses located between the AND gates
and each of the OR gates.
Simplified PLD
□ Outputs are programmed as
Types - Simple PLDs
□ PROM(Programmable ROM)
□ PAL (Programmable Array Logic)
□ PLA (Programmable Logic Array)
□ GAL (Generic Array Logic)
Basic configuration
Example – Full adder
□ S=m(1,2,4,7)
□ C=m(3,5,6,7)
PROM Realization of FA
Example 2- Binary to Gray code
Code converter realization
PROM – Example 3
Realize BCD to Excess 3 code
converter
□ Using PLA
□ Truth Table relating BCD and Excess-3 codes
□ Boolean expression for □ K-Map solution
each Excess-3 code bits
PLA Realization
PLA Programming table
Logic equations
□ E3 =
□ E2=
□ E1=
□ E0=
PLA Example
PLA Programming Table
Comparison PROM and PLA
PROM PLA
AND array fixed and OR array AND and OR array are
programmable programmable
All minters are decoded AND array can be programmed

to get desired midterms
Only Boolean function in Any Boolean function in SOP
standard SOP can be form can be implemented
implemented
Programmable Array Logic
□ In a PLA both the AND and OR planes are
programmable.
□ the programmable switches presented two
difficulties for manufacturers of these devices:
they were hard to fabricate correctly, and they
reduced the speed-performance of circuits
implemented in the PLAs.
□ Drawbacks led to the development of a similar
device in which the AND plane is
programmable, but the OR plane is fixed. Such
a chip is known as a programmable array logic
(PAL) device.
□ are simpler to manufacture, and thus less
expensive than PLAs, and offer better
performance, PALs have become popular in
practical applications.
Standard PAL
Example 1
□ Realize functions using PAL
f1 = x1x2x3` +x1`x2x3
f2 = x1`x2 `+x1x2x3
Example
PAL Realization of Functions
Limitations
□ Limited number of switching functions
can realize
□ Selection of device to particular
applications, single product term can not
be shared between two sum terms
□ If two sum contain a common product
term that product must be generate
twice
□ More cost effective than PROM and PLA
Comparison PLA and PAL
PLA PAL
AND and OR array are AND array programmable and
programmable OR array is fixed
AND array can be programmed AND array can be programmed

to get desired midterms to get desired midterms
Any Boolean function in SOP Limited number of switching

form can be implemented functions can realize
Less cost effective More cost effective
Selection of device to particular

applications (fixed type)
Generic Array Logic (GAL)
□ Generic array logic family consists of
electrically erasable programmable devices
□ Same logic properties as PAL but can be erased
and reprogrammed.
□ Programmed and reprogrammed using a PAL
programmer.
□ GAL has a programmable And array and a fixed
OR array. The reprogrammable array is
essentially a grid of conductors forming rows
and columns with an electrically erasable CMOS
(E2CMOS) cell at each cross point.
GAL Architecture
□ The GAL has the programmable logic and the
OLMC (Output Logic Macro cell) Logic that
excludes OR gates and flip-flops.
Complex PLD
□ For implementation of circuits that require more
inputs and outputs, either multiple PLAs or PALs
can be employed or else a more sophisticated type
of chip, called a complex programmable logic
device (CPLD).
□ A CPLD comprises multiple circuit blocks on a
single chip, with internal wiring resources to
connect the circuit blocks. Each circuit block is
similar to a PLA or a PAL.
Architecture of CPLD
Field Programmable gate array
□ All FPGA contain regular structure of
programmable basic logic cells surrounded by
programmable interconnects .
□ FPGAs used to implement logic circuits of more
than a few hundred thousand equivalent gates
in size.
□ Two examples of FPGAs, called the Altera FLEX
10K and the Xilinx XC4000
Architecture of FPGA
FPGA - Characteristics
□ None of the mask layers are customized
□ A method for programming the basic logic cells
and the interconnect
□ The core is a regular array of programmable
basic logic cells that can implement
combinational as well as sequential logic
(flip-flops)
□ A matrix of programmable interconnect
surrounds the basic logic cells
□ Programmable I/O cells surround the core
□ Design turnaround is a few hours
LUT(lookup table)
□ The most commonly used logic block is a
lookup table (LUT),which contains storage cells
that are used to implement a small logic
function.
□ Each cell is capable of holding a single logic
value, either 0 or 1. The stored value is
produced as the output of the storage cell
Structure of LUT
□ Two input LUT
Three input LUT
Applications
□ Consumer products like DVD players and
high-end televisions sets
□ Control circuits for automobiles factories and
test equipment
□ High speed network switches and computer
equipment like large tape and disk storage
systems
□ Internet routers
ASIC Design Flow
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DSD with Verilog HDL

All minters are decoded AND array can be programmed

AND array can be programmed AND array can be programmed

Any Boolean function in SOP Limited number of switching

Less cost effective More cost effective

Selection of device to particular

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