Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd
Upload
69 views

Ece2008 Vlsi System Design Syllabus

This document outlines an ECE course on VLSI system design. The course has 5 modules that cover MOS transistor fabrication and characteristics, VLSI circuit design processes, gate-level design, subsystem design, and memory and testing. The objectives are to learn MOS transistor concepts, digital logic layout, and subsystem design concepts. Students will design CMOS logic circuits and memory concepts. The course includes 12 hours on MOS technology and design rules, 9 hours each on design processes and gate-level design, and 7 hours on memories and testing. Students will be evaluated based on 3 CAT exams and a 40% lab component.

Uploaded by

yaswanth r
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
69 views

Ece2008 Vlsi System Design Syllabus

This document outlines an ECE course on VLSI system design. The course has 5 modules that cover MOS transistor fabrication and characteristics, VLSI circuit design processes, gate-level design, subsystem design, and memory and testing. The objectives are to learn MOS transistor concepts, digital logic layout, and subsystem design concepts. Students will design CMOS logic circuits and memory concepts. The course includes 12 hours on MOS technology and design rules, 9 hours each on design processes and gate-level design, and 7 hours on memories and testing. Students will be evaluated based on 3 CAT exams and a 40% lab component.

Uploaded by

yaswanth r
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

ECE2008 VLSI System Design TPC 3 2 4

Version 1.0
Course Pre- ECE1003
requisites
1. To learn the various fabrications and characteristics of MOS
transistor.
Objectives: 2. To learn the various concepts required to obtain the digital logic
layout diagrams.
3. To learn various subsystem design concepts and memory elements.
Expected 1. Design CMOS based logic circuits.
Outcome: 2. Design concepts of memories.
Module No. 1 Introduction 12 Hours
Introduction to MOS Technology, Basic MOS Transistor action: Enhancement and Depletion
Modes. Basic electrical properties of MOS. Threshold voltage and Body Effect. MOS and
CMOS circuit Design Process: MOS Layers, Stick diagrams, Lambda based Design rules and
Layout diagrams.

Module No. 2 VLSI Circuit Design Processes 9 Hours


VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, CMOS Design
rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and
Gates, Scaling of MOS circuits.

Module No. 3 VLSI Gate Level Design 8 Hours


Design of MOS inverters with different loads. Basic Logic Gates with CMOS: INVERTER,
NAND, NOR, AOI and OAI gates. Pass transistor, Transmission gate logic circuits, BiCMOS
inverter, D flip flop using Transmission gates.

Module No. 4 VLSI Subsystem Design 9 Hours

Multiplexer, Shifters, Adders, Multipliers, Parity generators, Comparators, Programmable Logic


Arrays.

Module No. 5 Memories & Testing 7 Hours


Design of Dynamic Register Element, 3T, 1T Dynamic RAM Cell, 6T Static RAM Cell. NOR
and NAND based ROM Memory Design. Basic VLSI Testing: Defects, Fault Models, Scan,
Built-in-self Test (BIST).

Text Books
1. Kamran Eshraghian, Douglas A. Pucknell, Sholeh Eshraghian, “Essentials of VLSI
circuits and systems”, PHI, 2011.
References
1. John P. Uyemura, “Introduction to VLSI Circuits and systems”, John Wiley & Sons,
2011
2. W. Wolf, Modern VLSI Design - System on Chip design, 3/e, Pearson Education.
3. Neil H E Weste, David H
4. arris, Ayan Banerjee “CMOS VLSI Design –A circuit and System Perspective”, 3/e,
Pearson Education, 2006
5.
List of Experiments

1. Different layers of MOS and CMOS inverter layout, and lambda based design rule
checks.
2. Design and simulation of basic logic gates using MOS, CMOS and BiCMOS
technology.
3. Design and simulation of basic logic gates and D-flip flop using pass transistors and
transmission gate.
4. Design and verification of 1-bit Parity generator cell using CMOS layout
5. Design and verification of 4x1 Multiplexer using CMOS layout

Sub-system Design using Verilog HDL

6. Design and verification of basic logic gates and flip flops using Verilog HDL based
Testbenches.
7. Design of basic combinational circuits and transmission gates using Verilog switch
primitives.
8. Design of universal shift register and universal counter using Verilog HDL
9. Design of synchronous and asynchronous memories using Verilog HDL
10. Design of ALU and Linear feedback shift register using Verilog HDL.
11. Design of 3-input Arbiter and parity checker using Verilog HDL.

Mode of Evaluation CAT 1 (20%), CAT 2 (20%), CAT 3 (20%) LAB (40%)
Recommended by the Board 30-06-2018
of Studies on
Date of Approval by the 2nd Academic Council 21.07.2018
Academic Council

You might also like