MISRIMAL NAVAJEE MUNOTH JAIN ENGINEERING COLLEGE

(Managed by Tamil Nadu Educational and Medical Trust)

Thoraipakkam, Chennai- 600 097.

LABORATORY RECORD

SUBJECT: EC8661 - VLSI Design Laboratory

NAME : …………………………….…..

CLASS : ………………………………..
REGISTER NO : …………………………………
 MISRIMAL NAVAJEE MUNOTH JAIN ENGINEERING COLLEGE
(Managed by Tamil Nadu Educational and Medical Trust)
Thoraipakkam, Chennai – 600 097

Name ……………………………………………………. Class ………………………………….

Register No ……………………………………………... Branch ……………………………….

Certified that this a bonafide record of the work done by the above student in
EC8661 - VLSI Design Laboratory during the year 2019-2020

Signature of Faculty-in-Charge Signature of Head of Department

Submitted for the Practical Examination held on ………………………………………………………

External Examiner Internal Examiner

Date:
 Index

Signature of
S. No. Name of the Experiment DATE Page
the faculty

1 Study of Xilinx ISE 9.1i

2 Study of XC3S400- Xilinx SPARTAN 3 FPGA

3 FPGA Design flow

4 Study of Simulation using XILINX ISE 9.1i

5 Study of Schematic entry using XILINX ISE 9.1i

Simulation and Implementation of 8-Bit Adder

6

Simulation and Implementation of 4-Bit

7
Multiplier

Simulation and implementation of

8
Arithmetic Logic Unit (ALU)

Simulation and Implementation of Universal

9
Shift Register

10 Simulation and Implementation of Finite State

Machine (Moore/Mealy)

11 Simulation and Implementation of RAM

12 Simulation of CMOS gates

13 Simulation of CMOS D-Flip Flop

14 Simulation of 4 Bit Synchronous Counter

15 Simulation of CMOS circuits using Tanner EDA

Simulation of a CMOS Differential Amplifier using

16
Tanner EDA

17 Layout of a CMOS Inverter

EX.NO:1 STUDY OF XILINX ISE9.1i
DATE:

AIM:
To study XILINX ISE 9.1i.

PROCEDURE:
Starting the ISE Software

To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting:

Start →All Programs →Xilinx ISE 9.1i →Project Navigator

Note: Your start-up path is set during the installation process and may differ from the one above.

Accessing Help

At any time during the tutorial, you can access online help for additional information about the ISE
software and related tools.

To open Help, do either of the following:

 Press F1 to view Help for the specific tool or function that you have selected or
highlighted.

 Launch the ISE Help Contents from the Help menu. It contains information about creating
and maintaining your complete design flow inISE.

Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board.

To create a new project:

 Select File New Project... The New Project Wizardappears.

 Type tutorial in the Project Namefield.
 Enter or browse to a location (directory path) for the newproject.
  A tutorial subdirectory is createdautomatically.
 Verify that HDL is selected from the Top-Level Source Typelist.
 Click Next to move to the device propertiespage.
 Fill in the properties in the table as shownbelow:
♦ Product Category:All
♦ Family:Spartan3
♦ Device:XC3S200
♦Package:FT256
♦Speed Grade:-4
♦ Top-Level Source Type:HDL
♦ Synthesis Tool: XST(VHDL/Verilog)
♦ Simulator: ISE Simulator(VHDL/Verilog)
♦ Preferred Language: Verilog (orVHDL)
♦ Verify that Enable Enhanced Design Summary isselected.
 Leave the default values in the remainingfields.

 When the table is complete, your project properties will look like thefollowing

 Click Next to proceed to the Create New Source window in the NewProject Wizard. At the end
of the next section, your new project will becomplete.

Create an HDL Source

In this section, you will create the top-level HDL file for your design. Determine the language that
you wish to use for the tutorial. Then, continue either to the “Creating a VHDL Source” section
below, or skip to the “Creating a Verilog Source” section.

Creating a VHDL Source

Create a VHDL source file for the project as follows:
 Click the New Source button in the NewProject Wizard.
 Select VHDL Module as the sourcetype.
 Type in the file namecounter.
 Verify that the Add to project checkbox isselected.
 ClickNext.
 Declaretheportsforthecounter designbyfillingintheport informationasshownbelow:
  Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new
source filetemplate.
 Click Next, then Next, thenFinish.
 The source file containing the entity/architecture pair displays in the
Workspace,andthecounterdisplaysintheSourcetab,asshownbelow:

Using Language Templates (VHDL)

Thenextstepincreatingthenewsourceistoaddthebehavioraldescriptionforthecounter.Todothis you will

use a simple counter code example from the ISE Language Templates and customize it for the
counterdesign.

 Place the cursor just below the begin statement within the counterarchitecture.
 Open the Language Templates by selecting Edit →LanguageTemplates…

 Note: You can tile the Language Templates and the counter file by
selecting Window →Tile Vertically to make them bothvisible.
 Using the “+” symbol, browse to the following codeexample:
 VHDL →Synthesis Constructs →Coding Examples→Counters
→Binary → Up/Down Counters →Simple Counter.
 With Simple Counter selected, select Edit →Use in File, or select the Use Templatein File
toolbar button. This step copies the template into the counter source file.
 Close the LanguageTemplates.
 Final Editing of the VHDL Source

 Add the following signal declaration to handle the feedback of the counter output below the
architecture declaration and above the first beginstatement:
 signal count_int : std_logic_vector(3 downto 0) :="0000";
 Customize the source file for the counter design by replacing the port and signal name
placeholders with the actual ones asfollows:
 replace all occurrences of <clock> withCLOCK
 replace all occurrences of <count_direction> with
DIRECTION
 ♦ replace all occurrences of <count> withcount_int
 Add the following line below the end process;statement:
 COUNT_OUT <=count_int;
 Save the file by selecting File→Save.
When you are finished, the counter source file will look like the following:

libraryIEEE;

use IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration ifinstantiating

-- any Xilinx primitive in thiscode.

--library UNISIM;

--use UNISIM.VComponents.all;

entity counteris

Port ( CLOCK:in STD_LOGIC;

DIRECTION:in STD_LOGIC;

COUNT_OUT:out STD_LOGIC_VECTOR (3 downto0));

end counter;

architecture Behavioral of counteris

signal count_int : std_logic_vector(3 downto 0) := "0000"; begin

process (CLOCK)
begin

if CLOCK='1' and CLOCK'event then if

DIRECTION='1' then

count_int <= count_int + 1; else

count_int <= count_int - 1; end

if;
 end if; end
process;

COUNT_OUT <=
count_int; end Behavioral;

Creating a Verilog Source

Create the top-level Verilog source file for the project as follows:
 Click New Source in the New Project dialogbox.
 Select Verilog Module as the source type in the New Source dialogbox.
 Type in the file namecounter.
 Verify that the Add to Project checkbox isselected.
 ClickNext.
 Declaretheportsforthecounter designbyfillingintheportinformationasshownbelow:

 Click Next, then Finish in the New Source Information dialog box to complete the new source
filetemplate.
 Click Next, then Next, thenFinish.
The source file containing the counter module displays in the Workspace, and the counter displays in the
Sources tab, as shown below:

Using Language Templates (Verilog)

The next step in creating the new source is to add the behavioral description for counter. Use a simple
counter code example from the ISE Language Templates and customize it for the counter design.
 Place the cursor on the line below the output [3:0] COUNT_OUT;statement.
 Open the Language Templates by selecting Edit →LanguageTemplates…
 Note: You can tile the Language Templates and the counter file by
selecting Window →Tile Vertically to make them bothvisible.
 Using the “+” symbol, browse to the following codeexample:
 Verilog →Synthesis Constructs →Coding Examples→Counters
→Binary →
 Up/Down Counters →SimpleCounter
 With Simple Counter selected, select Edit →Use in File, or select the Use Templatein File
toolbar button. This step copies the template into the counter source file.
 Close the LanguageTemplates.

Final Editing of the Verilog Source
 To declare and initialize the register that stores the counter value, modify the declaration
statement in the first line of the template asfollows:
 replace: reg [<upper>:0] <reg_name>; with: reg [3:0]
count_int =0;
 Customize the template for the counter design by replacing the port and signal name
placeholders with the actual ones asfollows:
 replace all occurrences of <clock> with CLOCK
 replace all occurrences of <up_down> withDIRECTION
 replace all occurrences of <reg_name> with count_int
 Add the following line just above the endmodule statement to assign the register value to the
outputport:
 assign COUNT_OUT =count_int;
 Save the file by selecting File→Save.

When you are finished, the code for the counter will look like the following:

module counter(CLOCK, DIRECTION,

COUNT_OUT); input CLOCK;

inputDIRECTION;

output [3:0]COUNT_OUT;

reg [3:0] count_int = 0; always

@(posedge CLOCK)
if(DIRECTION)

count_int <= count_int + 1; else

count_int <= count_int - 1;

assign COUNT_OUT = count_int;

endmodule

You have now created the Verilog source for the tutorial project.

Checking the Syntax of the New Counter Module

When the source files are complete, check the syntax of the design to find errors and typos.
 Verify that Synthesis/Implementation is selected from the drop-down list in the Sources
window.
 Select the counter design source in the Sources window to display the related processes
in the Processeswindow.
 Click the “+” next to the Synthesize-XST process to expand the processgroup.
 Double-click the Check Syntaxprocess.
 Note:Youmustcorrectanyerrorsfoundinyoursourcefiles.Youcan check
for errors in the Console tab of the Transcript window. If you
continue without valid syntax, you will not be able to simulate or
synthesize yourdesign.
 Close the HDLfile.

Design Simulation
Verifying Functionality using Behavioral Simulation

Create a test bench waveform containing input stimulus you can use to verify the functionality of the
counter module. The test bench waveform is a graphical view of a test bench.

Create the test bench waveform as follows:

 Select the counter HDL file in the Sourceswindow.
 Create a new test bench source by selecting Project →NewSource.
 In the New Source Wizard, select Test Bench WaveForm as the source type, andtype
counter_tbw in the File Name field.
 ClickNext.
 The Associated Source page shows that you are associating the test bench waveform with the
source file counter. ClickNext.
 The Summary page shows that the source will be added to the project, and it displays the source
directory, type and name. ClickFinish.
 You need to set the clock frequency, setup time and output delay times in the Initialize Timing
dialog box before the test bench waveform editing windowopens.
 The requirements for this design are thefollowing:

♦ Thecountermustoperatecorrectlywithaninputclockfrequency=25 MHz.
♦ TheDIRECTIONinputwill bevalid10nsbeforetherisingedgeof
CLOCK.
♦ Theoutput(COUNT_OUT)mustbevalid10nsaftertherisingedgeof
CLOCK. The design requirements correspond with the valuesbelow.
 Fill inthefieldsintheInitializeTimingdialogboxwiththefollowinginformation:

♦ Clock High Time: 20ns

♦ Clock Low Time:20ns
♦ Input Setup Time: 10ns
♦ Output Valid Delay:10ns
♦ Offset: 0ns.
♦ Global Signals: GSR(FPGA)
Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatic
Initial Length of Test Bench: 1500 ns.


 Click Finish to complete the timinginitialization.

 TheblueshadedareasthatprecedetherisingedgeoftheCLOCK correspondtotheInputSetup Time in
the Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for
the counter design asfollows:
♦ Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the
counter will countup
♦ Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that the
counter will countdown
 Save thewaveform.
 In the Sources window, select the Behavioral Simulation view to see that the test bench
waveform file is automatically added to yourproject.
 Close the test benchwaveform.
Simulating Design Functionality

Verify that the counter design functions as you expect by performing behavior simulation as follows:
 VerifythatBehavioralSimulationandcounter_tbwareselectedintheSources window.
 In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and double-
click the Simulate Behavioral Modelprocess.
 The ISE Simulator opens and runs the simulation to the end of the test
bench.
 Toviewyoursimulationresults,selecttheSimulationtabandzoominonthetransitions.
 Verify that the counter is counting up and down asexpected.
 Closethesimulationview.Ifyouarepromptedwiththefollowingmessage,“Youhaveanactive
simulation open. Are you sure you want to close it?“, click Yes tocontinue.
You have now completed simulation of your design using the ISE Simulator.

Create Timing Constraints

Specify the timing between the FPGA and its surrounding logic as well as the frequency the design
must operate at internal to the FPGA. The timing is specified by entering constraints that guide the
placement and routing of the design. It is recommended that you enter global constraints. The clock
period constraint specifies the clock frequency at which your design must operate inside the FPGA. The
offset constraints specify when to expect valid data at the FPGA inputs and when valid data will be
available at the FPGA outputs.

Entering Timing Constraints

To constrain the design do the following:

 Select Synthesis/Implementation from the drop-down list in the Sourceswindow.

 Select the counter HDL sourcefile.
 Click the “+” sign next to the User Constraints processes group,and double-click the
 Create Timing Constraintsprocess.
 ISE runs the Synthesis and Translate steps and automatically
creates a User Constraints File (UCF). You will be prompted
with the followingmessage:
 Click Yes to add the UCF file to yourproject.
 The counter.ucf file is added to your project and is visible in the Sources
window. The Xilinx Constraints Editor opensautomatically.
 Note: You can also create a UCF file for your project byselecting
Project →Create New Source.
 In the next step, enter values in the fields associated with CLOCK in the
Constraints Editor Globaltab.
 Select CLOCK in the Clock Net Name field, then select the Period toolbar button or double-
click the empty Period field to display the Clock Period dialogbox.

 Enter 40 ns in the Timefield.

 Click OK.
 Select the Pad to Setup toolbar button or double-click the empty Pad to Setup field to display
the Pad to Setup dialogbox.

 Enter 10 ns in the OFFSET field to set the input offsetconstraint.

  Click OK.
 Select the Clock to Pad toolbar button or double-click the empty Clock to Pad field to display
the Clock to Pad dialogbox.
 Enter 10 ns in the OFFSET field to set the output delayconstraint.

 Click OK.
 The constraints are displayed in theConstraints (

 Save the timing constraints. If you are prompted to rerun the TRANSLATE or XST step,
click OK tocontinue.
 Close the ConstraintsEditor.

Implement Design and Verify Constraints

Implement the design and verify that it meets the timing constraints specified in the previous
section.
Implementing the Design

 Select the counter source file in the Sourceswindow.

 Open the Design Summary by double-clicking the View Design Summary process in the
Processestab.
 Double-click the Implement Design process in the Processestab.
 Notice that after Implementation is complete, the Implementation processes have a green
check mark next to them indicating that they completed successfully without Errors or
Warnings.
 5. LocatethePerformanceSummarytablenearthebottomofthe
DesignSummary.
 Click the All Constraints Met link in the Timing Constraints field to view the Timing
Constraints report. Verify that the design meets the specifiedtiming requirements.

 Close the DesignSummary.

Assigning Pin Location Constraints

Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan-3
Startup Kit demo board.
To constrain the design ports to package pins, do the following:

 Verify that counter is selected in the Sources window.

 Double-clicktheAssignPackagePinsprocessfoundintheUserConstraintsprocessgroup.The Xilinx
Pinout and Area Constraints Editor (PACE)opens.
 Select the Package Viewtab.
 In the Design Object List window, enter a pin location for each pin in the Loc column using the
followinginformation:
♦ CLOCK input port connects to FPGA pin T9 (GCK0 signal onboard)
♦ COUNT_OUT<0> output port connects to FPGA pin K12 (LD0 signal on
board)
♦ COUNT_OUT<1> output port connects to FPGA pin P14 (LD1 signal on
board)
♦ COUNT_OUT<2> output port connects to FPGA pin L12 (LD2 signal on
board)
♦ COUNT_OUT<3> output port connects to FPGA pin N14 (LD3 signalon
board)
♦ DIRECTION input port connects to FPGA pin K13 (SW7 signal on
board)
 Select File →Save. You are prompted to select the bus delimiter type based on the synthesis
tool you are using. Select XST Default <>and clickOK.
 ClosePACE.
Reimplement Design and Verify Pin Locations

Reimplement the design and verify that the ports of the counter design are routed to the package pins
specified in the previous section.

First, review the Pinout Report from the previous implementation by doing the following:

 Open the Design Summary by double-clicking the View Design Summary process in the
Processeswindow.
 Select the Pinout Report and select the Signal Name column header to sort the signal names.
NoticethePinNumbersassignedtothedesignportsintheabsenceoflocationconstraints.

 Reimplement the design by double-clicking the Implement Designprocess.

 Select the Pinout Report again and select the Signal Name column header to sort the signal
names.
 Verify that signals are now being routed to the correct packagepins.
  Close the DesignSummary.

Download Design to the Spartan™-3 Demo Board

This is the last step in the design verification process. This section provides simple instructions for
downloading the counter design to the Spartan-3 Starter Kit demo board.
 Connectthe5VDCpowercabletothepowerinputonthedemo
board(J4).
 ConnectthedownloadcablebetweenthePCanddemoboard(J7).
 SelectSynthesis/Implementationfromthedrop-downlistinthe
Sourceswindow.
 Select counter in the Sourceswindow.
 IntheProcesseswindow, clickthe“+”signtoexpandthe
Generate Programming File processes.
 Double-click the Configure Device (iMPACT)process.
 TheXilinxWebTalkDialogboxmayopenduringthisprocess.
ClickDecline.
 SelectDisablethecollectionofdeviceusagestatisticsforthis
project only and clickOK.
 iMPACTopensandtheConfigureDevicesdialogboxisdisplayed.
  In the Welcome dialog box, select Configure devices using Boundary-Scan(JTAG).
 VerifythatAutomaticallyconnecttoacableandidentifyBoundary-Scanchainisselected.
 ClickFinish.
 Ifyougetamessagesayingthattherearetwodevicesfound,clickOKtocontinue.
 The devices connected to the JTAG chain on the board will be detected and
displayed in the IMPACTwindow
 The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200
device in the JTAG chain, select the counter.bit file and clickOpen.

 If you get a Warning message, clickOK.

 Select Bypass to skip any remainingdevices.
 Right-click on the xc3s200 device image, and select Program... The Programming Properties
dialog boxopens.
 ClickOKtoprogramthedevice.
 When programming is complete, the Program Succeeded message isdisplayed.

 Ontheboard,LEDs0,1,2, and3arelit, indicatingthat thecounterisrunning.

 Close IMPACT without saving.

RESULT:
Thus XILINX 9.1i is studied.
 XC3S400- XILINX SPARTAN 3 FPGA

XC3S400 – IC Details

Mark Revision Code

Device Type Fabrication Code

∑ XILINX
(XC3S400) F=UMC 8D (200nm)
Package SPARTAX G= UMC 12 A (300nm)
(TQG144EGQ0649)
TM
XC3S400
Grade Process Technology Q=90nm
(D3057375A) TQG1445PQ034
Data Code
D3057375A
Speed Range
4C
Temperature Range
EX.NO:2 STUDY OF XC3S400- XILINX SPARTAN 3FPGA
DATE:

AIM:
To study XC3S400 – XILINX Spartan 3 Field Programmable Gate Array (FPGA)
INTRODUCTION:
A field programmable gate array (FPGA) is a semiconductor device containing programmable
logic components called “configurable logic blocks” and programmable interconnects. Logic blocks can
be programmed to perform the logic functioning ranging from basic gates to more complex logic
function. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-
flops or more complete blocks of memory.
A hierarchy of programmable interconnects allows logic blocks to be interconnected as needed
by the system engineer (designer). These can be programmed by the designer, after FPGA is
manufactured, to implement any logical function – hence the name “FIELD PROGRAMMABLE”.

FPGA DESIGN AND PROGRAMMING

To define the behaviour of the FPGA the user provides a hardware description language (HDL)
or a schematic design. Common HDLs are VHDL and Verilog. Then, using an electronic design
automation tool, a technology netlist is generated. This can be then fitted to the actual FPGA
architecture using a process called place-and-route. The user will valiDATE the map, place and route
results via timing analysis, simulation and other verification methodologies. Once the design and
validation process is complete, the bit file is generated is used to configure the FPGA.

XILINX XC3S400 – SPARTAN 3 FPGA

It is specifically designed as very low cost, high performance logic solution for high volume,
consumer-oriented applications.
ARCHITECTURE OF XC3S400
This consists of 5 fundamental programmable functionable elements
1. Configurable logic blocks (CLB) contain RAM based look-up-tables (LUTs) to implement logic
and storage elements that can be used as flip flops or latches. CLBs can be programmed to
perform a wide variety of logical functions as well asto store data.
2. I/O Blocks (IOBs) control the flow of data between the I/O pin and the internal logic of the
device. Each IOB supports bidirectional data flow plus 2-state operations. Double Data rate
(DDR) registers are included. The digitally controlled impedance (DCI) feature provides
automatic on-chip terminations, simplifying boarddesigns.
3. Block RAM provides data storage in the form of 18-10 bit dual portblocks
4. Multiplierblocksaccept two18-bitbinarynumbersasinputsandcalculatetheproducts
5. Digital clock manager (DCM) blocks provide self calibrating, fully digital solution for
distributing, delaying, multiplying, dividing and phase shifting clocksignals
 These elements are organized as shown in the diagram. A ring of IOBs surrounds a regular array
of CLBs. It has 4 RAM columns. Each column is made up of several 18kbit RAM blocks; each block is
associated with a delicate multiplier. The DCMs are positioned at the ends of the outer block RAM
columns.

XC3S400 consists of rich network of traces and switches that interconnect all functional elements,
transmitting signals among them. Each functional element has an associated switch matrix that permits
multiple connections as routing.

RESULT:
Thus XC3S400 – XILINX SPARTAN 3 field programmable gate array (FPGA) was studied.
FPGA DESIGN FLOW
EX.NO:3 FPGA DESIGN FLOW
DATE:

AIM
To study FPGA design flow using XILINX ISE – 9.1i
INTRODUCTION:
The integrated software environment (ISE) is the Xilinx design software that allows to take the
design from design entry through Xilinx device programming. The ISE design flow comprises the
followingsteps,designentry,designsynthesis,designimplementation,andXilinxdeviceprogramming.
Design verification which includes both function verification and timing verification, takes place at
different points during the designflow.
DESIGN ENTRY:
Design entry is the first step in the ISE design flow. During design entry, sources files are
created based on the design objectives. The top-level design file can be created using a Hardware
Description Language (HDL), such as VHDL, Verilog or using a schematic.
SYNTHESIS:
After design entry and optional simulation, the synthesis step is run. During this step, VHDL,
verilog, or mixed language designs become netlist files that are accepted as input to the implementation
step.
IMPLEMENTATION:
After synthesis, the design implementation is executed, which converts the logical design into a
physical file format that can be downloaded to the selected target device. From project Navigator, the
implementation process can be run in one step, or each of the implementation processes can be run
separately.
BACK ANNOTATION:
Back annotation is the translation of a routed or fitted design to a timing simulation netlist.
VERIFICATION:
The functionality of the design can be verified at several points is the design flow. The simulator
software can be used to verify the functionality and timing of the design or a portion of the design. The
simulator interprets VHDL or verilog code into circuit functionality and displays logical results of the
described HDL to determine correct circuit operation. Simulation allows to create and verify complex
functions in a relatively small amount of time. The in-circuit verification can also be run after
programming the device.
DEVICE CONFIGURATION:
After generating a programming file, the target device is configured. During configuration files
are generated and the programming files are downloaded from a host computer to a Xilinx device.

RESULT
Thus the FPGA design flow was studied using Xilinx ISE – 9.1i
EX.NO:4 STUDY OF SIMULATION USING XILINXISE-9.1i
DATE:

AIM:
To study the simulation of a digital circuit using Xilinx ISE 9.1i

INTRODUCTION:
During HDL simulation, the simulator software verified the functionality, the timing of the
design or portion of the design. The simulator interprets VHDL or Verilog code into circuit functionality
and displays the logical result of the desired HDL to determine correct circuit operation. Simulation
allows to create and verify complex functions in a relatively small amount of time.
Simulation takes place at several points in the design flow. It is one of the first steps after design
entry and one of the last steps after implementation. As part of verifying the end functionality and
performance of the design.
Simulation is an iterative process, which may require repeating until both design functionality
and performance timing is met. For a typical design, simulation libraries
1. Compilation of the simulationlibraries
2. Creation of the designs testbench
3. Functionalsimulation
4. Implementation of the design and creation of thetiming simulation netlist
5. Timingsimulation
SIMULATION LIBRARIES
Most designs are built with gentle code, so device specific components are not necessary.
However in certain cases if may be required or beneficial to use device specification components in the
codetoachievethedesiredcircuitimplementationandresultswhenthecomponentisinstantiatedinthe
design,thesimulatormustreferencealibrarythatdescribesthefunctionalityofthecomponenttoensure proper
simulation, XILINX provides simulation libraries for simulationprimitives.
UNISIM library for functional simulation of XILINX primitives
XILINX core library for functional simulation of linx primitives
SIMPRIM lib for timing simulation of XILINX primitives
TEST BENCH
To simulate your design you need both the design under test (DUT) or unit under test (UUT) and
the stimulus provided by the test bench. A test bench is HDL code that allows to provide a documental,
repeatable set of stimuli that is portable across different simulator. A test bench can be as simple as a file
with clock and input data or a more complicated file that includes error checking, file input and output
and conditional testing. The test bench can be created using either of the following methods.

(i) TEXTEDITOR
This is the recommended method for verifying complex designs. It allows using all the
features available in the HDL language and gives you flexibility in verifying design.
Although this method may be more challenging in that one must create this code, the
advantage is that it may produce more precise & accurate results than using the bench
waveform editor.
 (ii) XILINX TEST BENCH WAVEFORM EDITOR
This is the recommended method for verifying less complicated simulation tasks, and is
recommendedifthedesignerisnewtoHDLsimulation.Itallowstographicallyenterthetest bench to
drive the stimulus to the design. The same test bench can be used for both functions and
timing simulation.
FUNCTIONALSIMULATION
After the simulation libraries & create the test bench & design code are compiled, one can
perform functional simulation on the design. Functional simulation is an iterative process, which may
require multiple simulations to achieve the desired end functionality of the design.

RESULT
Thus the Simulation using XILINX ISE-9.1i was studied.
EX.NO:5 STUDY OF SCHEMATIC ENTRY USING XILINX ISE9.1i
DATE:

AIM
To study the schematic entry of a digital circuit using XILINX ISE9.1i.
INTRODUCTION
Schematics are used for top level or lower level design files. It allows to have a visual
representation of the design.
TOP LEVEL SCHEMATIC
Schematics are used in the top level and low level modules are created using any of the
following source types. To instantiate a lower level module in the top level design and the schematic
symbol is instantiated.
LOWER LEVEL SCHEMATIC
Schematics can be used to define the lower level modules of the design. If the top level design is
schematic symbol is created and it is instantiated in the top level. If the top level design file is an HDL
file a template is created.
All schematics are ultimately converted either VHDL or verilog structural netlist before being
passed.
SCHEMATIC DESIGN METHODS
When using a schematic the top level design either of the following method is used to describe
the lower level modules.
i) TOP-DOWN SCHEMATIC DESIGNMETHOD
Using this method a top level block diagram description of the design is created using a
schematic. Then each symbol pushed down and its behaviour is defined using HDL or schematic file.
1) SCHEMATIC:
The schematic contains input markers that correspond to the pins in the block symbol created.
The schematic is built by adding symbols ad described in adding a symbol.
2) VHDL (OR)VERILOG:
The template contains HDC port descriptions that correspond to the pins in the block symbol
created. The behavior of the module can be then added. The ISE language template provides a
convenient method to insert.
ii) BOTTON-UP SCHEMATIC DESIGNMETHOD:
Using this method a top level schematic design is created and lower level functional blocks is
then created to instantiate.

RESULT:
Thus the schematic entry of a digital circuit was studied using XILINX ISE 9.1i.
8-BIT ADDER

BLOCK DIAGRAM

TRUTH TABLE

A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
EX.NO:6 SIMULATION AND IMPLEMENTATION OF 8-BIT ADDER
DATE:

AIM
To Simulate and Implement the 8-Bit Adder using XILINX ISE 9.1i .

APPARATUS REQUIRED
1. PC with Xilinx ISE 9.1i
2. XC3S400 FPGA kit

PROGRAM
8-BIT ADDER

module bit_8_adder(A,B,Cin,S,Cout);
input [7:0] A,B;
input Cin;
output [7:0] S;
output Cout;
wire C0,C1,C2,C3,C4,C5,C6;
full_add FA0(A[0],B[0],Cin, S[0], C0);
full_add FA1(A[1],B[1],C0, S[1], C1);
full_add FA2(A[2],B[2],C1, S[2], C2);
full_add FA3(A[3],B[3],C2, S[3], C3);
full_add FA4(A[4],B[4],C3, S[4], C4);
full_add FA5(A[5],B[5],C4, S[5], C5);
full_add FA6(A[6],B[6],C5, S[6], C6);
full_add FA7(A[7],B[7],C6, S[7], Cout);
endmodule
module full_add(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum = a^b^c;
assign carry = (a&b)|(b&c)|(c&a);
endmodule
8-BIT ADDER

RTL SCHEMATIC

TESTBENCH WAVEFORM
PROCEDURE
1. Open the Xilinx software and click the menu option file and select the new project from the sub menu
2. In the process tab, click on create new source->Verilog module. Then give a file name for it and select the
respective inputs and outputs from it.
3. Enter the given code respectively.
4. Go to process tab, click on synthesize XST->check syntax for checking the program.
5. From the process tab, click on create new source->test bench waveform and give a file name to it.
6. Select combinational in initial timing and clock wizard.
7. Give the input in the waveform module
8. In the sources tab change to behavioral simulation and click the test bench file you have created.
9. Click on the XILINX ISE Simulator from the process tab and select the simulate behavioral model.
10. The output will be obtained in the wave form module.

IMPLEMENTATION
1. Select the source file in the sources window
2. Open the design summary by clicking the view design process in the processes tab.
3. DOUBLE Click the implement design process in the process tab.
4. Notice that after implementation is complete, the implementation processes have a green check mark next
to them indicating that they are completed successfully without any errors or warnings.
5. Locate the performance summary table near the bottom of the design summary.
6. Click the all constraints met link in the timing constraints report. Verify that the design meets the specified
timing requirements.
7. Close the design summary.
RESULT
Thus the 8-Bit Adder is Simulated and Implemented.
4-BIT MULTIPLIER

BLOCK DIAGRAM

RTL SCHEMATIC

TESTBENCH WAVEFORM
EX.NO:7 SIMULATION AND IMPLEMENTATION Of 4-BIT MULTIPLIER
DATE:
AIM
To Simulate and Implement the 4 Bit Multiplier using XILINX ISE 9.1i.

APPARATUS REQUIRED
1. PC with Xilinx ISE 9.1i
2. XC3S400 FPGA kit

PROGRAM
4-BIT MULTIPLIER

module multiplier_4_bit (A,B,C);

input [3:0] A;
input [3:0] B;
output [7:0] C;
assign C[7:0] =A[3:0] * B[3:0];
endmodule

PROCEDURE
1. Open the Xilinx software and click the menu option file and select the new project from the sub menu
2. In the process tab, click on create new source->verilog module. Then give a file name for it and select the
respective inputs and outputs from it.
3. Enter the given code respectively.
4. Go to process tab, click on synthesise XST->check syntax for checking the program.
5. From the process tab, click on create new source->test bench waveform and give a file name to it.
6. Select combinational in initial timing and clock wizard.
7. Give the input in the waveform module
8. In the sources tab change to behavioural simulation and click the test bench file you have created.
9. Click on the XILINX ISE Simulator from the process tab and select the simulate behavioural model.
10. The output will be obtained in the wave form module.

IMPLEMENTATION
1. Select the source file in the sources window.
2. Open the design summary by clicking the view design process in the processes tab.
3. DOUBLE Click the implement design process in the process tab.
4. Notice that after implementation is complete, the implementation processes have a green check mark next
to them indicating that they are completed successfully without any errors or warnings.
5. Locate the performance summary table near the bottom of the design summary.
6. Click the all constraints met link in the timing constraints report. Verify that the design meets the specified
timing requirements.
7. Close the design summary.

RESULT
Thus the 4-Bit Multiplier is Simulated and Implemented.
ARITHMETIC LOGIC UNIT

RTL SCHEMATIC

TESTBENCH WAVEFORM
EX.NO:8 SIMULATION AND IMPLEMENTATION OF
DATE: ARITHMETIC LOGIC UNIT (ALU)
AIM
To Simulate and Implement the Arithmetic logic unit (ALU).

APPARATUS REQUIRED
1. PC with Xilinx ISE 9.1i
2. XC3S400 FPGA kit

PROGRAM
ARITHMETIC LOGIC UNIT

module alu (a, b, s, clk, c);

input [2:0] a;
input [2:0] b;
input [2:0] S;
input clk;
output [5:0]c;
reg [5:0]c;
always@ (posedge clk)
case (s)
3’b000: c=a+b;
3’b001: c=a-b;
3’b010: c=~(a+b);
3’b011: c=a*b;
3’b100: c=a&b;
3’b101: c=~a;
3’b110: c=a/b;
3’b111: c=a^b;
endcase
endmodule

PROCEDURE
1. Open the Xilinx software and click the menu option file and select the new project from the sub menu
2. In the process tab, click on create new source->verilog module. Then give a file name for it and select
the respective inputs and outputs from it.
3. Enter the given code respectively.
4. Go to process tab, click on synthesise XST->check syntax for checking the program.
5. From the process tab, click on create new source->test bench waveform and give a file name to it.
6. Select combinational in initial timing and clock wizard.
7. Give the input in the waveform module
8. In the sources tab change to behavioural simulation and click the test bench file you have created.
9. Click on the XILINX ISE Simulator from the process tab and select the simulate behavioural model.
10. The output will be obtained in the wave form module.
IMPLEMENTATION
1. Select the source file in the sources window
2. Open the design summary by clicking the view design process in the processes tab.
3. DOUBLE Click the implement design process in the process tab.
4. Notice that after implementation is complete, the implementation processes have a green check mark
next to them indicating that they are completed successfully without any errors or warnings.
5. Locate the performance summary table near the bottom of the design summary.
6. Click the all constraints met link in the timing constraints report. Verify that the design meets the
specified timing requirements.
7. Close the design summary.

RESULT
Thus the Arithmetic Logic Unit is Simulated and Implemented.
UNIVERSAL SHIFT REGISTER

RTL SCHEMATIC

TESTBENCH WAVEFORM
EX.NO:9 SIMULATION AND IMPLEMENTATION OF
DATE: UNIVERSAL SHIFT REGISTER

AIM
To Simulate and Implement the Universal Shift Register.

APPARATUS REQUIRED
1. PC with Xilinx ISE 9.1i

2. XC3S400 FPGA kit

PROGRAM
UNIVERSAL SHIFT REGISTER

module unishft_reg(s1,s0,PIin,LFin,RTin,clk,reset,q3,q2,q1,q0);
input s1,s0;
input LFin,RTin;
input clk,reset;
input[3:0]PIin;
output q3,q2,q1,q0;
reg q3,q2,q1,q0;
always @ (posedge clk or posedge reset)
if (reset)
{q3,q2,q1,q0}=4'b0000;

else

case ({s1,s0})

2'b00:{q3,q2,q1,q0}={q3,q2,q1,q0};

2'b01:{q3,q2,q1,q0}={RTin,q3,q2,q1};

2'b10:{q3,q2,q1,q0}={q2,q1,q0,LFin};

2’b11 :{q3,q2,q1,q0}=PIin;

endcase
endmodule
 PROCEDURE
1. Open the Xilinx software and click the menu option file and select the new project from the sub menu
2. In the process tab, click on create new source->verilog module. Then give a file name for it and
select the respective inputs and outputs from it.
3. Enter the given code respectively.
4. Go to process tab, click on synthesise XST->check syntax for checking the program.
5. From the process tab, click on create new source->test bench waveform and give a file name to it.
6. Select combinational in initial timing and clock wizard.
7. Give the input in the waveform module
8. In the sources tab change to behavioural simulation and click the test bench file you have created.
9. Click on the XILINX ISE Simulator from the process tab and select the simulate behavioural model.
10. The output will be obtained in the wave form module.

IMPLEMENTATION
1. Select the source file in the sources window
2. Open the design summary by clicking the view design process in the processes tab.
3. DOUBLE Click the implement design process in the process tab.
4. Notice that after implementation is complete, the implementation processes have a green check
mark next to them indicating that they are completed successfully without any errors or warnings.
5. Locate the performance summary table near the bottom of the design summary.
6. Click the all constraints met link in the timing constraints report. Verify that the design meets
the specified timing requirements.
7. Close the design summary.

RESULT
Thus the Universal Shift Register is Simulated and Implemented.
MOORE MODEL

RTL SCHEMATIC

TESTBENCH WAVEFORM
EX.NO:10 SIMULATION AND IMPLEMENTAION OF
DATE: FINITE STATE MACHINE

AIM
To Simulate and Implement the Finite State Machine (Moore/Mealy)

APPARATUS REQUIRED
1. PC with Xilinx ISE 9.1i
2. XC3S400 FPGA Kit

PROGRAM
MOORE MODEL
module Moore_Model (output[1:0] y_out, input x_in, clock, reset);
reg[1:0] state;
parameter s0= 2’b00, s1=2’b01, s2= 2’b10, s3= 2’b11;
always@ (posedgeclock, negedgereset)
if (reset== 0) state<= s0;
else case (state)
s0: if(~x_in) state<= s1; else state<= s0;
s1: if (x_in) state<= s2; else state<= s3;
s2: if (~x_in) state<=s3; else state<= s2;
s3: if (~x_in) state<=s0; else state<= s3;
endcase
assign y_out= state;
endmodule
MEALY MODEL

RTL SCHEMATIC

TESTBENCH WAVEFORM
MEALY MODEL
module mealy_model (outputregy_out, input x_in, clock, reset);
reg[1:0] state, next_state;
parameter s0= 2’b00, s1= 2’b01, s2= 2’b10, s3= 2’b11;
always@ (posedgeclock, negedgereset)
if (reset==0) state<= s0;
else state<= next_state;
always@(state, x_in)
case (state)
s0: if (x_in) next_state= s1; else next_state= s0;
s1: if (x_in) next_state= s3; else next_state= s0;
s2: if (~x_in) next_state= s0; else next_state= s2;
s3: if (x_in) next_state= s2; else next_state= s0;
endcase
always@ (state, x_in)
case (state)
s0: y_out=0;
s1, s2, s3: y_out= ~x_in;
endcase
endmodule

PROCEDURE
1. Open the Xilinx software and click the menu option file and select the new project from the sub menu.
2. In the process tab, click on create new source ->verilog module. Then give a file name for it and select the
respective inputs and outputs from it.
3. Enter the given code respectively.
4. Go to process tab, click on synthesis XST -> check syntax for checking the program.
5. From the process tab, click on create new source -> test bench waveform and give a file name to it.
6. Select combinational in initial timing and clock wizard.
7. Give the input in the waveform module.
8. In the sources tab change to behavioural simulation and click the test bench file you have created.
9. Click on the XILINX ISE simulator from the process tab and select the simulate behavioural model.
10. The output will be obtained in the waveform module.
IMPLEMENTATION
1. Select the source file in the sources window.
2. Open the design summary by clicking the view design process in the processes tab.
3. DOUBLE Click the implement design process in the process tab.
4. Notice that after implementation is complete, the implementation processes have a green check mark next
to them indicating that they are completed successfully without any errors or warnings.
5. Locate the performance summary table near the bottom of the design summary.
6. Click the all constraints met link in the timing constraints report. Verify that the design meets the specified
timing requirements.
7. Close the design summary.

RESULT
Thus the Finite State Machine (Moore/Mealy) is simulated and implemented.
RAM

RTL SCHEMATIC

TESTBENCH WAVEFORM
EX.NO:11 SIMULATION AND IMPLEMENTATION OF RAM
DATE:

AIM
To Simulate and Implementation the RAM.

APPARATUS REQUIRED
1. PC with Xilinx ISE 9.1i
2. XC3S400 FPGA Kit

PROGRAM
RAM
module memory(data, addr, we, clk, q);
input[7:0] data;
input[5:0] addr;
input we;
input clk;
output[7:0] q;
reg[7:0] ram[63:0];
reg[5:0] addr_reg;
always@(negedge clk)
begin
if (we)
ram[addr]<=data;
addr_reg<=addr;
end
assign q=ram[addr_reg];
endmodule

PROCEDURE
1. Open the Xilinx software and click the menu option file and select the new project from the sub menu.
2. In the process tab, click on create new source ->verilog module. Then give a file name for it and select the
respective inputs and outputs from it.
3. Enter the given code respectively.
4. Go to process tab, click on synthesis XST -> check syntax for checking the program.
5. From the process tab, click on create new source -> test bench waveform and give a file name to it.
6. Select combinational in initial timing and clock wizard.
7. Give the input in the waveform module.
8. In the sources tab change to behavioural simulation and click the test bench file you have created.
9. Click on the XILINX ISE simulator from the process tab and select the simulate behavioural model.
10. The output will be obtained in the waveform module.
IMPLEMENTATION
1. Select the source file in the sources window.
2. Open the design summary by clicking the view design process in the processes tab.
3. DOUBLE Click the implement design process in the process tab.
4. Notice that after implementation is complete, the implementation processes have a green check mark next
to them indicating that they are completed successfully without any errors or warnings.
5. Locate the performance summary table near the bottom of the design summary.
6. Click the all constraints met link in the timing constraints report. Verify that the design meets the specified
timing requirements.
7. Close the design summary.

RESULT
Thus the RAM is Simulated and Implemented.
CMOS INVERTER

BLOCK DIAGRAM

p-mos

n-mos

TESTBENCH WAVEFORM
EX.NO:12 SIMULATION OF CMOS GATES
DATE:

AIM
To Simulate the CMOS Gates.

APPARATUS REQUIRED
1. PC with Xilinx ISE 9.1i
2. XC3S400 FPGA Kit

PROGRAM
CMOS INVERTER
module my_not (out, in);
output out;
input in;
supply1 pwr;
supply0 gnd;
pmos (out, pwr, in);
nmos (out, gnd, in);
endmodule

CMOS NOR GATE

module my_nor (out, a, b);
output out;
input a, b;
wire c;
supply1 pwr;
supply0 gnd;
pmos p1 (c, pwr, b);
pmos p2 (out, c, a);
nmos n1 (out, gnd, a);
nmos n2 (out, gnd, b);
endmodule
CMOS NOR GATE

BLOCK DIAGRAM

A P1

P2 B

OUT

N1 N2

TESTBENCH WAVEFORM
CMOS NAND GATE

module my_nand (out, a, b);

output out;
input a, b;
wire c;
supply1 pwr;
supply0 gnd;
pmos p1 (out, pwr, a);
pmos p2 (out, pwr, b);
nmos n1 (c, gnd, b);
nmos n2 (out, c, a);
endmodule

PROCEDURE
1. Open the Xilinx software and click the menu option file and select the new project from the sub menu.
2. In the process tab, click on create new source ->verilog module. Then give a file name for it and select
the respective inputs and outputs from it.
3. Enter the given code respectively.
4. Go to process tab, click on synthesis XST -> check syntax for checking the program.
5. From the process tab, click on create new source -> test bench waveform and give a file name to it.
6. Select combinational in initial timing and clock wizard.
7. Give the input in the waveform module.
8. In the sources tab change to behavioural simulation and click the test bench file you have created.
9. Click on the XILINX ISE simulator from the process tab and select the simulate behavioural model.
10. The output will be obtained in the waveform module.

IMPLEMENTATION
1. Select the source file in the sources window.
2. Open the design summary by clicking the view design process in the processes tab.
3. DOUBLE Click the implement design process in the process tab.
4. Notice that after implementation is complete, the implementation processes have a green check mark
next to them indicating that they are completed successfully without any errors or warnings.
5. Locate the performance summary table near the bottom of the design summary.
6. Click the all constraints met link in the timing constraints report. Verify that the design meets the
specified timing requirements.
7. Close the design summary.
CMOS NAND GATE

BLOCK DIAGRAM

P1 P2

N1

N2

TESTBENCH WAVEFORM
RESULT

Thus the CMOS Gates are Simulated.

CMOS D-FLIPFLOP

BLOCK DIAGRAM

TESTBENCH WAVEFORM
EX.NO:13 SIMULATION OF CMOS D-FLIPFLOP
DATE:

AIM
To Simulate the CMOS D-FlipFlop.

APPARATUS REQUIRED
1. PC with Xilinx ISE 9.1i
2. XC3S400 FPGA Kit

PROGRAM
CMOS D-FLIPFLOP

module DFF (q,qbar,dd,clk);

outputq,qbar;
inputd,clk;
wire e;
wireclkbar;
my_not(clkbar,clk);
cmos C1(e,d,clk,clkbar);
cmos C2(e,q,clkbar,clk);
my_not(qbar,e);
my_not(qbar,e);
endmodule

modulemy_not(out,in);
output out;
input in;
supply1pwr;
supply0gnd;
pmos (out,pwr,in);
nmos(out,gnd,in);
endmodule
PROCEDURE
1. Open the Xilinx software and click the menu option file and select the new project from the sub menu.
2. In the process tab, click on create new source ->verilog module. Then give a file name for it and select the
respective inputs and outputs from it.
3. Enter the given code respectively.
4. Go to process tab, click on synthesis XST -> check syntax for checking the program.
5. From the process tab, click on create new source -> test bench waveform and give a file name to it.
6. Select combinational in initial timing and clock wizard.
7. Give the input in the waveform module.
8. In the sources tab change to behavioural simulation and click the test bench file you have created.
9. Click on the XILINX ISE simulator from the process tab and select the simulate behavioural model.
10. The output will be obtained in the waveform module.

IMPLEMENTATION
1. Select the source file in the sources window.
2. Open the design summary by clicking the view design process in the processes tab.
3. DOUBLE Click the implement design process in the process tab.
4. Notice that after implementation is complete, the implementation processes have a green check mark
next to them indicating that they are completed successfully without any errors or warnings.
5. Locate the performance summary table near the bottom of the design summary.
6. Click the all constraints met link in the timing constraints report. Verify that the design meets the
specified timing requirements.
7. Close the design summary.

RESULT
 Thus the CMOS D-FlipFlop is Simulated.
4-BIT SYNCHRONOUS COUNTER

BLOCK DIAGRAM

TESTBENCH WAVEFORM
EX.NO:14 SIMULATION OF 4-BIT SYNCHRONOUS COUNTER
DATE:

AIM
To Simulate the 4-Bit Synchronous Counter.

APPARATUS REQUIRED
1. PC with Xilinx ISE 9.1i
2. XC3S400 FPGA Kit

PROGRAM
4-BIT SYNCHRONOUS COUNTER
module counter (clk, reset, q);
input clk;
input reset;
output[3:0];
always@ (posedge clk)
if (reset) q<= 4’b0;
else q<= q+1;
endmodule

PROCEDURE
1. Open the Xilinx software and click the menu option file and select the new project from the sub menu.
2. In the process tab, click on create new source ->verilog module. Then give a file name for it and select the
respective inputs and outputs from it.
3. Enter the given code respectively.
4. Go to process tab, click on synthesis XST -> check syntax for checking the program.
5. From the process tab, click on create new source -> test bench waveform and give a file name to it.
6. Select combinational in initial timing and clock wizard.
7. Give the input in the waveform module.
8. In the sources tab change to behavioural simulation and click the test bench file you have created.
9. Click on the XILINX ISE simulator from the process tab and select the simulate behavioural model.
10. The output will be obtained in the waveform module.
IMPLEMENTATION
1. Select the source file in the sources window.
2. Open the design summary by clicking the view design process in the processes tab.
3. DOUBLE Click the implement design process in the process tab.
4. Notice that after implementation is complete, the implementation processes have a green check mark
next to them indicating that they are completed successfully without any errors or warnings.
5. Locate the performance summary table near the bottom of the design summary.
6. Click the all constraints met link in the timing constraints report. Verify that the design meets the
specified timing requirements.
7. Close the design summary.

RESULT

Thus the 4-Bit Synchronous Counter is Simulated.

EX.NO.15 SIMULATION OF CMOS CIRCUITS USING
DATE: TANNER EDA

AIM:
To perform the Simulation of CMOS circuits using Tanner EDA .

APPARATUS REQUIRED:
System with P4 Processor & Tanner EDA Tool.

THEORY:
Tanner EDA (Electronic design automation)is a suite of tools for the design of integrated
circuits. These tools allow you to enter schematics, perform SPICE simulations, do physical design (i.e.,
chip layout), and perform design rule checks (DRC) and layout versus schematic (LVS) checks. There
are 3 tools that are used for this process:

S-edit-a schematic capture tool.

T.S PICE-theSPICEsimulationengineintegratedwithS-edit. L-
edit-the physical designtool.

S-Edit:
S-edit is a schematic entry tool that is used to document circuits that can be driven forward into a
layout of an integrated circuit. It also provides the ability to perform SPICE simulations of the circuits
using a simulation engine called T-SPICE.

CMOS NOT GATE

SCHEMATIC:
OUTPUT WAVEFORM:

CMOS NAND GATE

SCHEMATICS:

OUTPUT WAVEFORM:
CMOS NOR GATE

SCHEMATIC:

OUTPUT WAVEFORM:
EX-OR USING CMOS NAND GATE:

SCHEMATIC:

OUTPUT WAVEFORM:
EX-NOR USING CMOS NAND GATE:

SCHEMATIC:

OUTPUT WAVEFORM:
EX-OR USING CMOS NOR GATE:

SCHEMATIC:

OUTPUT WAVEFORM:
SYMBOL FOR NAND GATE

SYMBOL FOR NOR GATE

BOOLEAN EXPRESSION Y=A+BC(~D) USING NAND

SCHEMATIC
OUTPUT WAVEFORM:

BOOLEAN EXPRESSION Y=A+BC(~D) USING NOR

SCHEMATIC:
OUTPUT WAVEFORM

PROCEDURE

Start a New Design & Setup Libraries

a) StartS-Edit:-Start→ AllPrograms→TannerEDA→TannerToolsv15.0→ S-Editv15.0
b) Start a NewDesign:

Using the pull down menus, create a new design:

- File → New → NewDesign

A dialog will appear asking for a design name and location. When you give the name, S-edit will create
a folder of that name in the directory that you provide that will contain all of the design files.

c) First,you needtoincludealibrarywhichcontainsthesymbolsforallbasiccircuitelementssuch as
resistors, NMOS, capacitors,etc…
d) e)OntheleftsideoftheS-editscreenyou’llseeaLibraries window,clickonthe“Add”button.
–

Browse to
Tanner EDA\TannerToolsv15.0\Process\Standard_Libraries\SPICE_Elements\SPICE_Elements.tanner”
and click“OK”
Again click on the add button:

Browse to“C:\Documents and Settings\administrator\My Documents\Tanner EDA\Tanner Tools

v15.0\Process\Generic_250nm\Generic_250nm_Devices\Generic_250nm_Devices.tanner”

Thelibrariesthatyou justaddedhavesymbolsforNMOSandPMOStransistors.However,allnon-
linearcomponentssuchasMOStransistorsrequireamodeltodescribetheirbehavior.wewillusea
transistortechnology called“Generic_025”,whichrepresentsastandard,0.25umCMOSprocess.

e) CreateanewCell.A“cell”isa designelement.Acellcancontainmultipleviewssuchas
schematics and symbols. Cells can be instantiated in othercells.

Using the pull down menus, create a new cell view:

- Cell – New View:
and clickOK.
A blank schematic page will appear.

f) EntertheNMOStransistor-Ontheleft,click on“Devices”intheupperwindow.Thiswill
displayallofthesymbolsavailableinthisgroup.You should seeallofthecomponentsthatyou can
implement on a CMOS integratedcircuit.

- Onthebottomleftwindow,clickonceon“NMOS”.Youshould seethesymboloftheNMOS
transistor show up in the symbol viewer window at the bottom.–

To place the NMOS, you will click on the “Instance” button. Two things happen when you click on this
button. First, a dialog will appear that will allow you to setup the parameters for the NMOS. Second, the
symbol will attach to your mouse. We will place the NMOS in the schematic first and then set its
properties later. This is an easier way to enter the device. Click in the schematic window to drop an
instance of the NMOS. Hit the “Esc” button to end the insert-mode. Repeat this same step for placing
PMOS transistor.

Enter a DC source/pulse source - Using the same process you used for the NMOS symbol, enter a
“SPICE_Elements: Voltage Source”. This is a generic voltage source symbol that is configured as a DC,
TRAN, PWL, etc.. in its properties dialog.

a) EnterVddandGnd:Usingthesameprocessyouused fortheNMOSsymbol,entera“Misc: Vdd”

and “Misc:Gnd”.
b) Enter Wires - You can enter wires by clicking on the “wire” icon at thetop

Enterwiresbyclickingonasymbolnodeandthendragging.Entercornersbyclickingonce where you

want to turn.

c) EnteringthePorts:PortsareenteredusingtheiconsonthetopoftheS-editwindow.Enterthe
following: In Port: Name it “IN” Out Port: Name it“OUT”
d) Setup – SPICESimulations

Using the pull down menus: - Setup → SPICE Simulations -

On the left, click on “Transient/Fourier Analysis”

On the right, enter the following

Stop time-600ns,maximum time step -10ns,print start time-1ns,print time step-10ns

Click on General-Library file and browse” Tanner EDA/Tanner Tools

v15.0/Process/Generic_250nm/Generic_250nm_Tech/Generic_250nm.lib tt”

e) Simulate theDesign

- ClickontheGreenArrowtostartthesimulator:TheT-Spicewindowwillappear.IfeverythingisOK, the
waveform viewer will alsoappear.

f) CreatetheInverterSymbolSymbolscaneitherbecreatedmanuallybycreatinganewsymbol view or
automatically by S-edit. Remove DCsource and pulsesource.

Click on cell- generate symbol- modify. Now we can draw our own symbol.

Result

The schematic of CMOS NOT, NAND, NOR , EX-OR and Boolean expression was drawn
using S-Edit and simulated.
EX.NO:16 SIMULATION OF A CMOS DIFFERENTIAL AMPLIFIER USING
DATE: TANNER EDA

AIM
To draw a CMOS Differential amplifier and perform the SPICE simulation. Also determine the
gain , bandwidth and Common mode rejection ratio ( CMRR ).

APPARATUS REQUIRED

System with P4 Processor & Tanner EDA Tool.

THEORY

A differential amplifier is a type of electronic amplifier that multiplies the difference between two
inputs by some constant factor (the differential gain).

Many electronic devices use differential amplifiers internally. The output of an ideal differential amplifier is
given by:

Vout = Ad(Vin1 – Vin2)

Where Vin1 and Vin2 are the input voltages and Ad is the differential gain. In practice, however, the gain is
not quite equal for the two inputs. This means that if Vin1 and Vin2 are equal, the output will not be zero,
as it would be in the ideal case. A more realistic expression for the output of a differential amplifier thus
includes a second term.

Vout = (Ad(Vin1 – Vin2) + Ac(Vin1 + Vin2))/2

Ac is called the common-mode gain of the amplifier. As differential amplifiers are often used when
it is desired to null out noise or bias-voltages that appear at both inputs, a low common-mode gain is
usually considered good.

The common-mode rejection ratio, usually defined as the ratio between differential-mode gain and common-
mode gain, indicates the ability of the amplifier to accurately cancel voltages that are common to both inputs.
Common- mode rejection ratio (CMRR):

CMRR= Ad / Ac
CIRCUIT DIAGRAM

PROCEDURE

 Draw the schematic of differential amplifier usingS-Edit.

 SPICE Commands -Print voltage->interface->Ac phase and Ac magnitude indb
 SPICE Commands->AC_Measure_Gain
 SPICE Commands->AC_Measure_GainBandwidthProduct
 Perform AC Analysis of the differentialamplifier.
 Goto setup ->spice simulation. Choose acanalysis and give the following values .
 Startfrequency=10,Stopfrequency=10meg,No.offrequency=25,Sweeptype=dec.Clickon
general type and give path to Generic_250nm.lib.Then ClickOK.
 RUN Simulation to getoutput.
 Change phase of one voltage source to1800
 Obtain the frequency response fromW-Edit.

OUTPUT

Common Mode:
Measurement result summary
AC_Measure_Gain_1 = 1.7293
At = 10.0000k
AC_Measure_GainBandwidthProduct_1= 3.5177k

Differential Mode:

Measurement result summary

AC_Measure_Gain_1 = 27.3656
At = 10.0000
AC_Measure_GainBandwidthProduct_1= 1.6359X

CMRR= Ad / Ac

RESULT:

The gain, bandwidth and CM RR of the differential amplifier was obtained using AC analysis.
EX.NO:17 LAYOUT OF A CMOS INVERTER
DATE:

AIM
To draw the layout of a CMOS inverter using L-EDIT and simulate it.

APPARATUS REQUIRED
System with P4 Processor & Tanner EDA Tool.

THEORY
Tanner EDA is a suite of tools for the design of integrated circuits. These tools allow you to enter
schematics, perform SPICE simulations, do physical design (i.e., chip layout), and perform design rule
checks (DRC) . There are 3 tools that are used for this process:

S-edit-a schematic capturetool.

T-SPICE-the SPICE simulation engine integrated with S-
edit. L-edit-the physical designtool.

S-Edit
S-edit is a schematic entry tool that is used to document circuits that can be driven forward into a layout
of an integrated circuit. It also provides the ability to perform SPICE simulations of the circuits using a
simulation engine called T-SPICE.

L - Edit (IC Physical Design Tool):

L - edit is an integrated circuit physical design tool from Tanner EDA. This tool allows you to draw the
layout of an IC, look at cross - sections, perform DRC (design rule check) , and generate a Netlist of your
layout so thatyou can perform LVS (layout versus schematic) using a differenttool.

SCHEMATIC OF INVERTER
NETLIST GENERATED BY S-EDIT:

NETLIST FOR SCHEMATIC:

* SPICE export by: S-Edit 15.02

* Exporttime: Thu Mar 19 10:52:232015
Wed Apr 10 15:19:172013
* Design: not
* Cell: not
* View: view0
* Exportas: top-levelcell
* Exportmode: hierarchical
* Exclude empty cells: no
* Exclude .model:yes
* Exclude.end: no
* Excludesimulatorcommands: no
* Expandpaths: yes
* Wraplines: 80 characters
* Rootpath: D:\SRI\not
* Exclude global pins:no
* Excludeinstancelocations: no
* Control property name:SPICE

********* Simulation Settings - General Section *********

*-------- Devices With SPICE.ORDER == 0.0 --------

***** Top Level *****

MNMOS_2_5v_1 Out In Gnd Gnd NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u
+$ $x=3793 $y=3200 $w=414 $h=600
MPMOS_2_5v_1 Out In Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u
+$ $x=3793 $y=4100 $w=414 $h=600

********* Simulation Settings - Analysis Section *********

.end
Layout of a Inverter

NETLIST FOR LAYOUT:

******************************************************************************
* SPICE netlist generated by HiPer Verify's NetListExtractor
*
* Extract DATE/Time: Thu Mar 19 11:20:482015
*L-EditVersion: L-Edit Win3215.02.20100805.07:58:22
*
* Rule SetName:
* TDBFileName: D:\NewFolder\CMOSINV-LSPICE.tdb
* CommandFile: C:\Documents and Settings\placement\My Documents\Tanner
EDA\TannerToolsv15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.ext
* CellName: Cell0
* WriteFlat: YES
******************************************************************************
M1OUT1GND_GND_NMOS25l=2.5e-007w=2.5e-006ad=2.5e-012as=2.5e-012pd=7e-006
ps=7e-006 $(31 21.5 31.2524)
M2OUT1VDDVDDPMOS25l=2.5e-007w=4.8e-006ad=4.8e-012as=4.8e-012pd=1.16e-005
ps=1.16e-005 $(31 27 31.2531.8)
* Devicecount
*M(NMOS25) 1
*M(PMOS25) 1
* Number of devices:2
* Number of nodes: 4
**********************************

PROCEDURE
Export a SPICE Netlist

Exporting a SPICE Netlist is a good idea in order to verify that you have entered the schematic correctly.
Also, this Netlist will be used later when performing a “Layout versus Schematic (LVS)” check.

With the schematic open, use the pull down menus to perform: -

File → Export → Export SPICE. - Browse to your design directory and give the file

name “file name.spc”. - Click “OK”

Launch L-edit,

1. Start → All Programs → Tanner EDA → Tanner Tools v15.0 → L-Editv15.0

2. Create a new layout design: - File – New - select “Layout” - under “Copy TDB…”, browseto:
\
TannerEDA\TannerToolsv15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm_TechSetup.td
b

- Click“OK”

When you copy in the Generic_025.tbd files, it loads all of the layer definitions for the 0.25um process
and the design rule information. On the left, you should see a set of layers for this technology that can be
used to create devices.

3. Verify the technology rule options &setupgrid

- Setup – Design

Now setup the grid. Click on the “Grid” tab. Since we are using a 0.25um grid, let’s put our major grid 0.25
microns and snap grid at 0.125um. Then we will put our minor grid at 0.05 microns.

4. select the layers and contact from Layer palette, draw the devices and inter connection with
proper measurement.

5. Click on DRC setup icon and check DRC standard rulesonly

6. Run DRC to make sure your dimensions are not violating any design rules - Click onthe
DRC button in the upper left corner of the screen (little green play arrow). If everything checks out, you
should a pop up that says it passed DRC.

Extract a SPICE Netlist of Layout

Using the pull down menus, perform: - Tools → Extract setup You will need to provide an extraction file
for this process (*.ext) - Browse to “..\Generic_025_Kit\Generic_025.ext” You will want to provide a
SPICE output file. Browse to your design directory .
The output waveform is

Result:
The layout of CMOS inverter using L – Edit was drawn and was simulated