RFG30P05, RFP30P05, RF1S30P05SM

Data Sheet January 2002

30A, 50V, 0.065 Ohm, P-Channel Power Features

MOSFETs • 30A, 50V
These are P-Channel power MOSFETs manufactured
• rDS(ON) = 0.065Ω
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits, gives • Temperature Compensating PSPICE® Model
optimum utilization of silicon, resulting in outstanding • Peak Current vs Pulse Width Curve
performance. They were designed for use in applications
such as switching regulators, switching converters, motor • UIS Rating Curve
drivers, and relay drivers. These transistors can be • 175oC Operating Temperature
operated directly from integrated circuits.
• Related Literature
Formerly developmental type TA09834. - TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER PACKAGE BRAND
D
RFG30P05 TO-247 RFG30P05

RFP30P05 TO-220AB RFP30P05

G
RF1S30P05SM TO-263AB F1S30P05

NOTE: When ordering, use the entire part number. Add the suffix 9A to S
obtain the TO-263AB variant in tape and reel, i.e., RF1S30P05SM9A.

Packaging
JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE SOURCE
DRAIN DRAIN
GATE
GATE DRAIN
DRAIN (FLANGE)
(BOTTOM
SIDE METAL)

JEDEC TO-263AB

GATE DRAIN
(FLANGE)
SOURCE

©2002 Fairchild Semiconductor Corporation RFG30P05, RFP30P05, RF1S30P05SM Rev. B

 RFG30P05, RFP30P05, RF1S30P05SM

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified

RFG30P05, RFP30P05
RF1S30P05SM UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS -50 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR -50 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 30 A
Pulsed Drain Current (Note 3) (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Refer to Peak Current Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 120 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 W/oC
Single Pulse Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 150oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V -50 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA -2 - -4 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - -1 µA
VDS = 0.8 x Rated BVDSS, TC = 150oC - - -25 µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance rDS(ON) ID = 30A, VGS = -10V (Figure 9) - - 0.065 Ω
Turn-On Time t(ON) VDD = -25V, ID = 15A, - - 80 ns
RL = 1.67Ω, VGS = -10V,
Turn-On Delay Time td(ON) - 15 - ns
RG = 6.25Ω
Rise Time tr (Figure 13) - 23 - ns
Turn-Off Delay Time td(OFF) - 28 - ns
Fall Time tf - 18 - ns
Turn-Off Time t(OFF) - - 100 ns
Total Gate Charge Qg(TOT) VGS = 0 to -20V VDD = -40V, - 140 170 nC
ID = 30A, RL = 1.33Ω,
Gate Charge at -10V Qg(-10) VGS = 0 to -10V - 70 85 nC
IG(REF) = 1.6mA
Threshold Gate Charge Qg(TH) VGS = 0 to -2V - 5.5 6.6 nC
Input Capacitance CISS VDS = -25V, VGS = 0V - 3200 - pF
f = 1MHz
Output Capacitance COSS - 800 - pF
(Figure 12)
Reverse Transfer Capacitance CRSS - 175 - pF
Thermal Resistance, Junction to Case RθJC - - 1.25 oC/W

Thermal Resistance, Junction to Ambient RθJA TO-220, TO-263 - - 62 oC/W

TO-247 - - 30 oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) VSD ISD = -30A - - -1.5 V

Reverse Recovery Time trr ISD = -30A, dISD/dt = -100A/µs - - 150 ns

NOTES:
2. Pulsed: pulse duration = 300µs max, duty cycle = 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).

©2002 Fairchild Semiconductor Corporation RFG30P05, RFP30P05, RF1S30P05SM Rev. B

 RFG30P05, RFP30P05, RF1S30P05SM

Typical Performance Curves Unless Otherwise Specified

1.2 -40
POWER DISSIPATION MULTIPLIER

1.0

ID , DRAIN CURRENT (A)

-30
0.8

0.6 -20

0.4
-10
0.2

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

1
THERMAL IMPEDANCE

0.5
ZθJC, NORMALIZED

0.2
PDM
0.1 0.1

0.05 t1
t2
0.02
NOTES:
0.01 DUTY FACTOR: D = t1/t2
SINGLE PULSE PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

-200 -500
TC = 25oC
VGS = -20V FOR TEMPERATURES ABOVE 25oC
-100 100µs DERATE PEAK CURRENT
VGS = -10V
CAPABILITY AS FOLLOWS:
IDM , PEAK CURRENT (A)
ID , DRAIN CURRENT (A)

175 – T C
I = I 25  ---------------------
1ms  150 
-100

-10 10ms
OPERATION IN THIS
AREA MAY BE 100ms TRANSCONDUCTANCE
LIMITED BY rDS(ON)
MAY LIMIT CURRENT
VDSS MAX = -50V DC IN THIS REGION
TC = 25oC
-1 -10
-1 -10 -100 10-5 10-4 10-3 10-2 10-1 100 101
VDS , DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (s)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

©2002 Fairchild Semiconductor Corporation RFG30P05, RFP30P05, RF1S30P05SM Rev. B

 RFG30P05, RFP30P05, RF1S30P05SM

Typical Performance Curves Unless Otherwise Specified (Continued)

-100 -75
VGS = -20V
STARTING TJ = 25oC
IAS , AVALANCHE CURRENT (A)

VGS = -10V
-60 VGS = -8V

ID, DRAIN CURRENT (A)

VGS = -7V
-45
PULSE DURATION = 80µs
-10 DUTY CYCLE = 0.5% MAX
STARTING TJ = 150oC
TC = 25oC
-30

VGS = -6V
If R = 0
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) -15
VGS = -5V
If R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] VGS = -4.5V
-1 0
0.1 1 10 100 0 -2 -4 -6 -8 -10
tAV , TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V)

NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS

-75 2
IDS(ON), DRAIN TO SOURCE CURRENT (A)

PULSE DURATION = 80µs PULSE DURATION = 80µs

NORMALIZED DRAIN TO SOURCE
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
VDD = -15V VGS = -10V, ID = 30A
-60
-55oC 1.5
25oC
ON RESISTANCE

175oC
-45
1

-30

0.5
-15

0 0
0 -2 -4 -6 -8 -10 -80 -40 0 40 80 120 160 200
VGS, GATE TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (oC)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2 2
VGS = VDS, ID =-250µA ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE

1.5 1.5
THRESHOLD VOLTAGE
NORMALIZED GATE

1 1

0.5 0.5

0
0
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ , JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
JUNCTION TEMPERATURE VOLTAGE vs JUNCTION TEMPERATURE

©2002 Fairchild Semiconductor Corporation RFG30P05, RFP30P05, RF1S30P05SM Rev. B

 RFG30P05, RFP30P05, RF1S30P05SM

Typical Performance Curves Unless Otherwise Specified (Continued)

4000 -50 -10

GATE

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS, GATE TO SOURCE VOLTAGE (V)

VDD = BVDSS SOURCE VDD = BVDSS
CISS VOLTAGE
C, CAPACITANCE (pF)

3000 -37.5 -7.5

RL = 1.67Ω
IG(REF) = 1.6mA
VGS = 0V, f = 1MHz
VGS = -10V
CISS = CGS + CGD
2000 -25 -5
CRSS = CGD
COSS ≈ CDS + CGS
0.75 BVDSS
0.50 BVDSS
1000 -12.5 -2.5
COSS 0.25 BVDSS

DRAIN SOURCE VOLTAGE

CRSS
0 0 0
0 -5 -10 -15 -20 -25 IG(REF) IG(REF)
20 t, TIME (µs) 80
VDS , DRAIN TO SOURCE VOLTAGE (V) IG(ACT) IG(ACT)

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT

Test Circuits and Waveforms

VDS
tAV

L 0

VARY tP TO OBTAIN
REQUIRED PEAK IAS RG
-
VDD
+

0V DUT VDD
tP IAS
VGS
VDS
IAS tP
0.01Ω
BVDSS

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)

VDS tr tf
RL 0
10% 10%

VGS
VDS
- 90% 90%
VDD
VGS
VGS + 0
DUT 10%
RGS
50% 50%
PULSE WIDTH
90%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

©2002 Fairchild Semiconductor Corporation RFG30P05, RFP30P05, RF1S30P05SM Rev. B

 RFG30P05, RFP30P05, RF1S30P05SM

Test Circuits and Waveforms (Continued)

VDS
VDS
RL Qg(TH)
0

VGS = -2V
VGS
- -VGS VGS = -10V
VDD
+ Qg(-10)

DUT VGS = -20V

VDD
IG(REF)
Qg(TOT)

0
IG(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

©2002 Fairchild Semiconductor Corporation RFG30P05, RFP30P05, RF1S30P05SM Rev. B

 RFG30P05, RFP30P05, RF1S30P05SM

PSPICE Electrical Model

.SUBCKT RFP30P05 2 1 3;
REV 8/21/94

CA 12 8 3.23e-9 ESG
CB 15 14 3.23e-9 - + 5 DRAIN
CIN 6 8 3.08e-9 8 2
10
6 LDRAIN
DBODY 5 7 DBDMOD
RSCL2 RSCL1
DBREAK 7 11 DBKMOD
+ 51 EBREAK +
DPLCAP 10 6 DPLCAPMOD
5 17
ESCL
51 18
EBREAK 5 11 17 18 -77.3 50 -
EDS 14 8 5 8 1 11
DPLCAP RDRAIN DBODY
EGS 13 8 6 8 1
ESG 5 10 8 6 1 16
VTO +
EVTO 20 6 8 18 1 -
MOS2
EVTO 21
GATE 20 + 18 -
9 6
IT 8 17 1 1 MOS1
8 DBREAK
LGATE RGATE
LDRAIN 2 5 1e-9 RIN CIN
LGATE 1 9 4.92e-9 LSOURCE
RSOURCE
LSOURCE 3 7 4.60e-9 8 7
3
SOURCE
MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01 S1A S2A
12 13 14 15 RBREAK
17 18
RBREAK 17 18 RBKMOD 1 8 13
RDRAIN 50 16 RDSMOD 39.85e-3 S1B S2B RVTO
RGATE 9 20 2.34 13 CB 19
RIN 6 8 1e9 CA 14 IT
+ +
RSCL1 5 51 RSCLMOD 1e-6 VBAT
EGS 6 EDS 6
RSCL2 5 50 1e3 +
8 8
RSOURCE 8 7 RDSMOD 2.56e-3 - -
RVTO 18 19 RVTOMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 -0.81

ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/114,5))}

.MODEL DBDMOD D (IS=4.7e-13 RS=1.31e-2 TRS1=1.39e-4 TRS2=-4.77e-6 CJO=2.85e-9 TT=8.81e-8)

.MODEL DBKMOD D (RS=2.23e-1 TRS1=1.97e-3 TRS2=-2.37e-5)
.MODEL DPLCAPMOD D (CJO=0.78e-9 IS=1e-30 N=10)
.MODEL MOSMOD PMOS (VTO=-3.75 KP=10.83 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=9.08e-4 TC2=-1.72e-6)
.MODEL RDSMOD RES (TC1=5.01e-3 TC2=1.02e-5)
.MODEL RSCLMOD RES (TC1=2.09e-3 TC2=5.88e-7)
.MODEL RVTOMOD RES (TC1=-2.99e-3 TC2=1.40e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.4 VOFF=1.4)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.4 VOFF=3.4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.2 VOFF=-3.8)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.8 VOFF=1.2)

.ENDS

NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; authors, William J. Hepp and C. Frank Wheatley.

©2002 Fairchild Semiconductor Corporation RFG30P05, RFP30P05, RF1S30P05SM Rev. B

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™ FAST  OPTOLOGIC™ SMART START™ VCX™
Bottomless™ FASTr™ OPTOPLANAR™ STAR*POWER™
CoolFET™ FRFET™ PACMAN™ Stealth™
CROSSVOLT™ GlobalOptoisolator™ POP™ SuperSOT™-3
DenseTrench™ GTO™ Power247™ SuperSOT™-6
DOME™ HiSeC™ PowerTrench  SuperSOT™-8
EcoSPARK™ ISOPLANAR™ QFET™ SyncFET™
E2CMOSTM LittleFET™ QS™ TinyLogic™
EnSignaTM MicroFET™ QT Optoelectronics™ TruTranslation™
FACT™ MicroPak™ Quiet Series™ UHC™
FACT Quiet Series™ MICROWIRE™ SILENT SWITCHER  UltraFET 
STAR*POWER is used under license
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
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the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4
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