LIST OF CONTENTS

CHAPTER NO CONTENTS PAGE NO

ABSTRACT (i)

LIST OF TABLE (ii)

LIST OF FIGURE (iii)

1. INTRODUCTION
2. BLOCK DIAGRAM
2.1 BLOCK DIAGRAM EXPLANATION
3. CIRCUIT DIAGRAM
4. SOFTWARE REQUIREMENT
4.1 KEIL COMPILER
4.1.1 FEATURES
4.2 EMBEDDED C
5. HARD WARE REQUIREMENT
5.1 8051 MIC ROCONTROLLER
5.2 POWER SUPPLY
5.3 COMPARATOR
5.4 FIRE SENSOR
5.5 GAS SENSOR
5.6 BLUETOOTH
6. ADVANTAGE
7. APPLICATION
8. CONCLUSION
9. REFERENCE

1
 ABSTRACT

The objective of this project is to provide security to the home, and this project can
operate efficiently without human interference by using a user friendly Bluetooth technology.
More over the security is handled by using two types of sensors namely gas sensor, fire sensor.
The sensor will keep on monitoring if there any abnormalities in the parameter and the data will
be transferred to the PC through Bluetooth. The parameter value can also be uploaded to the
internet from the PC. The abnormalities will also be intimated through the Bluetooth.

2
LIST OF TABLE

3
LIST OF FIGURE

4
 INTRODUCTION

The Embedded technology plays a major role in integrating the various functions
associated with it. This needs to tie up the various sources of the department in a closed loop
system. This project puts forth the first step in achieving the desired target. With the advent in
technology, the existing systems are developed to have in built intelligence. There is several
security systems provided in the earlier days but these cannot be handled easily. So we are in
need of user friendly procedure to provide security system. In our proposed system we are
incorporating gas and temperature sensors in order to monitor the remote home through online
update.

5
BLOCK DIAGRAM:

Transmitter Unit:

Power
Supply

C
Gas
Gas O
Sensor
Sensor M 8051
P
A Micro
Fire
Fire R
Sensor
Sensor A Controller
T
O
R

Receiver Unit

PC with
WEB

6
BLOCK DIAGRAM EXPLANATION:

The system is proposed in such a passion to provide security to the home with the help of
an user friendly technology – Bluetooth. For security purpose we are using Gas sensor
and Temperature sensor that are connected to the 8051 microcontroller through
comparator. The sensor will keep on monitoring is there any abnormalities in the
parameter and the acquired data will be transferred to the PC through Bluetooth. The
parameter value can also be uploaded to the internet from the PC. The abnormalities will
also be intimated through the Bluetooth.

7
4. SOFTWARE REQUIREMENT:

4.1 KEIL C Compiler

The Kiel C51 C Compiler for the 8051 microcontroller is the most popular 8051 C compiler in
the world. It provides more features than any other 8051 C compiler available today.

The C51 Compiler allows you to write 8051 microcontroller applications in C that, once
compiled, have the efficiency and speed of assembly language. Language extensions in the C51
Compiler give you full access to all resources of the 8051.

The C51 Compiler translates C source files into relocatable object modules which contain full
symbolic information for debugging with the µVision Debugger or an in-circuit emulator. In
addition to the object file, the compiler generates a listing file which may optionally include
symbol table and cross reference information.

4.1.1 Features
 Nine basic data types, including 32-bit IEEE floating-point,
 Flexible variable allocation with bit, data, b data, I data, x data, and p data memory types,
 Interrupt functions may be written in C,
 Full use of the 8051 register banks,
 Complete symbol and type information for source-level debugging,
 Use of AJMP and ACALL instructions,
 Bit-addressable data objects,
 Built-in interface for the RTX51 Real-Time Kernel,
 Support for dual data pointers on Atmel, AMD, Cypress, Dallas Semiconductor, Infineon,
Philips, and Triscend microcontrollers,
 Support for the Philips 8xC750, 8xC751, and 8xC752 limited instruction sets,

Support for the Infineon 80C517 arithmetic unit

8
4.2 EMBEDDED C

The C programming language is perhaps the most popular programming language for
programming embedded systems we mentioned other popular programming languages).

Most C programmers are spoiled because they program in environments where not only is there
a standard library implementation, but there are frequently a number of other libraries available
for use. The cold fact is, that in embedded systems, there rarely are many of the libraries that
programmers have grown used to, but occasionally an embedded system might not have a
complete standard library, if there is a standard library at all. Few embedded systems have
capability for dynamic linking, so if standard library functions are to be available at all, they
often need to be directly linked into the executable. Oftentimes, because of space concerns, it is
not possible to link in an entire library file, and programmers are often forced to "brew their
own" standard c library implementations if they want to use them at all. While some libraries are
bulky and not well suited for use on microcontrollers, many development systems still include
the standard libraries which are the most common for C programmers.

C remains a very popular language for micro-controller developers due to the code efficiency
and reduced overhead and development time. C offers low-level control and is considered more
readable than assembly. Many free C compilers are available for a wide variety of development
platforms. The compilers are part of an IDEs with ICD support, breakpoints, single-stepping and
an assembly window. The performance of C compilers has improved considerably in recent
years, and they are claimed to be more or less as good as assembly, depending on who you ask.
Most tools now offer options for customizing the compiler optimization. Additionally, using C
increases portability, since C code can be compiled for different types of processors.

5. HARDWARE REQUIREMENT

5.1 MICROCONTROLLER

The generic 8031 architecture sports a Harvard architecture, which contains two separate buses
for both program and data. So, it has two distinctive memory spaces of 64K X 8 size for both
program and data. It is based on an 8 bit central processing unit with an 8 bit Accumulator and
another 8 bit B register as main processing blocks. Other portions of the architecture include few

9
8 bit and 16 bit registers and 8 bit memory locations.Each 8031 device has some amount of data
RAM built in the device for internal processing. This area is used for stack operations and
temporary storage of data.This base architecture is supported with onchip peripheral functions
like I/O ports, timers/counters, versatile serial communication port. So it is clear that this 8031
architecture was designed to cater many real time embedded needs.

The following list gives the features of the 8051 architecture:

 Optimized 8 bit CPU for control applications.

 Extensive Boolean processing capabilities.
 64K Program Memory address space.
 64K Data Memory address space.
 128 bytes of onchip Data Memory.
 32 Bi-directional and individually addressable I/O lines.
 Two 16 bit timer/counters.
 Full Duplex UART, On-chip clock oscillator.
 6-source / 5-vector interrupt structure with priority levels.
Now you may be wondering about the non mentioning of memory space meant for the program
storage, the most important part of any embedded controller. Originally this 8031 architecture
was introduced with onchip, ‘one time programmable’ version of Program Memory of size 4K X
8. Intel delivered all these microcontrollers (8051) with user’s program fused inside the device.
The memory portion was mapped at the lower end of the Program Memory area. But, after
getting devices, customers couldn’t change any thing in their program code, which was already
made available inside during device fabrication.

10
 Figure 1 - Block Diagram of the 8031 Core

So, very soon Intel introduced the 8031 devices (8751) with re-programmable type of Program
Memory using built-in EPROM of size 4K X 8. Like a regular EPROM, this memory can be re-
programmed many times. Later on Intel started manufacturing these 8031 devices without any
onchip Program Memory.Now I go ahead giving more information on the important functional
blocks of the 8031.

5.1.1 DIFFERENCES BETWEEN MICROCONTROLLER AND MICROPROCESSOR:

 Microprocessors have many instructions for moving data from external memory to internal
memory. But microcontrollers have a few such instructions.
 Microprocessors have less bit handling instructions, but microcontrollers have many such
instructions.
 Microprocessors are concerned with rapid movement of code and data from external
memory. But Microcontroller is concerned with that of bits within the chip.
 Of course Microprocessor needs additional chips for memory, parallel port, timer etc and
microcontroller needs no such external ports.

11
 8031

Figure 2 - 8031 Microcomputer Pinout Diagram

Figure 3 - 8031 Microcomputer logic symbol

12
5.1.2 OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can
be configured for use as an onchip oscillator, as shown in Figure 1. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no
requirements on the duty cycle of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by two flip-flop, but minimum and maximum voltage high
and low time specifications must be observed.

5.1.3 8051 CLOCK

 8051 has an on-chip oscillator

 It needs an external crystal
 Crystal decides the operating frequency of the 8051

5.1.4 IDLE MODE

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special functions
registers remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to
internal RAM in this event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction

13
following the one that invokes Idle should not be one that writes to a port pin or to external
memory.

5.1.5 POWER DOWN MODE

In the power down mode the oscillator is stopped, and the instruction that invokes power down is
the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the power down mode is terminated. The only exit from power down is a hardware
reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be
activated before VCC is restored to its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.

5.1.6 8051 RESET

 RESET is an active High input

 When RESET is set to High, 8051 goes back to the poweron state
 Power-On Reset
 Push PB and active High on RST
 Release PB, Capacitor discharges and RST goes low
 RST must stay high for a min of 2 machine cycles

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5.1.7 CENTRAL PROCESSING UNIT

The CPU is the brain of the microcontrollers reading user’s programs and executing the expected
task as per instructions stored there in. Its primary elements are an 8 bit Arithmetic Logic Unit
(ALU), Accumulator (Acc), few more 8 bit registers, B register, Stack Pointer (SP), Program
Status Word (PSW) and 16 bit registers, Program Counter (PC) and Data Pointer Register
(DPTR).

5.1.8 THE ACCUMULATOR

If worked with any other assembly language you will be familiar with the concept of an
accumulator register. The Accumulator, as its name suggests, is used as a general register to
accumulate the results of a large number of instructions. It can hold an 8-bit (1-byte) value and is
the most versatile register the 8052 has due to the sheer number of instructions that make use of
the accumulator. More than half of the 8052ís 255 instructions manipulate or use the
Accumulator in some way.

For example, if you want to add the number 10 and 20, the resulting 30 will be stored in the
Accumulator. Once you have a value in the Accumulator you may continue processing the value
or you may store it in another register or in memory.

5.1.9 THE "R" REGISTERS

The "R" registers are sets of eight registers that are named R0, R1, through R7. These registers
are used as auxiliary registers in many operations. To continue with the above example, perhaps
you are adding 10 and 20. The original number 10 may be stored in the Accumulator whereas the
value 20 may be stored in, say, register R4. To process the addition you would execute the
command:As mentioned earlier, there are four sets of ‘R’ registers, register bank 0, 1, 2, and 3.
When the 8052 is first powered up, register bank 0 (addresses 00h through 07h) is used by
default. In this case, for example, R4 is the same as Internal RAM address 04h. However, your
program may instruct the 8052 to use one of the alternate register banks; i.e., register banks 1, 2,
or 3. In this case, R4 will no longer be the same as Internal RAM address 04h. For example, if
your program instructs the 8052 to use register bank 1, register R4 will now be synonymous with

15
Internal RAM address 0Ch. If you select register bank 2, R4 is synonymous with 14h, and if you
select register bank 3 it is synonymous with address 1Ch. The concept of register banks adds a
great level of flexibility to the 8052, especially when dealing with interrupts (we'll talk about
interrupts later). However, always remember that the register banks really reside in the first 32
bytes of Internal RAM.

5.1.10 THE "B" REGISTER

The "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit (1-byte)
value. The "B" register is only used implicitly by two 8052 instructions: MUL AB and DIV AB.
Thus, if you want to quickly and easily multiply or divide A by another number, you may store
the other number in "B" and make use of these two instructions.Aside from the MUL and DIV
instructions, the "B" register is often used as yet another temporary storage register much like a
ninth "R" register.

5.1.11 THE PROGRAM COUNTER (PC)

The Program Counter (PC) is a 2-byte address that tells the 8052 where the next instruction to
execute is found in memory. When the 8052 is initialized PC always starts at 0000h and is
incremented each time an instruction is executed. It is important to note that PC isn’t always
incremented by one. Since some instructions are 2 or 3 bytes in length the PC will be
incremented by 2 or 3 in these cases.The Program Counter is special in that there is no way to
directly modify its value. That is to say, you can’t do something like PC=2430h. On the other
hand, if you execute LJMP 2430h you’ve effectively accomplished the same thing.It is also
interesting to note that while you may change the value of PC (by executing a jump instruction,
etc.) there is no way to read the value of PC. That is to say, there is no way to ask the 8052
"What address are you about to execute?" As it turns out, this is not completely true: There is one
trick that may be used to determine the current value of PC.

5.1.12 THE DATA POINTER (DPTR)

The Data Pointer (DPTR) is the 8052ís only user-accessible 16-bit (2-byte) register. The
Accumulator, "R" registers, and "B" register are all 1-byte values. The PC just described is a 16-
bit value but isn’t directly user-accessible as a working register.DPTR, as the name suggests, is

16
used to point to data. It is used by a number of commands that allow the 8052 to access external
memory. When the 8052 accesses external memory it accesses the memory at the address
indicated by DPTR.

While DPTR is most often used to point to data in external memory or code memory, many
developers take advantage of the fact that it’s the only true 16-bit register available. It is often
used to store 2-byte values that have nothing to do with memory locations.

5.1.13 THE STACK POINTER (SP)

The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte) value. The
Stack Pointer is used to indicate where the next value to be removed from the stack should be
taken from. When you push a value onto the stack, the 8052 first increments the value of SP and
then stores the value at the resulting memory location. When you pop a value off the stack, the
8052 returns the value from the memory location indicated by SP, and then decrements the value
of SP.This order of operation is important. When the 8052 is initialized SP will be initialized to
07h. If you immediately push a value onto the stack, the value will be stored in Internal RAM
address 08h. This makes sense taking into account what was mentioned two paragraphs above:
First the 8051 will increment the value of SP (from 07h to 08h) and then will store the pushed
value at that memory address (08h).SP is modified directly by the 8052 by six instructions:
PUSH, POP, ACALL, LCALL, RET, and RETI. It is also used intrinsically whenever an
interrupt is triggered (more on interrupts later. Don’t worry about them for now!).

5.1.14 INPUT / OUTPUT PORTS

The 8031’s I/O port structure is extremely versatile and flexible. The device has 32 I/O pins
configured as four eight bit parallel ports (P0, P1, P2 and P3). Each pin can be used as an input
or as an output under the software control. These I/O pins can be accessed directly by memory
instructions during program execution to get required flexibility.These port lines can be operated
in different modes and all the pins can be made to do many different tasks apart from their
regular I/O function executions. Instructions, which access external memory, use port P0 as a
multiplexed address/data bus. At the beginning of an external memory cycle, low order 8 bits of

17
the address bus are output on P0. The same pins transfer data byte at the later stage of the
instruction execution.

Also, any instruction that accesses external Program Memory will output the higher order byte
on P2 during read cycle. Remaining ports, P1 and P3 are available for standard I/O functions.
But all the 8 lines of P3 support special functions: Two external interrupt lines, two counter
inputs, serial port’s two data lines and two timing control strobe lines are designed to use P3 port
lines. When you don’t use these special functions, you can use corresponding port lines as a
standard I/O.Even within a single port, I/O operations may be combined in many ways. Different
pins can be configured as input or outputs independent of each other or the same pin can be used
as an input or as output at different times. You can comfortably combine I/O operations and
special operations for Port 3 lines.

5.1.15 TIMERS / COUNTERS

8031 has two 16 bit Timers/Counters capable of working in different modes. Each consists of a
‘High’ byte and a ‘Low’ byte which can be accessed under software. There is a mode control
register and a control register to configure these timers/counters in number of ways.These timers
can be used to measure time intervals, determine pulse widths or initiate events with one
microsecond resolution upto a maximum of 65 millisecond (corresponding to 65, 536 counts).
Use software to get longer delays. Working as counter, they can accumulate occurrences of
external events (from DC to 500KHz) with 16 bit precision.

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5.1.16 INTERRUPTS

The 8031 has five interrupt sources: one from the serial port when a transmission or reception
operation is executed; two from the timers when overflow occurs and two come from the two
input pins INT0, INT1. Each interrupt may be independently enabled or disabled to allow polling
on same sources and each may be classified as high or low priority. A high priority source can
override a low priority service routine. These options are selected by interrupt enable and priority
control registers, IE and IP. When an interrupt is activated, then the program flow completes the
execution of the current instruction and jumps to a particular program location where it finds the
interrupt service routine. After finishing the interrupt service routine, the program flows return to
back to the original place. The Program Memory address, 0003H is allotted to the first interrupt
and next seven bytes can be used to do any task associated with that interrupt.

Interrupt Source Service routine starting address

External 0 0003H

Timer/Counter 0 000BH

External 1 0013H

19
Timer/counter 1 001BH

Serial port 0023H

5.1.17 SERIAL PORT

Each 8031 microcomputer contains a high speed full duplex (means you can simultaneously use
the same port for both transmitting and receiving purposes) serial port which is software
configurable in 4 basic modes: 8 bit UART; 9 bit UART; Interprocessor Communications link
or as shift register I/O expander. For the standard serial communication facility, 8031 can be
programmed for UART operations and can be connected with regular personal computers,
teletype writers, modem at data rates between 122 bauds and 31 kilobauds. Getting this facility is
made very simple using simple routines with option to select even or odd parity. You can also
establish a kind of Interprocessor communication facility among many microcomputers in a
distributed environment with automatic recognition of address/data.Apart from all above, you
can also get super fast I/O lines using low cost simple TTL or CMOS shift registers.

5.1.18 8051 PIN FUNCTIONS

I/O PORTS (P0, P1, P2, P3)

Of the 40 pins of the typical 8052, 32 of them are dedicated to I/O lines that have a one-to-one
relation with SFRs P0, P1, P2, and P3. The developer may raise and lower these lines by writing
1s or 0s to the corresponding bits in the SFRs. Likewise, the current state of these lines may be
read by reading the corresponding bits of the SFRs.

All of the ports have internal pull-up resistors except for port 0.

PORT 0

Port 0 is dual-function in that it in some designs port 0ís I/O lines are available to the developer
to access external devices while in other designs it is used to access external memory. If the
circuit requires external RAM or ROM, the microcontroller will automatically use port 0 to clock
in/out the 8-bit data word as well as the low 8 bits of the address in response to a MOVX
instruction and port 0 I/O lines may be used for other functions as long as external RAM isn’t
being accessed at the same time. If the circuit requires external code memory, the

20
microcontroller will automatically use the port 0 I/O lines to access each instruction that is to be
executed. In this case, port 0 cannot be utilized for other purposes since the state of the I/O lines
are constantly being modified to access external code memory.Note that there are no pull-up
resistors on port 0, so it may be necessary to include your own pull-up resistors depending on the
characteristics of the parts you will be driving via port 0.

PORT 1

Port 1 consists of 8 I/O lines that you may use exclusively to interface to external parts. Unlike
port 0, typical derivatives do not use port 1 for any functions themselves. Port 1 is commonly
used to interface to external hardware such as LCDs, keypads, and other devices. With 8052
derivatives, two bits of port 1 are optionally used as described forextended timer 2 functions.
These two lines are not assigned these special functions on 8051ís since 8051ís don’t have a
timer 2. Further, these lines can still be used for your own purposes if you don’t need these
features of timer 2.P1.0 (T2): If T2CON.1 is set (C/T2), then timer 2 will be incremented
whenever there is a 1-0 transition on this line. With C/T2 set, P1.0 is the clock source for timer 2.
P1.1 (T2EX): If timer 2 is in auto-reload mode and T2CON.3 (EXEN2) is set, a 1-0 transition on
this line will cause timer 2 to be reloaded with the auto-reload value. This will also cause the
T2CON.6 (EXF2) external flag to be set, which may cause an interrupt if so enabled.

PORT 2

Like port 0, port 2 is dual-function. In some circuit designs it is available for accessing devices
while in others it is used to address external RAM or external code memory. When the MOVX
@DPTR instruction is used, port 2 is used to output the high byte of the memory address that is
to be accessed. In these cases, port 2 may be used to access other devices as long as the devices
are not being accessed at the same time a MOVX instruction is using port 2 to address external
RAM. If the circuit requires external code memory, the microcontroller will automatically use
the port 2 I/O lines to access each instruction that is to be executed. In this case, port 2 cannot be
utilized for other purposes since the state of the I/O lines are constantly being modified to access
external code memory.

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PORT 3

Port 3 consists entirely of dual-function I/O lines. While the developer may access all these lines
from their software by reading/writing to the P3 SFR, each pin has a pre-defined function that
the microcontroller handles automatically when configured to do so and/or when necessary. P3.0
(RXD): The UART/serial port uses P3.0 as the receive line. In circuit designs that will be using
the microcontroller’s internal serial port, this is the line into which serial data will be clocked.
Note that when interfacing an 8052 to an RS-232 port that you may not connect this line directly
to the RS-232 pin; rather, you must pass it through a part such as the MAX232 to obtain the
correct voltage levels. This pin is available for any use the developer may assign it if the circuit
has no need to receive data via the integrated serial port.P3.1 (TXD): The UART/serial port uses
P3.1 as the ‘transmit line.’ In circuit designs that will be using the microcontroller’s internal
serial port, this is the line that the microcontroller will clock out all data which is written to the
SBUF SFR. Note that when interfacing an 8052 to an RS-232 port that you may not connect this
line directly to the RS-232 pin; rather, you must pass it through a part such as the MAX232 to
obtain the correct voltage levels. This pin is available for any use the developer may assign it if
the circuit has no need to transmit data via the integrated serial port.P3.2 (-INT0): When so
configured, this line is used to trigger an ‘External 0 Interrupt.’ This may either be low-level
triggered or may be triggered on a 1-0 transition. Please see the chapter on interrupts for details.
This pin is available for any use the developer may assign it if the circuit does not need to trigger
an external 0 interrupt.P3.3 (-INT1): When so configured, this line is used to trigger an ‘External
1 Interrupt.’ This may either be low-level triggered or may be triggered on a 1-0 transition.
Please see the chapter on interrupts for details. This pin is available for any use the developer
may assign it if the circuit does not need to trigger an external 1 interrupt.P3.4 (T0): When so
configured, this line is used as the clock source for timer 0. Timer 0 will be incremented either
every instruction cycle that T0 is high or every time there is a 1-0 transition on this line,
depending on how the timer is configured. Please see the chapter on timers for details. This pin is
available for any use the developer may assign it if the circuit does not to control timer 0
externally.

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P3.5 (T1): When so configured, this line is used as the clock source for timer 1. Timer 1 will be
incremented either every instruction cycle that T1 is high or every time there is a 1-0 transition
on this line, depending on how the timer is configured. Please see the chapter on timers for
details. This pin is available for any use the developer may assign it if the circuit does not to
control timer 1 externally.P3.6 (-WR): This is external memory write strobe line. This line will
be asserted low by the microcontroller whenever a MOVX instruction writes to external RAM.
This line should be connected to the RAM’s write (-W) line. This pin is available for any use the
developer may assign it if the circuit does not write to external RAM using MOVX.P3.7 (-RD):
This is external memory write strobe line. This line will be asserted low by the microcontroller
whenever a MOVX instruction writes to external RAM. This line should be connected to the
RAM’s write (-W) line. This pin is available for any use the developer may assign it if the circuit
does not read from external RAM using MOVX.

5.1.19 OSCILLATOR INPUTS (XTAL1, XTAL2)

The 8052 is typically driven by a crystal connected to pins 18 (XTAL2) and 19 (XTAL1).
Common crystal frequencies are 11.0592Mhz as well as 12Mhz, although many newer
derivatives are capable of accepting frequencies as high as 40Mhz.While a crystal is the normal
clock source, this isn’t necessarily the case. A TTL clock source may also be attached to XTAL1
and XTAL2 to provide the microcontroller’s clock.

5.1.20 RESET LINE (RST)

Pin 9 is the master reset line for the microcontroller. When this pin is brought high for two
instruction cycles, the microcontroller is effectively reset. SFRs, including the I/O ports, are
restored to their default conditions and the program counter will be reset to 0000h. Keep in mind
that Internal RAM is not affected by a reset. The microcontroller will begin executing code at
0000h when pin 9 returns to a low state.

The reset line is often connected to a reset button/switch that the user may press to reset the
circuit. It is also common to connect the reset line to a watchdog IC or a supervisor IC (such as
MAX707). The latter is highly recommended for commercial and professional designs since
traditional resistor-capacitor networks attached to the reset line, while often sufficient for
students or hobbyists, are not terribly reliable.

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5.1.21 ADDRESS LATCH ENABLE (ALE)

The ALE at pin 30 is an output-only pin that is controlled entirely by the microcontroller and
allows the microcontroller to multiplex the low-byte of a memory address and the 8-bit data
itself on port 0. This is because, while the high-byte of the memory address is sent on port 2, port
0 is used both to send the lowbyte of the memory address and the data itself. This is
accomplished by placing the low-byte of the address on port 0, exerting ALE high to latch the
low-byte of the address into a latch IC (such as the 74HC573), and then placing the 8 data-bits
on port 0. In this way the 8052 is able to output a 16-bit address and an 8-bit data word with 16
I/O lines instead of 24.The ALE line is used in this fashion both for accessing external RAM
with MOVX @DPTR as well as for accessing instructions in external code memory. When your
program is executed from external code memory, ALE will pulse at a rate of 1/6th that of the
oscillator frequency. Thus if the oscillator is operating at 11.0592Mhz, ALE will pulse at a rate
of 1,843,200 times per second. The only exception is when the MOVX instruction is executed
one ALE pulse is missed in lieu of a pulse on WR or RD.

5.1.22 PROGRAM STORE ENABLE (-PSEN)

The Program Store Enable (PSEN) line at pin 29 is exerted low automatically by the
microcontroller whenever it accesses external code memory. This line should be attached to the
Output Enable (-OE) pin of the EPROM that contains your code memory.

PSEN will not be exerted by the microcontroller and will remain in a high state if your program
is being executed from internal code memory.

5.1.23 EXTERNAL ACCESS (-EA)

The External Access (-EA) line at pin 31 is used to determine whether the 8052 will execute
your program from external code memory or from internal code memory. If EA is tied high
(connected to +5V) then the microcontroller will execute the program it finds in internal/on-chip
code memory. If EA is tied low (to ground) then it will attempt to execute the program it finds in
the attached external code memory EPROM. Of course, your EPROM must be properly
connected for the microcontroller to be able to access your program in external code memory.

24
5.1.24 MEMORY ORGANIZATION

The 8051 architecture provides both onchip memory as well as off chip memory expansion
capabilities. It supports several distinctive ‘physical’ address spaces, functionally separated at the
hardware level by different addressing mechanisms, read and write controls signals or both:

 On chip Program Memory

 On chip Data Memory
 Off chip Program Memory
 Off chip Data Memory
 On chip Special Function Registers
The Program Memory area (EPROM incase of external memory or Flash/EPROM incase of
internal one) is extremely large and never lose information when the power is removed. Program
Memory is used for information needed each time power is applied: Initialization values,
Calibration data, Keyboard lookup tables etc along with the program itself. The Program
Memory has a 16 bit address and any particular memory location is addressed using the 16 bit
Program Counter and instructions which generate a 16 bit address.Onchip Data memory is
smaller and therefore quicker than Program Memory and it goes into a random state when power
is removed. Onchip RAM is used for variables which are calculated when the program is
executed.In contrast to the Program Memory, On chip Data Memory accesses need a single 8 bit
value (may be a constant or another variable) to specify a unique location. Since 8 bits are more
than sufficient to address 128 RAM locations, the onchip RAM address generating register is
single byte wide.Different addressing mechanisms are used to access these different memory
spaces and this greatly contributes to microcomputer’s operating efficiency.

The 64K byte Program Memory space consists of an internal and an external memory portion. If
the EA pin is held high, the 8051 executes out of internal Program Memory unless the address
exceeds 0FFFH and locations 1000H through FFFFH are then fetched from external Program

25
Memory. If the EA pin is held low, the 8031 fetches all instructions from the external Program
Memory. In either case, the 16 bit Program Counter is the addressing mechanism.

Figure 4 - Program Memory

The Data Memory address space consists of an internal and an external memory space. External
Data Memory is accessed when a MOVX instruction is executed.Apart from onchip Data
Memory of size 128/256 bytes, total size of Data Memory can be expanded upto 64K using
external RAM devices.

Total internal Data Memory is divided into three blocks:

Lower 128 bytes.

Higher 128 bytes

Special Function Register space.

Higher 128 bytes are available only in 8032/8052 devices.

26
Even though the upper RAM area and SFR area share same address locations, they are accessed
through different addressing modes. Direct addresses higher than 7FH access SFR memory space
and indirect addressing above 7FH access higher 128 bytes (in 8032/8052).

Figure 5 - Internal Data Memory

27
The next figure indicates the layout of lower 128 bytes. The lowest 32 bytes (from address 00H
to 1FH) are grouped into 4 banks of 8 registers. Program instructions refer these registers as R0
through R7. Program Status Word indicates which register bank is being used at any point of
time.

Figure 7 - Lower 128 Bytes of Internal RAM

The next 16 bytes above these register banks form a block of bit addressable memory space. The
instruction set of 8031 contains a wide range of single bit processing instructions and these
instructions can directly access the 128 bits of this area.The SFR space includes port latches,
timer and peripheral control registers. All the members of 8031 family have same SFR at the
same SFR locations. There are some 16 unique locations which can be accessed as bytes and as
bits.

28
5.1.25 COMMON MEMORY SPACE

The 8031’s Data Memory may not be used for program storage. So it means you can’t execute
instructions out of this Data Memory.But, there is a way to have a single block of offchip
memory acting as both Program and Data Memory. By gating together both memory read
controls (RD and PSEN) using an AND gate, a common memory read control signal can be
generated.In this arrangement, both memory spaces are tied together and total accessible memory
is reduced from 128 Kbytes to 64 Kbytes.The 8031 can read and write into this common memory
block and it can be used as Program and Data Memory.You can use this arrangement during
program development and debugging phase. Without taking Microcontroller off the socket to
program its internal ROM (EPROM/Flash ROM), you can use this common memory for frequent
program storage and code modifications.

5.1. 25 ADDRESSING MODES

8031’s assembly language instruction set consists of an operation mnemonic and zero to three
operands separated by commas. In two byte instructions the destination is specified first, and
then the source. Byte wide mnemonics like ADD or MOV use the Accumulator as a source
operand and also to receive the result.

The 8031 supports five types of addressing modes:

 Register Addressing
 Direct Addressing
 Register Indirect Addressing
 Immediate Addressing
 Index Addressing
5.1.26 REGISTER ADDRESSING

Register Addressing accesses the eight working registers (R0-R7) of the selected register bank.
The least significant three bits of the instruction opcode indicate which register is to be used for
the operation. One of the four banks of registers is to be predefined in the PSW before using
register addressing instruction. ACC, B, DPTR and CY, (the Boolean Accumulator) can also be
addressed in this mode.

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5.1.27 DIRECT ADDRESSING

Direct addressing can access any onchip variables or hardware register. To indicate the address
of the location, an additional byte is attached to the opcode. Depending on the highest order bit
of the direct address byte one of two physical memory space is selected.

DIRECT ADDRESSING

When the direct address range is between 0 and 127 (00H - 7FH) one of the 128 low order
onchip RAM location is accessed. All I/O ports, special function, control registers are assigned
between 128 and 255 (80H - FFH). When direct addressing indicates any location in this range,
corresponding hardware register is accessed.

This is the only method available for accessing I/O ports and special function registers.

5.1. 28REGISTER INDIRECT ADDRESSING

Register indirect addressing uses the contents of either R0 or R1 (in the pre selected register
bank) as a address pointer to locate in a 256 byte block (the lower 128 bytes of internal RAM in
8031 or 256 bytes in 8032) or the lower 256 bytes of external data memory. Note that the special
function registers are not accessible in this mode. Access to full 64K external data memory
address space is indicated by the 16 bit Data Pointer register, DPTR.Execution of PUSH and
POP instructions also involve indirect register addressing. The Stack Pointer indicates the correct
stack location anywhere in the internal RAM.

5.1.29 IMMEDIATE ADDRESSING

When a source operand is a constant rather than a variable, then the constant can be embedded
into the instruction itself. This kind of instructions take two bytes and first one specifies the
opcode and second byte gives the required constant.

5.1.30 INDEX ADDRESSING

Only the Program Memory can be accessed by this mode. This mode is intended for reading
lookup tables in the Program Memory. A 16 bit base register (either DPTR or the Program
Counter) points to the base of the lookup tables and the Accumulator carries the constant

30
indicating table entry number.The address of the exact location of the table is formed by adding
the Accumulator data to the base pointer.

5.1.31 INSTRUCTION SET

8031 architecture sports a powerful and versatile instruction set that enables the user to develop a
compact program. There is a facility to manipulate both byte data and 1 bit binary data. The table
gives complete information on the instruction set.

5.1.32 1 - DATA TRANSFER INSTRUCTIONS

The above table gives the instructions that can be used to move data around internal memory
spaces and the addressing modes that can be used with each one.The MOV <dest>, <src>
instruction allows data to be transferred between any two internal RAM locations without
disturbing the Accumulator. The upper 128 bytes of the data RAM can be accessed only by

31
indirect addressing and SFR space by direct addressing.In all 8031 devices, the stack resides in
onchip RAM, and grows upwards. The PUSH instruction first increments the Stack Pointer (SP),
then copies the byte into the stack. PUSH and POP use only direct addressing to identify the byte
being saved or restored. But the stack itself is accessed by indirect addressing using the SP
register. This means the stack can go into the upper 128 bytes if they are implemented but not
into SFR space.In devices that don’t have upper 128 bytes, if the SP points to anywhere in upper
128 bytes, pushed bytes are lost and popped bytes are indeterminate.The data transfer
instructions include a 16 bit MOV that can be used to initialize the Data Pointer (DPTR) for
lookup tables in Program Memory or for 16 bit external Data Memory accesses.The XCH A,
<byte> instruction causes the Accumulator and the addressed byte to exchange the data. The
XCHD A,@Ri instruction exchange only low nibble between the Accumulator and the addressed
byte.

5.1.33 2 - DATA TRANSFER IN EXTERNAL RAM

This following table gives possible data transfer operations in external data memory space. Only
indirect addressing can be used. The choice is whether to use a one byte address by @Ri, where
Ri can be either R0 or R1 of the selected register bank or a two byte address, @DPTR.

Note that in all external data RAM accesses the Accumulator is always either the destination or
source of data.The read and write strobes to external RAM are activated only during the
execution of a MOVX instruction. Normally these signals are inactive and infact if they are not
going to be used at all, then their pins are available as extra I/O lines.

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5.1.34 LOOKUP TABLES

This table shows the two instructions that are available for reading lookup tables from Program
Memory. Since they access only Program Memory, the lookup tables can only be read not
updated. The mnemonic MOVC is for ‘move constant’. If the table access is to external Program
Memory, then the read strobe is PSEN.The first MOVC instruction of the table can read a byte
from 256 entries, numbered 0 through 255. The number of the desired entry loaded into the
Accumulator and the Data Pointer is set up to point to beginning of the table.

The other MOVC instruction works with the Program Counter (PC). Hence PC acts as the table
base and the Accumulator should carry the table entry value.

5.1.35 ARITHMETIC INSTRUCTIONS

Note that most of the operations use Accumulator and any byte in the internal data memory
space can be increased or decrease without using Accumulator.

The instruction MUL AB multiplies the unsigned eight bit integer values held in the
Accumulator and B registers. The lower order byte of the 16 bit product is left in the
Accumulator and the higher order byte in B.

DIV AB divides the unsigned eight bit integer in the Accumulator by the unsigned eight bit
integer in the B register. The integer part of quotient stays with the Accumulator and the
remainder in the B register. The DAA instruction is for BCD arithmetic operations. In BCD
arithmetic, ADD and ADD C instructions should always be followed by a DAA operation, to

33
ensure that the result is also in BCD. The DAA operation produces a meaningful result only in
the second step when adding two BCD bytes.

5.1.36 LOGICAL INSTRUCTIONS

The following table gives the list of 8031’s logical instructions. The instructions that perform
Boolean operations (AND, OR, Exclusive OR, NOT) on bytes perform the operation on a bit by
bit basis. All of the logical instructions that are Accumulator specific execute in 1µs (using a
12MHz clock). Others take 2µs.

34
Boolean operations can be performed on any byte in the lower 128 internal data memory space
or the SFR space using direct addressing without having to use the Accumulator. If the operation
is in response to an interrupt, not using the Accumulator saves time and effort in the interrupt
service routine.

35
The Rotate instructions (RL A, RLC A, etc.) shift the Accumulator 1 bit to the left or right. For a
left rotation, the MSB rolls into the LSB position and for a right rotation, the LSB rolls into MSB
position.

The SWAP A instruction interchanges the high and low nibbles within the Accumulator. This is
a useful operation in BCD manipulation.

5.1.37 PROGRAM CONTROL – JUMPS, CALLS, AND RETURNS

LJMP (long jump) encodes a 16 bit address in the 2nd and 3rd instruction bytes. The destination
may be anywhere in the 64K byte Program Memory address space.The two byte AJMP
(Absolute jump) instruction encodes its destination using a 11 bit address which is embedded in
the instruction itself. Address bits 10 through 8 form a 3 bit field in the opcode and address bits 7
through 0 form a second byte.Address bits 15-11 remain unchanged from the incremented
contents of the PC, so AJMP can only be used when the destination is known to be within the
same 2K memory block.

5.1.38 JUMP INSTRUCTIONS

Following table gives a list of unconditional jumps.

36
As you can see, there are three types of jump operations:

SJMP – Short Jump

LJMP – Long Jump

AJMP – Absolute Jump

Basically these jump operations differ from each other by the way of address generation meant
for that jump operation.

SJMP (Short Jump) determines the destination with a Program Counter relative address
mentioned in the second byte. The CPU calculates the destination at run time by adding the
signed 8 bit displacement value to the incremented PC. Negative offset values will cause jumps
upto 128 bytes backwards; positive values upto 127 bytes forward.

In contrast, LJMP instructions jump into any place in the 64K bytes program space. The
instruction is three bytes long, first byte is the opcode and next two bytes give destination
address.Like SJMP, AJMP instructions jump into much longer space, anywhere into 2K block.
The instruction is 2 bytes long, containing the opcode in the first byte and the second byte holds
low byte of the destination address. The opcode itself carries higher order bits of 2K space (bits 8
– 10). During the instruction execution, these 11 bits are simply substituted for the low 11 bits in
the PC. Hence, the destination has to be within the same 2K block as the instruction following
the AJMP.The JMP @A+DPTR instruction supports case jumps. The destination address is
calculated during run time as the sum of the 16 bit DPTR register and the Accumulator.Typical
application for this case jump is the facility to jump to the exact location in a lookup table. This
particular type of jumps is one of the most wanted operations. Normally, the DPTR holds the
address of a lookup table. During runtime, the Accumulator is made to calculate the exact
position of the required byte. This instruction sums up both DPTR and the Accumulator and then
jumps to that specific byte.

37
These are two CALL instructions: LCALL and ACALL. These instructions are used to call
subroutine and they differ in a way the subroutine address is determined.Each instruction
increments the PC to the first byte of the following instruction and then pushes it onto the stack
(low byte first). Saving both bytes increments the Stack Pointer by two. LCALL instruction is for
the long subroutine call operation and the instruction is a 3 byte long one and second and third
bytes carry the address of the subroutine. So the subroutine can be anywhere in the 64K Program
Memory space.But the ACALL instruction drives an absolute subroutine call operation and uses
the 11 bit address format. The subroutine should be within the 2K block as the instruction
following the ACALL.Subroutines should end with a RET instruction that pops the high and low
order bytes of the PC successively from the stack, decreasing the Stack Pointer by two and
program execution continues at the address pushed, the first byte of the instruction immediately
following the call.RETI can be used to return from an interrupt service routine. The only
difference between RET and RETI is that RETI tells the interrupt control system that the
interrupt in progress is done. If there is no active interrupt operation, then the RETI is
functionally same as RET.

5.1.39 CONDITIONAL JUMP INSTRUCTIONS

Like SJMP, all conditional jump instructions use relative addressing: JZ (jump if Zero) and JNZ
(jump if not Zero) monitor the state of the Accumulator as implied by their names while JC
(jump on carry) and JNC (jump on no carry) test whether or not the carry flag is set. All these 4
instructions are two byte instructions.

38
The 8031 instruction set supports another set of conditional jump instruction using Boolean
processing. They are covered separately.

5.1.40 OPERATE AND BRANCH INSTRUCTIONS

CJNE, DJNZ - This group of instructions combine a byte operation with a conditional jump
based on the results. CJNE (Compare and Jump if Not Equal) compares two byte operands and
execute a jump if they disagree. The carry flag is set following the rules of subtraction. If the
unsigned integer value of the first operand is less than that of second, then it is set. Otherwise, it
is cleared. The CJNE instruction can also be used for loop control. Two bytes are specified in the
operand field of the instruction. The jump is executed only if the two bytes are not equal.DJNZ
(Decrement and Jump if not Zero) decrements the register or direct address indicated and jumps
if the result is not zero, without affecting any flags. This provides a simple means of executing a
program loop a given number of times, or for adding a moderate time delay (from 2 to 512
machine cycles) using a single instruction. CJNE and DJNZ, like all conditional jumps use
Program Counter relative addressing for the destination address.

5.1.41 BOOLEAN INSTRUCTIONS

The 8031 devices contain a complete Boolean (single bit) processor. The internal RAM contains
128 addressable bits and the SFR space can support upto 128 other addressable bits. All of the
port lines are bit addressable and each one can be treated as a separate single bit port.

39
The instructions that access these bits are not just conditional branches, but a complete menu of
MOVE, SET, CLEAR, COMPLEMENT, OR, AND instructions. This range of bit operations are
not easily obtained in other architectures with any amount of byte oriented software.The
instruction set for the Boolean processor is shown here. All bit accesses are direct addressing. Bit
addresses 00H through 7FH are in the lower 128 bytes and bit addresses 80H through FFH are in
SFR space.The carry bit is used as the Boolean processor. Bit instructions that refer to the carry
bit as C assemble as carry specific instructions. The carry bit also has a direct address, since it
resides in the PSW register which is bit addressable.Boolean instructions support JB (Jump on
Bit), JNB (Jump on No Bit), JBC (Jump on Bit and Clear), JC (Jump on Carry) and JNC (Jump
on No Carry) operations.The destination address for these jumps is specified in the second byte
of the instruction. This is a signed (two’s complement) offset byte that is added to the PC if the
jump is executed. The range of jump is therefore –128 to +127 Program Memory bytes relative
to the first byte following the jump instruction.

40
41
5.2 POWER SUPPLY

Block Diagram

The ac voltage, typically 220V rms, is connected to a transformer, which steps that ac voltage
down to the level of the desired dc output. A diode rectifier then provides a full-wave rectified
voltage that is initially filtered by a simple capacitor filter to produce a dc voltage. This resulting
dc voltage usually has some ripple or ac voltage variation.

A regulator circuit removes the ripples and also remains the same dc value even if the input dc
voltage varies, or the load connected to the output dc voltage changes. This voltage regulation is
usually obtained using one of the popular voltage regulator IC units.

TRANSFORMER RECTIFIER FILTER IC REGULATOR LOAD

Fig 8 Block Diagram of Power supply

Working principle

Transformer

The potential transformer will step down the power supply voltage (0-230V) to (0-6V) level.
Then the secondary of the potential transformer will be connected to the precision rectifier,
which is constructed with the help of op–amp. The advantages of using precision rectifier are it
will give peak voltage output as DC, rest of the circuits will give only RMS output.

42
Bridge rectifier

When four diodes are connected as shown in figure, the circuit is called as bridge rectifier. The
input to the circuit is applied to the diagonally opposite corners of the network, and the output is
taken from the remaining two corners.
Let us assume that the transformer is working properly and there is a positive potential, at point
A and a negative potential at point B. the positive potential at point A will forward bias D3 and
reverse bias D4.
The negative potential at point B will forward bias D1 and reverse D2. At this time D3 and D1
are forward biased and will allow current flow to pass through them; D4 and D2 are reverse
biased and will block current flow.

The path for current flow is from point B through D1, up through RL, through D3, through the
secondary of the transformer back to point B. this path is indicated by the solid arrows.
Waveforms (1) and (2) can be observed across D1 and D3.

One-half cycle later the polarity across the secondary of the transformer reverse, forward biasing
D2 and D4 and reverse biasing D1 and D3. Current flow will now be from point A through D4,
up through RL, through D2, through the secondary of T1, and back to point A. This path is
indicated by the broken arrows. Waveforms (3) and (4) can be observed across D2 and D4. The
current flow through RL is always in the same direction. In flowing through RL this current
develops a voltage corresponding to that shown waveform (5). Since current flows through the
load (RL) during both half cycles of the applied voltage, this bridge rectifier is a full-wave
rectifier.

One advantage of a bridge rectifier over a conventional full-wave rectifier is that with a given
transformer the bridge rectifier produces a voltage output that is nearly twice that of the
conventional full-wave circuit.

This may be shown by assigning values to some of the components shown in views A and B.
assume that the same transformer is used in both circuits. The peak voltage developed between

43
points X and y is 1000 volts in both circuits. In the conventional full-wave circuit shown—in
view A, the peak voltage from the center tap to either X or Y is 500 volts. Since only one diode
can conduct at any instant, the maximum voltage that can be rectified at any instant is 500 volts.

The maximum voltage that appears across the load resistor is nearly-but never exceeds-500 v0lts,
as result of the small voltage drop across the diode. In the bridge rectifier shown in view B, the
maximum voltage that can be rectified is the full secondary voltage, which is 1000 volts.
Therefore, the peak output voltage across the load resistor is nearly 1000 volts. With both
circuits using the same transformer, the bridge rectifier circuit produces a higher output voltage
than the conventional full-wave rectifier circuit.

IC voltage regulators

Voltage regulators comprise a class of widely used ICs. Regulator IC units contain the circuitry
for reference source, comparator amplifier, control device, and overload protection all in a single
IC. IC units provide regulation of either a fixed positive voltage, a fixed negative voltage, or an
adjustably set voltage. The regulators can be selected for operation with load currents from
hundreds of milli amperes to tens of amperes, corresponding to power ratings from milli watts to
tens of watts.

44
 Fig 9 Circuit Diagram of Power Supply

A fixed three-terminal voltage regulator has an unregulated dc input voltage, Vi, applied to one
input terminal, a regulated dc output voltage, Vo, from a second terminal, with the third terminal
connected to ground.

The series 78 regulators provide fixed positive regulated voltages from 5 to 24 volts. Similarly,
the series 79 regulators provide fixed negative regulated voltages from 5 to 24 volts.
 For ICs, microcontroller, LCD --------- 5 volts
 For alarm circuit, op-amp, relay circuits ---------- 12 volts

5.3 COMPARATOR
In electronics, a comparator is a device that compares two voltages or currents and
switches its output to indicate which is larger. They are commonly used in devices such
as Analog-to-digital converters (ADCs). The input voltages must stay within the limits specified
by the manufacturer. Early integrated comparators, like the LM111 family, and certain high-
speed comparators like the LM119 family, require input voltage ranges substantially lower than
the power supply voltages (±15 V vs. 36V).[1] Rail-to-rail comparators allow any input voltages
within the power supply range. When powered from a bipolar (dual rail) supply,

or, when powered from a unipolar TTL/CMOS power supply:

Specific rail-to-rail comparators with p-n-p input transistors, like the LM139 family, allow input
potential to drop 0.3 Volts below the negative supply rail, but do not allow it to rise above the

45
positive rail.[2] Specific ultra-fast comparators, like the LMH7322, allow input signal to swing
below the negative rail and above the positive rail, although by a narrow margin of only 0.2V.
[3]
 Differential input voltage (the voltage between two inputs) of a modern rail-to-rail comparator
is usually limited only by the full swing of power supply.

5.4 FIRE SENSOR

This fire sensor circuit exploits the temperature sensing property of an ordinary signal diode IN
34 to detect heat from fire. At the moment it senses heat, a loud alarm simulating that of Fire
brigade will be produced. The circuit is too sensitive and can detect a rise in temperature of 10
degree or more in its vicinity. Ordinary signal diodes like IN 34 and OA 71 exhibits this property
and the internal resistance of these devices will decrease when temperature rises.

Fig 10 Typical Fire detecting sensor

The fire sensor circuit is too sensitive and can detect a rise in temperature of 10 degree or more
in its vicinity. Ordinary signal diodes like IN 34 and OA 71 exhibits this property and the
internal resistance of these devices will decrease when temperature rises. In the reverse biased
mode, this effect will be more significant. Typically the diode can generate around 600 milli
volts at 5 degree centigrade. For each degree rise in temperature; the diode generates 2 mV
output voltage. That is at 5 degree it is 10 mV and when the temperature rises to 50 degree, the
diode will give 100 milli volts. This voltage is used to trigger the remaining circuit. Transistor T1
46
is a temperature controlled switch and its base voltage depends on the voltage from the diode and
from VR and R1. Normally T1 conducts (due to the voltage set by VR) and LED glows. This
indicates normal temperature.

When T1 conducts, base pf T2 will be grounded and it remains off to inhibit the Alarm
generator. IC UM 3561 is used in the circuit to give a Fire force siren. This ROM IC has an
internal oscillator and can generate different tones based on its pin connections. Here pin 6 is
shorted with the Vcc pin 5 to get a fire force siren. When the temperature near the diode
increases above 50 degree, it conducts and ground the base of T1. This makes T1 off and T2 on.
Alarm generator then gets current from the emitter of T2 which is regulated by ZD to 3.1 volt
and buffered by C1.Resistor R4 ( 220K) determines the frequency of oscillation and the value
220K is a must for correct tone. To set the fire sensor circuit, keep a lighted candle near the
diode and wait for 1 minute. Slowly adjust VR till the alarm sounds. Remove the heat .After one
minute, alarm will turns off. VR can be used for further adjustments for particular temperature
levels.

Fig 11 Typical Circuit Diagram using Heat Sensor

47
5.5 Gas Sensor

A gas detector is a device which detects the presence of various gases within an area, usually as
part of a safety system. This type of equipment is used to detect a gas leak and interface with a
control system so a process can be automatically shut down. A gas detector can also sound an
alarm to operators in the area where the leak is occurring, giving them the opportunity to leave
the area. This type of device is important because there are many gases that can be harmful to
organic life, such as humans or animals.

Gas detectors can be used to detect combustible, flammable and toxic gases,

and oxygen depletion. This type of device is used widely in industry and can be found in a
variety of locations such as on oil rigs, to monitor manufacture processes and emerging
technologies such as photovoltaic. They may also be used in firefighting.

Gas detectors are usually battery operated. They transmit warnings via a series of audible and
visible signals such as alarms and flashing lights, when dangerous levels of gas vapors are
detected. As detectors measure a gas concentration, the sensor responds to a calibration gas,
which serves as the reference point or scale. As a sensor’s detection exceeds a preset alarm level,
the alarm or signal will be activated. As units, gas detectors are produced as portable or
stationary devices. Originally, detectors were produced to detect a single gas, but modern units
may be used.

48
 Fig 12 Typical gas sensor

5.6 Bluetooth

As one of the youngest member of the LAN family, wireless LANs were little used until
recently. The main reasons for this were high prices and low data rates, as well as licensing
requirements. However, increasing requirements for mobility, relocation and coverage of
locations difficult to wire are making wireless LANs more popular every day.

Wireless LANs can be designed in many different ways depending on their applications, one
kind is a wireless ad-hoc network. An ad-hoc network is a peer-to-peer network set up
temporarily to meet some immediate need. In contrast to the majority of radio systems in use
today, it doesn’t have any centralized server. Ad hoc radio systems have been in use for some
time, for example walky-talky systems are broadly used by police, military and fire departments.
However, the Bluetooth system is the first commercial ad hoc radio system envisioned to be used
on a large scale and widely available to the public.

The Bluetooth radio system began as an idea of Ericsson Mobile Communications in 1994., but
today, it is the result of the joint effort of many large companies (Ericsson, Intel, IBM, Toshiba,
Nokia, Microsoft, Lucent, etc). The Bluetooth system is named after Harald Blatand, a tenth-
century Danish Viking king, who united Denmark and Norway. The name was adopted because
Bluetooth wireless technology is expected to unify the telecommunication and computing
industry. The main aim of Bluetooth is to be widely available, inexpensive, convenient, easy to
use, reliable, small, and low power.

5.6.1 BLUETOOTH RADIO SYSTEM ARCHITECTURE

Bluetooth devices operate at 2.4GHz, in the globally available, license-free, ISM band. That is
the bandwidth reserved for general use by Industrial, Scientific and Medical applications
worldwide. Since this radio band is free to be used by any radio transmitter as long as it satisfies
the regulations, the intensity and the nature of interference can't be predicted. Therefore, the
interference immunity is very important issue for Bluetooth. Generally, interference immunity
can be obtained by interference suppression or avoidance. Suppression can be obtained by
coding or direct-sequence spreading, but the dynamic range of interfering signals in ad hoc
49
networks can be huge, so practically attained coding and processing gains are usually inadequate.
Avoidance in frequency is more practical. Since ISM band provides about 80MHz of bandwidth
and all radio systems are band limited, there is a high probability that a part of the spectrum can
be found without a strong interference.

Considering all this, FH-CDMA (Frequency Hopping - Code Division Multiple Access)
technique has been chosen to implement the multiple access scheme for the Bluetooth. It
combines a number of properties, which make it the best choice for an ad hoc radio system. It
fulfills the spreading requirements set in the ISM band, i.e. on average the signal can be spread
over a large frequency range, but instantaneously only a small part of the bandwidth is occupied,
avoiding most of potential interference. It also doesn't require neither strict time synchronization
(like TDMA), nor coordinated power control (like DS-CDMA). In the 2.45GHz ISM band, a set
of 79 hop carriers has been defined, at 1MHz spacing. A nominal hop dwell time is 625 us. Full-
duplex communication is achieved by applying time-division duplex (TDD), and since
transmission and reception take place at different time slots, they also take place at different hop
carriers. A large number of pseudo-random hopping sequences have been defined, and the
particular sequence is determined by the unit that controls the FH channel. That unit is usually
called the master and it also defines timing parameters during the certain session. All other
devices involved in the session, the slaves, have to adjust their spreading sequences and clocks to
the master's.

Bluetooth uses Gaussian-shaped frequency shift keying (GFSK) modulation with a nominal
modulation index of k=0.3. This binary modulation was chosen for its robustness, and, with the
accepted bandwidth restrictions, it can provide data rates to about 1Mbps. A noncoherent
demodulation can be accomplished by a limiting FM discriminator. This simple modulation
scheme allows the implementation of low-cost radio units, which is one of the main aims of the
Bluetooth system.

An FH Bluetooth channel is associated with the piconet. As mentioned earlier, the master unit
defines the piconet channel by providing the hop sequence and the hop phase. All other units
participating in the piconet are slaves. However, since the Bluetooth is based on peer
communications, the master/slave role is only attributed to a unit for the duration of the piconet.
When the piconet is cancelled, the master and slaves roles are canceled too. In addition to

50
defining the piconet, the master also controls the traffic on the piconet and takes care of access
control. The time slots are alternatively used for master and slaves transmission. In order to
prevent collisions on the channel due to multiple slave transmissions, the master applies a polling
technique, for each slave-to-master slot the master decides which slave is allowed to transmit. If
the master has no information to send, it still has to poll the slave explicitly with a short poll
packet. This master control effectively prevents collisions between the participants in the
piconet, but independent collocated piconets may interfere with one another when they
occasionally use the same hop carrier. This can happen because units don't check for a clear
carrier (no listen-before-talk). If the collision occurs, data are retransmitted at the next
transmission opportunity. Due to the short dwell time, collision avoidance schemes are less
appropriate for FH system.

5.6.2. BLUETOOTH PROTOCOL STACK

The Bluetooth protocol stack is defined as a series of layers, though there are some features
which cross several layers. A Bluetooth device can be made up of two parts: a host implementing
the higher layers of the protocol stack, and a module implementing the lower layers. This
separation of the layers can be useful for several reasons. For example, hosts such as PCs have
spare capacity to handle higher layers, allowing the Bluetooth device to have less memory and a
less powerful processor, which leads to cost reduction. Also, the host device can sleep and be
awoken by an incoming Bluetooth connection. Of course, an interface is needed between the
higher and lower layers, and for that purpose the Bluetooth defines the Host Controller Interface
(HCI). But for some small and simple systems, it is still possible to have all layers of the protocol
stack run on one processor. An example of such a system is a headset.

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 Applications Host
Higher Layers

AT Commands
TCS SDP Upper
Audio L2CAP Control

OBEX
Layers

WAP
HCI Driver on
Host
Physical Bus Driver
RFCOMM
HCI
Logical Link Control and Packets
Applicaton
Bluetooth Module
Physical Bus Driver
Host Controller Interface
Lower
HCI Driver Layers
Link Manager on
Link Manager
Bluetooth
Link Controller Module
Baseband/Link Controller
Radio
Radio

Figure 13 The Bluetooth Protocol Stack

5.6.3 Bluetooth Module

Baseband - There are two basic types of physical links that can be established between a master
and a slave:

 Synchronous Connection Oriented (SCO)

 Asynchronous Connection-Less (ACL)
An SCO link provides a symmetric link between the master and the slave, with regular periodic
exchange of data in the form of reserved slots. Thus, the SCO link provides a circuit-switched
connection where data are regularly exchanged, and as such it is intended for use with time-
bounded information as audio. A master can support up to three SCO links to the same or to
different slaves. A slave can support up to three SCO links from the same master.

52
An ACI link is a point-to-multipoint link between the master and all the slaves on the piconet. It
can use all of the remaining slots on the channel not used for SCO links. The ACL link provides
a packet-switched connection where data are exchanged sporadically, as they become available
from higher layers of the stack. The traffic over the ACL link is completely scheduled by the
master.

Each Bluetooth device has a 48 bit IEEE MAC address that is used for the derivation of the
access code. The access code has pseudo-random properties and includes the identity of the
piconet master. All the packets exchanged on the channel are identified by this master identity.
That prevents packets sent in one piconet to be falsely accepted by devices in another piconet
that happens to use the same hopping frequency in the certain time slot. . All packets have the
same format, starting with an access code, followed by a packet header and ending with the user
payload.

Access Code Header Payload

68 or 72 bits 54 bits 0 - 2745 bits

The access code is used to address the packet to a specific device. The header contains all
the control information associated with the packet and the link. The payload contains the actual
message information. The Bluetooth packets can be 1, 3, or 5 slots long, but the multislot packets
are always sent on a single-hop carrier.

The Link Controller - The link control layer is responsible for managing device discoverability,
establishing connections and maintaining them. In Bluetooth, three elements have been defined
to support connection establishment: scan, page and inquiry.

Inquiry is a process in which a device attempts to discover all the Bluetooth enabled
devices in its local area. A unit that wants to make a connection broadcasts an inquiry message
that induces the recipients to return their addresses. Units that receive the inquiry message return
an FHS (FH-synchronization) packet which includes, among other things, their identity and
clock information. The identity of the recipient is required to determine the page message and

53
wake-up sequence. For the return of FHS packets, a random backoff mechanism is used to
prevent collisions.

Inquiry
o
o
o
Laptop Mobile
Computer Inquiry Phone

FHS

Figure 14 Discovering a Bluetooth device

A unit in idle mode wants to sleep most of the time to save power, but, from time to time,
it also has to listen whether other units want to connect (page scan). In truly ad hoc system, there
is no common control channel a unit can lock to in order to listen for page messages. So, every
time the unit wakes up, it scans at a different hop carrier for an extended time. A trade-off has to
be made between idle mode power consumption and response time: increasing the sleep time
reduces power consumption but prolongs the time before an access can be made. The unit that
wants to connect has to solve the frequency-time uncertainty: it doesn't know when the idle unit
will wake up and on which frequency. For that reason, the paging unit transmits the access code
repeatedly at different frequencies: every 1.25ms the paging unit transmits two access codes and
listens twice for a response. In 10ms period, 16 different hop carriers are visited. If the idle unit
wakes up in any of these 16 frequencies, it will receive the access code and start with a
connection setup procedure. First, it will notify the paging unit by returning a message, and then
it will transmit a FHS packet which contains all of the pager's information. This information is
then used by both units to establish the piconet. Once a baseband link is established, the master
and slave can exchange roles if they wish, so that slave becomes master and master becomes
slave.

It should be noted that the control of links rests completely with the local device. If it
doesn't make itself discoverable by page scanning it cannot be found, if it does not make itself

54
connectable by page scanning it cannot be linked with, and once in a connection it is free to
disconnect without warning at any time.

Audio - Audio data is carried via SCO (Synchronous Connection Oriented) channels. These
SCO channels use pre-reserved slots to maintain temporal consistency of the audio carried on
them. This allows us to build devices such as wireless headsets, microphones and headphones
using Bluetooth for many consumer products such as cellular phones, call centre switchboards,
or even personal musical playback.

There are two routes for audio to pass through a Bluetooth system: through the HCI as
data in HCI packets, and via direct PCM connection to the baseband CODECs.

Higher Layers and Applications

Audio

Data

Control
Audio L2CAP

Host Controller Interface

Link Manager
Baseband
Radio

Figure 15 Position of audio in the Bluetooth stack

The HCI route has some deficiencies in carrying audio data, i.e. packets crossing the
HCL are subject to flow control and therefore to variable latency due to microcontroller
executing the HCI and LM (Link Manager) tasks. The direct PCM route is not well specified in
the Bluetooth specifications, but is very common in commercial implementations.

The Link Manager - The host drives a Bluetooth device through Host Controller Interface
(HCI) commands, but it is the link manager that translates those commands into operations at the

55
baseband level. Its main functions are to control piconet management (establishing and
destruction of the links and role change), link configuration, and security and QoS functions.

Link manager communicates with its peers on other devices using the Link Management
Protocol (LMP). Every LMP message begins with a flag bit which is 0 if a master initiated the
transaction and 1 if the slave initiated the transaction. That bit is followed by a 7-bit Operation
Code, and by the message's parameters.

TID OpCode Parameter 1

Parameter 2 Parameter 3
o
o
o

Parameter N-1 Parameter N

Figure 15 LMP PDU payload body

When a link is first set up, it uses single-slot packets by default. Multi-slot packets make
more efficient use of the band, but there are some occasions when they can't be used, for
example on noisy links or if SCO links don't leave sufficient space between their slots for multi-
slot packets.

LMP also provides a mechanism for negotiating encryption modes and coordinating
encryption keys used by devices on both ends of the link. In addition, LMP supports messages
for configuration of the quality of service on a connection. Packet types can automatically
change according to the channel quality, so that the data can be transferred at a higher rate when
the channel quality is good, and on lower rates with more error protection if the channel quality
deteriorates.

56
WHAT IS BLUETOOTH FOR?

Although originally thought of simply as a replacement for the nest of wires that connects PCs to
keyboards and printers, Bluetooth quickly evolved into a system that will allow people to detect
and communicate with each other through a variety of mainly portable devices without their
users' intervention. Bluetooth devices will be able to talk to each other as they come into range,
which is about 10 meters, although this can be extended to more than 100 meters by increasing
the transmit power from a nominal 1mW to as much as 100mW. Bluetooth technology is
expected to make its debut in cell phones and Palm-type personal digital assistants (PDAs), but
then will move quickly into notebook and laptop computers, printers, scanners, digital cameras,
household appliances, games, toys, and more.

With Bluetooth technology, one can send e-mail from the computer on his lap to the cellular
phone in his briefcase. Bluetooth-linked cell phone or similarly equipped PDA can automatically
synchronize with desktop PC whenever the cell phone passes it within the Bluetooth range. Or,
one can have hands-free communication between a Bluetooth enabled headset and a cell phone.
Or download images from a digital camera to a PC or a cell phone...
Presently, Nokia and Fujifilm are working on a mobile imaging technology that should enable
Nokia to add a Bluetooth chip to its clamshell-shaped 9110 Communicator so that it can receive
images taken on a Bluetooth-equipped Fujifilm digital camera.

Finish telecom operator Sonera has even demonstrated a Bluetooth enabled vending machine -
consumers buy products out of the machine by simply signaling an account code from a
Bluetooth cell phone or PDA.

Many other applications can be also thought of Bluetooth can serve as a means for connecting
laptop computers or other devices to the public Internet in airport lounges and conference centres
through permanent access points. It can also enable its users to exchange business cards with
everyone who passed on a street through a Bluetooth enabled Palm - but not unless it has been
given permission to identify the user to anyone. Maybe it would be neat to have a system that
would automatically reset all the digital clocks in a house following the power outage. Or, to

57
 have a Bluetooth link between the roller blades and a speedometer in a digital watch. But all
these applications will have to wait for some more time before they hit the market, since there is
still a lot of work to be done, mostly regarding interoperability issues and final test procedures
for Bluetooth products.

5.6.4 Bluetooth Host

Logical Link Control and Adaptation Protocol (L2CAP) - Logical Link Control and Adaptation
Protocol takes data from higher layers of the Bluetooth stack and from applications and sends
them over the lower layers of the stack. It passes packets either to the HCI, or in a host-less
system directly to the Link Manager. The major functions of the L2CAP are:
 Multiplexing between different higher layer protocols to allow several higher layer links
to share a single ACL connection. L2CAP uses channel numbers to label packets so that, when
they are received, they can be routed to the correct place.
 Segmentation and reassembly to allow transfer of larger packets than lower layers
support.
 Quality of service management for higher layer protocols.

All applications must use L2CAP to send data. It is also used by Bluetooth's higher layers
such as RFCOMM and SDP, so L2CAP is a compulsory part of every Bluetooth system.

RFCOMM - RFCOMM is a simple, reliable transport protocol that provides emulation of the
serial cable line settings and status of an RS-232 serial port. It provides connections to multiple
devices by relying on L2CAP to handle multiplexing over single connection. RFCOMM
supports two types of devices:
 Type 1 - Internal emulated serial port. These devices usually are the end of a
communication path, for example a PC or printer.
 Type 2 - Intermediate device with physical serial port. These are devices that sit in the
middle of a communication path, for example a modem.

58
 Up to 30 data channels can be set up, so RFCOMM can theoretically support 30 different
services at once. RFCOMM is based on GSM TS 07.10 standard, which is an asymmetric
protocol used by GSM cellular phones to multiplex several streams of data onto one physical
serial cable.

The Service Discovery Protocol - One of the most important members of the Bluetooth protocol
stack is Service Discovery Protocol (SDP). It provides a means for an SDP client to access
information about services offered by SDP servers. An SDP server is any Bluetooth device
which offers services to other Bluetooth devices. Information about services is maintained in
SDP databases. There is no centralized database, so each SDP server maintains its own database.
The SDP database is simply a set of records describing all the services which a Bluetooth device
can offer to another Bluetooth device, and service discovery protocol provides a means for
another device to look at these records. To make it easier to find the service you want, services
are arranged in a hierarchy structure as a tree which can be browsed. Clients begin by examining
the root of the tree, then follow the hierarchy out to the leaf nodes where individual services are
described.

To browse service classes, or get information about a specific service, SDP clients and
servers exchange messages which are carried in SDP Protocol Data Units (PDUs). The first byte
of PDU is an ID, identifying the message in the PDU. Services have Universally Unique
Identifiers (UUIDs) that describe them. The services defined by the Bluetooth profiles have
UUIDs assigned by the standard, but service providers can define their own services and assign
their own UUIDs to those services.

0 8 16 24 32 40

PDU ID Transaction ID Parameter Length

Parameters

Figure 16 Structure of an SDP PDU

59
 SDP relies on L2CAP links being established between SDP client and server, before
retrieving SDP information. Stages in setting up an SDP connection are shown on a following
figure.
Inquiry
Link Controller Paging
Connection Setup
LMP_host connection_req

LMP_accepted

LMP_name_req
Local Device
(SDP Client)
LMP_name_res

Remote Device
Link Manager

(SDP Server)
Connection Setup
Authentication

LMP_Setup_complete

LMP_Setup_complete

L2CAP_connection_req
L2CAP
Connection Setup L2CAP_connection_res

SDP_inquires
SDP Session SDP_responses

Disconnect Terminate Connection

Figure 17 Stages in setting up an SDP session

Supported Protocols - As mentioned at the beginning of this paper, one of the most important
characteristics of the Bluetooth specification is that it should allow devices from lots of different
manufacturers to work with one another. For that reason, Bluetooth is designed in such a way to
allow many different protocols to be run on top of it. Some of these protocols are:

60
 1. The Wireless Access Protocol (WAP) - WAP provides a protocol stack similar to the IP
stack, but it is tailored for the needs of mobile devices. It supports the limited display size and
resolution typically found on mobile devices by providing special formats for Web pages which
suit their capabilities. It also provides for the low bandwidth of mobile devices by defining a
method for WAP content to be compressed before it is transmitted across a wireless link. WAP
can use Bluetooth as a bearer layer in the same way as it can use GSM, CDMA and other
wireless services. The WAP stack is joined to the Bluetooth stack using User Datagram Protocol
(UDP), Internet Protocol (IP) and Point to Point Protocol (PPP).

2. Object Exchange Protocol (OBEX) - OBEX is a protocol designed to allow a variety of

devices to exchange data simply and spontaneously. Bluetooth has adopted this protocol from the
Infrared Data Association (IrDA) specifications. OBEX has a client/server architecture and
allows a client to push data to a server or pull data from the server. For example, a PDA might
pull a file from a laptop, or a phone synchronizing an address book might push it to a PDA. The
similarities between the two communications protocols' lower layers mean that IrDA's OBEX
protocol is ideally suited to transferring objects between Bluetooth devices.

3. The Telephony Control Protocol - Bluetooth's Telephony Control protocol Specification

(TCS) defines how telephone calls should be sent across a Bluetooth link. It gives guidelines for
the signaling needed to set up both point to point and point to multipoint calls. By use of TCS,
calls from an external network can be directed to other Bluetooth devices. For instance, a cellular
phone could receive a call and use TCS to redirect the call to a laptop, allowing the laptop to be
used as a hands-free phone. TCS is driven by a telephony application which provides the user
interface, and provides the source of voice or data transferred across the connection set up by
TCS.

Applications: The Bluetooth Profiles - In addition to protocols which guarantee that two units
speak the same language, Bluetooth specification defines the profiles. They are associated with
applications. The profiles specify which protocol elements are mandatory in certain applications.

61
 This concept prevents devices with little memory and processing power implementing the entire
Bluetooth stack when they only require a small fraction of it. Simple devices like a headset or
mouse can thus be implemented with a strongly reduced protocol stack.

The Bluetooth profiles are organized into groups, with each profile building upon the one
beneath and inheriting features from below. For developers, this means that key features of one
Bluetooth solution can be reused in other solutions, bringing down development costs and
speeding up the development cycle.

Figure 18 Bluetooth profiles

Generic Access Profile Telephony Control Protocol Specification

Service Discovery Cordless Intercom

Application Profile Telephony Profile Profile

Serial Port Profile

Generic Object Exchange Profile
Dial-Up Networking
Profile File Transfer
Profile
FAX
Profile
Object Push
Profile
Headset
Profile
Synchronization
LAN Access Profile
Profile

The profiles implemented by Bluetooth version 1.0 are:

 Generic Access - It defines the basic rules for using the protocol stack.
 Serial Port - How to use RFCOMM's serial port emulation capabilities in Bluetooth
products.
 Dial-up Networking - A Bluetooth link to a modem.
 FAX - How to transfer a fax over Bluetooth.
 Headset - A duplex link to a headset, controlled by an audio gateway such as cellular
phone.

62
 LAN Access Point - A link to LAN via Bluetooth.
 Generic Object Exchange - A set of rules for using OBEX, which supports file transfer,
object push and synchronization profiles.
 File Transfer - Transferring files between Bluetooth devices.
 Object Push - Pushing objects from a Bluetooth enabled server to a client.
 Synchronization - Synchronizing objects between Bluetooth devices.
 Cordless Telephony - Forwarding telephone calls to Bluetooth devices.
 Intercom - Short range voice connections between Bluetooth devices.

5.6.5 Security

Basic security elements need to be considered to prevent unauthorized usage and

eavesdropping in Bluetooth system though it is mainly intended for short-range connectivity
between personal devices. Security features are included at the link level and are based on a
secret link key that is shared by a pair of devices. To generate this key a pairing procedure is
used when the two devices communication for the first time.

At connection establishment, an authentication process is carried out to verify the

identities of the units involved. The authentication process uses a conventional challenge-
response routine. The verifier compares signed response (SRES) produced by the claimant with
its own SRES and decides if the challenger may continue with connection establishment. To
prevent eavesdropping on the link, which is a danger inherent to radio communications, the
payload of each packet is encrypted. Encryption is based on stream ciphering; the payload bits
are modulo-2 added to a binary keystream.

The central element in the security process is the 128-bit link key. This link key is a
secret key residing in the Bluetooth hardware and is not accessible by the user. The link key is
generated during an initialization phase. Once the initialization has been carried out, the 128-bit
link keys reside in the devices and can from then on be used for automatic authentication without

63
user interaction. In addition, methods are available to use the same encryption keys for all slaves
in a single piconet.

Bluetooth provides limited number of security elements at the lowest level. More
advanced security procedures can be implemented at higher layers.

5.6.6 Power Management

As many Bluetooth devices are operated by batteries, special attention has been paid to
the reduction of power consumption in the design. And many tests have been done to prove that
Bluetooth devices are too low in power to have any negative impact on health. Three low-power
modes, which extend battery life by reducing activity on a connection, have been defined. These
modes are called Park, Hold, and Sniff.

Park mode provides the greatest opportunities for power saving. The device only wakes
up in periodic beacon slots when it listens for unpark transmission from the Master. If it is not
unparked, it goes back to sleep, switching off its receiver. Devices that are parked give up their
active member addresses, so one Master can have more devices in Park mode at once. In Sniff
mode, the slave does not scan at every master-to-slave slot, but has a larger interval between
scans. Devices in Sniff mode keep their active member address. Typically, sniffing devices will
be active more often than parked devices. Both Park and Sniff modes involve putting devices
into a state where they wake up periodically while Hold mode just puts a connection in a low-
power state for a single period. So a Master needs to perform an inquiry to be able to service the
connections again.

In the connection state, current consumption is minimized and wasteful interference

prevented by only transmitting when data is available. In longer periods of silence, the master
needs to send a packet on the channel once in a while such that all slaves can resynchronize their
clocks and compensate for drift. During continuous TX/RX operations, a unit starts to scan for
the access code at the beginning of the RX slot. If the access code is not found, or even if it is
found but the slave address does not match the recipient, the unit goes to sleep until the next slot.

64
The header indicates what type of packet it is and how long the packet will last; therefore, the
non-addressed recipients can determine how long they can sleep.

The nominal transmit power used by most Bluetooth applications for short-range
connectivity is 0 dBm. This restricts current consumption and keeps interference to other systems
to a minimum. However, the Bluetooth radio specifications allow TX power up to 20 dBm.
Above 0 dBm, closed-loop received signal strength indication power control is mandatory. This
power control can compensate for propagation losses and slow fading.

In low-power modes many layers of the Bluetooth protocol stack are involved: as after
periods of inactivity, the device may lose synchronization and need to listen for transmissions
over a wider window than usual, the baseband layer alters correlator properties. The link
manager provides a variety of messages to configure and negotiate the low-power modes
between ends of a connection. HCI provides a set of commands that may be used by a host to
configure and control the power-saving capabilities of a module. L2CAP must be aware of low-
power modes for its quality of service commitments.

5.6.7 QoS

Different Bluetooth devices may have different requirements for data rate, delay
variance, and reliability. The specification provides Quality Of Service (QOS) configuration for
the properties of links according to the requirements of higher layer applications or protocols.
These properties include the type of QOS, token rate, token rate bucket size, peak bandwidth,
latency and delay variation.

High Layer Protocols and Applications High Layer Protocols and Applications
QOS Requirements

QOS Requirements
QOS Violations

QOS Violations
QOS Config. Success or FAil

QOS Config. Success or FAil

L2CAP QOS Negotiation

Logical Link Control and Adaptation Logical Link Control and Adaptation
QOS Setup

QOS Setup
QOS ViolationsQOS V

QOS ViolationsQOS V

65
Host Controller Interface Host Controller Interface
QOS Setup

QOS Setup
 Link Manager Link Manager

lationsLink Information

lationsLink Information
Link Control

Link Control
Link Manager Link Manager

Figure 19 QoS Messaging

Figure 6.1 shows how to use message throughout the Bluetooth protocol stack to control
QOS. Messages configuring and setting up QOS flow vertically up and down the layers of the
stack, while Link manager and Logical Link control and Adaptation layer (L2CAP) configure
QOS in peer to peer negotiations. Link Manager actually implements QOS policies for it
configures and controls the baseband links and has various means to try to meet the QOS which
L2CAP requests.

When a link is first set up, QOS is requested from the higher layer to L2CAP. Then the
negotiation packets of QOS configuration are sent between local and remote L2CAP. The link
manager provides QOS capabilities according to the requests from L2CAP. On systems with an
HCI, this interaction between L2CAP and Link Manager is accomplished through a series of
HCI commands and events. LMP commands can be used to configure the poll interval, the
maximum interval between packets sent from Master to Slave, and the broadcast packet repeat
times. QOS setup completion is generated when LMP has finished setting. If failed, message will
be sent back to higher layer to decide whether to try again or to give up. If succeeded, the
channel will then open for transferring data at the desired QOS.

Even a channel has been configured, it is important that applications are aware whether
their QOS is not as requested, as they may wish to either shut down the link rather than run it at
an inappropriate quality, or shut down other links to improve this link. In such case, lower layers
send QOS violation events to tell the higher layers and let them decide what to do about it.

6. ADVANTAGE

 It provides more flexibility.

 By using simple glove cost became low.

7. APPLICATION

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  Buildings

 Industries

8. Conclusion

67