School of Engineering and Physics

EE222
Lab 5

Name: Avishay Narayan(S11158219)

Alvish Naidu (S11158221)
Sidhant Kumar(S11158527)

AIM

The objectives of this experiment are to understand requirement analysis, logic design,
implementation and testing processes. This experiment addresses the design and
implementation of a 1-bit adder/subtractor.

THEORY
The truth table shown in for Half-Adder can be implemented with the following Boolean logic:
S = A ⊕ B (1)
C = A• B (2)
The symbol ⊕ stands for the logic function exclusive-or (XOR), which is one if the inputs are
different and zero if they are the same. The XOR is available as a standard IC logic gate (for
example, the 74x86). This circuit is called a half-adder. The reason for this name is that, although
the circuit works fine for adding two bits, it has no provision for adding a carry-in bit, and
therefore cannot be used directly in arithmetic involving more than two bits.

INPUTS OUTPUTS
SUM Cout
/DIF /Bou
x Cin/Bin B A F t
0 0 0 0 0 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 0 0
The full 1 1 0 0 1 0 adder Boolean
logic 1 1 0 1 0 1 equations for the
sum (S) 1 1 1 0 0 0 and carry-out
(COUT) bits are:
1 1 1 1 1 1

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 SABC =⊕⊕ IN (3)
COUT = A• B + B •CIN + A•CIN

(4) The corresponding logic circuit is shown in Fig. 3.

The rules of Boolean algebra have been used to reduce the carry-out part of the circuit to the
minimum number of logic gates, but it can be proven equivalent to Eq. 4. Figure 3. Full adder logic
circuit. The truth table is given.

INSTRUMENTS
i) Breadboard.
ii) Power Supply
iii) Multimeter
iv) Function Generator
v) Oscilloscope
vi) Resistors (~100 OHMS).
vii) LEDs.
viii) DIP Switch.

METHODOLOGY
The truth table was filled using the knowledge of adders. The input bits were X, Cin/Bin, B and A. The
output bits were SUM/DIF and Cout/Bout. When X was 0, B and A were added and the carry was put
into Cout/Bout column. When X was 1, B and A were subtracted and the carry was put into Cout/Bout
column.

K-maps and logic equations in Sum-Of-Products (SOP) form (with ANDs, ORs, and inverters only) was
filled for the two output signals: SUM/DIFF and Cout/Bout.

The logic equations generated were in minimal SOP but they were further minimized using XOR gates.

The logic circuit diagram for the 1-bit Adder/Subtractor was drawn. How many logic gates were needed
to implement the circuit and how IC’s were needed to implement the circuit was observed.

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The logic circuit diagram of the 1-bit Adder/Subtractor was drawn using only 2-input NAND gates, XOR
gates, and inverters. How many logic gates were needed to implement the circuit and how many IC’s
were needed to implement the circuit was observed.

The IC plan and wiring plan were drawn up and the circuit was constructed to the wiring plan on the
breadboard and shown to the Lab TA. The circuit was tested for all 16 input combinations.

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RESULTS
1.
Inputs Outputs
X Cin/Bi B A SUM/D Cout/B
n IF out
0 0 0 0 0 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 1 1 1
1 0 1 0 1 0
1 0 1 1 0 0
1 1 0 0 1 1
1 1 0 1 0 1
1 1 1 0 0 0
1 1 1 1 1 1

2.

XCin/Bin
BA 00 01 11 10
00 1 1
01 1 1
11 1 1
10 1 1

SUM/DIFF = Bin(B)’(A)’ + (Bin)’(B)’A + BinBA + (Bin)’B(A)’

XCin/Bin
BA 00 01 11 10
00 1

01 1 1 1
11 1 1 1
10 1

Cout/Bout = BinA + XCinBin(B)’ + XCin(B)’A + (XCin)’BA + (XCin)’BinB

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3. SUM/DIFF = Bin(B)’(A)’ + (Bin)’(B)’A + BinBA + (Bin)’B(A)’
= B’(Bin(A)’ + (Bin)’A) + B(BinA + (Bin)’(A)’)
= B’ (Bin ⊕ A) + B(Bin ⊕ A)’
= B ⊕ (Bin ⊕ A)

Cout/Bout = BinA + XCinBin(B)’ + XCin(B)’A + (XCin)’BA + (XCin)’BinB

= Bin (XCin ⊕ B) +A (XCin ⊕ B) + Bin A
=( ((Bin + A) (XCin ⊕ B) + (BinA))’)’
= (((Bin+A)’)’ (XCin ⊕ B) (BinA)’)
= ((Bin)’(A)’)’ (XCin ⊕ B) (BinA)’

4.

-6 logical gates
-3 IC chips

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5.

-6 logic gates
-3 IC chips

6.

6
7

7
 .

DISCUSSION
The 1-bit adder/subtractor accepts two 1-bit binary numbers and a carry input and outputs a 1-bit sum
and a carry. To complete the truth table the half adder addition and subtraction rules were used. For the
first set of inputs which were all zeros, since X was 0, it was added. According to the results the 21 gates
adder/subtractor circuit in minimized SOP form including invertors, AND and OR gates can be further
minimized to an 8-gate adder/subtractor circuit of inverters, NAND and XOR gates. K-Maps and different
Boolean identities were used to minimize the circuit. The XOR gate plays a major factor in minimizing

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the sum portion of the circuit as the sum portion of the minimized SOP form can be minimized to just 2
XOR gates. The Cout/Bout can be minimized to just 6 gates (2 invertors, 3 NAND gates and an XOR gate).

CONCLUSION
After completing this lab, it was learned how adders are implemented using XOR gates, NAND gates and
NOR gates. It was also learnt how to simplify the Boolean algebra expressions into XOR classifications.

REFERENCE
[1]"Half Adder and Full Adder Circuit with Truth Tables", ElProCus - Electronic Projects for Engineering
Students, 2019. [Online]. Available: https://www.elprocus.com/half-adder-and-full-adder/. [Accessed:
28- Mar- 2019].
[2]"XOR Gate - Learning About Logic Gates and Circuits", Logic.ly, 2019. [Online]. Available:
https://logic.ly/lessons/xor-gate/. [Accessed: 28- Mar- 2019].