visualization for the first time.

Ultrasmall digital image sensor

for endoscopic applications 1 INTRODUCTION

Martin Wäny*, Stephan Voltz, Fabio Gaspar, Lei The presented work addresses visualization in the
Chen, AWAIBA Lda. Madeira Tecnopolo, endoscopic field, mainly for minimally invasive surgery
and diagnosis. Especially for procedures in minimal size
9020-105 Funchal, Maderia Portugal. cavities or to locations where minimal diameter cavities
have to be passed for access. Standard endoscopic
ABSTRACT equipment with distal image sensor technology (chip on
tip endoscopes) was limited to endoscope diameters
This paper presents a digital image sensor SOC featuring a superior to 1mm, especially when besides the imaging
total chip area (including dicing tolerances) of 0.34mm2 channel working channels have to be added in the
for endoscopic applications. Due to this extremely small endoscope. This limitation mainly arose due to the used
form factor the sensor enables integration in endoscopes, CCD imaging technology which is limited to analogue
guide wires and locater devices of less than 1mm outer signal transmission, and requires multiple control inputs
diameter. The sensor embeds a pixel matrix of 10'000 for readout. Typically CMOS Image sensors for
pixels with a pitch of 3um x 3um covered with RGB filters endoscopic applications target similar applications than
in Bayer pattern. The sensor operates fully autonomous, earlier CCD's or explored the low power consumption [1-
controlled by an on chip ring oscillator and readout state 3] or lower cost [4-5] of CMOS image sensors. However
machine, which controls integration AD conversion and target generally applications which allow for sensor
data transmission, thus the sensor only requires 4 pin's for dimensions above 1mm. The demonstrated CMOS sensor
power supply and data communication. The sensor technology addresses procedures where smaller endoscope
provides a frame rate of 40Frames per second over a diameters are required, namely where the total scope
LVDS serial data link. The endoscopic application diameters needs to be below 1mm. The requirement to
requires that the sensor must work without any local reduce sensor size considerably below 1mm2 and enabling
power decoupling capacitances at the end of up to 2m operation without any external components, called for size
cabling and be able to sustain data communication over reduction of all components in the SOC sensors and high
the same wire length without deteriorating image quality. PSRR blocks. The reminder of this paper will address the
This has been achieved by implementation of a current design of the over all architecture and the most critical
mode successive approximation ADC and current steering blocks in required to integrate the sensor in the target chip
LVDS data transmission. An band gap circuit with -40dB area and finally will give characterization results.
PSRR at the data frequency was implemented as on chip
reference to improve robustness against power supply 2 SENSOR ARCHITECTURE
ringing due to the high series inductance of the long
cables. The B&W versions of the sensor provides a 2.1 Chip architecture
conversion gain of 30DN/nJ/cm2 at 550nm with a read
noise in dark of 1.2DN when operated at 2m cable. Using In order to minimize surface consumption the chip was
the photon transfer method according to EMVA1288 designed to work with a single 1.8V supply only. This
standard the full well capacity was determined to be permits to use smaller real estate for ESD protection. For
18ke-. According to our knowledge the presented work is critical matching the 1.8V MOS devices provide better
the currently world smallest fully digital image sensor. miss match performance per gate area compared to the
The chip was designed along with an aspheric single 3.3V counterparts. However the single 1.8V operation
surface lens to assemble on the chip without increasing the limit's the available head room for analogue circuitry,
form factor. The extremely small form factor of the especially in the on chip band gap reference but also the
resulting camera permit's to provide visualization with ADC and most importantly the pixel matrix. All blocks
much higher than state of the art spatial resolution in sub must be able to cope with significant power supply noise,
1mm endoscopic applications, where so far only optical since no off chip decoupling capacitors are available and
fiber bundles providing 1k – 3k image points could be the power supply wiring can be up to 2.5m for some
used. In many applications, such as guide wires and endoscopic applications. Figure 1 gives a simulated plot of
locater devices the small form factor permits to implement the power rails including the full chip consumption and a
wire model for a 2.4m supply and data lines. In order to
* waeny@awaiba.com phone +351 291 7253 124; fax  reduce the supply current surge, the main blocks were
+351 291 720 031; www.awaiba.com  designed in current mode schemes with constant total
current consumption. (Current steering instead of current A successive approximation register compares the
switching). Figure 2 shows the block diagram of the chip, sampled input signal with the programmable I-DAC
which is strictly reduced to the minimal amount of blocks voltage and adjusts in binary way. The block diagram of
necessary for autonomous function. the 8bit SAR is shown in figure 3.

S&H
Vin
SAR serial_out

IDAC

Fig.3: Block Diagram of the semi current mode 8bit

Fig. 1: Simulation of the on chip power ripple due to
SAR-ADC
2.4m cabling.

VDD
The over all timing of the ADC is made such that the
Readout Controller
ADC produces an 8bit sample every 10 clocks. The SAR
POR output is directly used as bit serial output stream to the
global_rst LVDS driver. Therefore the SAR reset state and tracking
VSS phase of the S&H stage had to be aligned such that they
Ring
provide a start and stop bit for the bit serial data
Row Decoder

Oscilator Bandgap
Pixel matrix Reference communication. The ADC works at 400kS/s with a 4MHz
ADC
Control
frequency to support a frame rate of 40Fps. The
out_n comparator offset is not important in this architecture nor
Column Buffer the absolute current reference offset, since both will only
ADC
lead to an over all offset shift of the pixel values, however
Column Decoder out_p both of them have to be insensitive to variation of the
Bias Generation
supply voltage.
Fig. 2: Chip block diagram.
3 RESULTS
2.3 AD Converter
3.1 ADC performance
AD converters in image sensors are typically implemented
as switched capacitor cyclic or pipelined architectures, [6] The ADC was implemented for test purpose in a separate
or more recently mainly as column parallel ADC's [7]. test chip. The characterized DNL of the ADC is shown in
However both of these architectures are much too figure 4. Due to a miss match slightly above estimation in
demanding for the available real estate of this sensor. For the IDAC a significant DNL error occurs when switching
low cost wireless sensors [8;9] had presented charge between the 4 thermometer bits and the binary steps in the
redistribution based ADCs with only 0.05mm2 area at IDAC, which result at a DNL increase every 16 codes.
100kHz resp. 0.034mm2 at 250kHz, which is in the target Besides these artifacts the ADC behaves well and since
range of our adc of 90um x 250um, and 400kHz sampling most of the output range in the imaging application will be
rate. Due to the high expected ripple on the power supply dominated by photon shot noise, the ADC performance is
the use of a capacitor based ADC was not preferred for sufficient for the purpose. Table 1 summarizes the ADC
noise coupling reasons. Therefore a current based SAR performance.
ADC was chosen. The reference current and a reference
voltage is generated from the band gap voltage and
multiplied by a DAC with 4 binary and 4 thermometer
bits. In order to avoid ringing by changes in current
consumption, the total current consumption of the IDAC is
maintained constant, and the non used current is drained.
 DNL 8bit ADC Total power  26mW
2 .5
consumption
2

1.5
Responsivity  30DN/nJ/cm2
1
B&W
DNL [DN/8bit]

0.5
Temporal noise  1.2DN
in dark
DNL
0

-0.5

-1
Bit resolution 8
-1.5
Frame rate 40Fps
-2
0.2 0.4 0.6 0.8
Input Vltage
1 1.2 1.4
Dynamic range 46.5 dB

Fig. 4: DNL of the ADC as measured on a separate Number of pixels 10'000

test chip for characterization purpose. Color version RGB Bayer
Table 1: Electrical and performance
Area 0.022mm2
Sampling Rate 400kHz Two sample images of the sensor are given in figure 7.

Power consumption 7mW
Bit Resolution 8 bit
Table 1: ADC Performance

3.2 Image sensor over all performance

The complete image sensor was characterized while using

a de-serialization to 8bit implemented in an FPGA, which
provides recovery of the clock signal embedded in the data Fig. 7: Two sample images of the sensor. Left
stream at every found bit transition. The B&W version of “Siemens star”, right McBeth color checker board.
the sensor was characterized using the photon transfer
method [10]. Figure 5. shows the obtained results. 5 CONCLUSIONS
Temporal Noise Variance [DN²]

Photon transfer plot

6.5

6
The presented work shows a image sensor with minimal
5.5 form factor. To our knowledge the presented work is
5

4.5
currently the world's smallest digital image sensor. The
4 availability of such small image sensors opens a complete
3.5
new filed to medical diagnosis and treatment over
E2 Temp Noise[DN²]
Physical limit (shot
3 nosie) [DN²]

2.5
minimally invasive procedures. Further improvements on
2

1.5 the somewhat disappointing ADC performance of the

1

0.5
demonstration sensor have already been undertaken by
0
0 25000 50000 75000
AWAIBA, which lead currently to comparable sensors
Photons/pixel [p~] exceeding true 9bit performance. The scope of this work
Fig. 5: Photon Transfer plot, showing the variance of to demonstrate feasibility of a SOC imager with only
the noise measured with 2m cabling versus the 0.35mm2 chip surface and its usability for endoscopic
physical shot noise limit. applications was clearly achieved.

A summary of the electrical and optical performance and REFERENCES

specification is given in table 2.
[1] Kwang-Bo Cho, A. Krymski, E. Fossum, " A 1.5V
Parameter Specification  550uW 176x144 Autonomous CMOS Active Pixel
Image Sensor" IEEE Trans. Electron Devices Vol 50
Supply voltage 1.8V Jan 2003 pp 96 - 106
[2] Shinya Itoh, Shoji Kawahito and Susumu
Terakawa,"A 2.6mW 2fps QVGA CMOS One-Chip
Wireless Camera with Digital Image Transmission
Function for Capsule Endoscopes", Proc. 2006 IEEE
International Symposium on Circuits and Systems
B3P-Z, pp.3353-3356, 2006.

[3] Milin Zhang, Bermak, A. Xiaowen Li, Zhihua Wang

"A low power CMOS image sensor design for wireless
endoscopy capsule" Proc. IEEE Biomedical Circuits
and Systems Conference, 2008. BioCAS 2008. pp.
397-400 20-22 Nov. 2008

[4] Dany Scheffer, "Endoscopes use CMOS image

sensors" On line: http://www.vision-
systems.com/display_article/301875/19/none/none/SP
FEA/Endoscopes-use-CMOS-image-sensors

[5] On Line:
http://www.ovt.com/uploads/parts/OV6930_PB(1.0)_
web.pdf
[6] S. Tanner; S. C. Lauxtermann; M. Waeny; M.
Willemin; N. Blanc; J. Grupp; R. Dinger; E. Doering;
M. Ansorge; P. Seitz; F. Pellandini "Low-power
digital image sensor for still-picture image acquisition"
Proc. of SPIE Vol. 4306 pp358-365
[7] M. F. Snoeij, A. Theuwissen, K. Makinwa, J. Huijsing
"A CMOS Imager With Column-Level ADC Using
Dynamic Column Fixed-pattern Noise Reduction"
IEEE JSSC Vol. 41, No 12 DEC 2006 pp 3007-3015

[8] M. Scott, B. Boser, K. Pister " An Ultralow-Energy

ADC for Smart Dust" IEEE JSSC Vol. 38. No 7 July
2003 pp 1123-1129

[9] K. Tanaka, Y. Kuramochi, T. Kurashina, K. Okada, A.

Matsuzuwa. " A 0.026mm2 Capacitance-to-Digital
Converter for Biotelemetry Applications Using a
Charge Redistribution Technique" Proc. EEE ASSCC
2007, 9-1 pp-244-247.

[10] Janesick, James R., CCD characterization using the

photon transfer technique, Proc. SPIE Vol. 570, Solid
State Imaging Arrays, K. Prettyjohns and E. Derenlak,
Eds., pp. 7-19 (1985)