Datasheet FAN 6755 PDF

FAN6755 — Highly Integrated Green-Mode PWM Controller
February 2010
FAN6755
Highly Integrated Green-Mode PWM Controller
Features Description
Internal High-Voltage Startup This highly integrated PWM controller provides several
features to enhance the performance of flyback
Low Operating Current (Maximum: 2mA) converters.
Adaptive Decreasing of PWM Frequency to 23KHz To minimize standby power consumption, a proprietary
at Light-Load condition to Improve Light-Load adaptive green-mode function reduces switching
Efficiency frequency at light-load condition. To avoid acoustic-
Frequency Hopping to Reduce EMI Emission noise problems, the minimum PWM frequency is set
above 23kHz. This green-mode function enables the
Fixed PWM Frequency: 65KHz power supply to meet international power conservation
®
Internal Leading-Edge Blanking requirements, such as Energy Star . With the internal
high-voltage startup circuitry, the power loss caused by
Built-in Synchronized Slope Compensation bleeding resistors is also eliminated. To further reduce
Auto-Restart Protection : Feedback Open-Loop power consumption, FAN6755 uses the BiCMOS
Protection (OLP), VDD Over-Voltage Protection process, which allows an operating current of only 2mA.
(OVP), Over-Temperature Protection (OTP), and The standby power consumption can be under 100mW
Line Over-Voltage Protection for most of LCD monitor power supply designs.
Soft Gate Drive with Clamped Output Voltage: 18V FAN6755 integrates a frequency-hopping function that
reduces EMI emission of a power supply with minimum
VDD Under-Voltage Lockout (UVLO) line filters. Its built-in synchronized slope compensation
Programmable Constant Power Limit (Full AC achieves a stable peak-current-mode control and
Input Range) improves noise immunity. The proprietary, external line
compensation ensures constant output power limit over
Internal OTP Sensor with Hysteresis a wide AC input voltage range from 90VAC to 264VAC.
Build-in 5ms Soft-Start Function
FAN6755 provides many protection functions. The
Input Voltage Sensing (VIN Pin) for Brown-in/out internal feedback open-loop protection circuit protects
Protection with Hysteresis and Line Over-Voltage the power supply from open feedback loop condition or
Protection output short condition. It also has line under-voltage
protection (brownout protection) and over-voltage
protection using an input voltage sensing pin (VIN).
Applications
FAN6755 is available in a 7-pin SOP package.
General-purpose switched-mode power supplies and
flyback power converters, including:
LCD Monitor Power Supply
Open-Frame SMPS
Ordering Information
Operating Eco
Part Number Package Packing Method
Temperature Range Status
7-Lead, Small Outline Integrated
FAN6755MY -40 to +105°C Green Circuit (SOIC), Depopulated Reel & Tape
JEDEC MS-112, .150 Inch Body
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

ENERGY STAR® is a registered trademark of the U.S. Department of Energy and the U.S. Environmental Protection Agency.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6755 • Rev. 1.0.0 1
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Figure 2. Functional Block Diagram

FAN6755 • Rev. 1.0.0 2
Marking Information
7
Z: Plant Code
X: 1-Digit Year Code
ZXYTT Y: 1-Digit Week Code
6755 TT: 2-Digit Die Run Code
TPM T: Package Type (M:SOP)
P: Y=Green Package
1 M: Manufacture Flow Code
Figure 3. Top Mark
Pin Configuration
SOP-7
VIN 1 7 HV
FB 2
SENSE 3 6 VDD
GND 4 5 GATE
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
Line-voltage detection. The line-voltage detection is used for brownout protection with
hysteresis. Constant output power limit over universal AC input range is also achieved using this
1 VIN
VIN pin. It is suggested to add a low-pass filter to filter out line ripple on the bulk capacitor.
Pulling VIN HIGH also triggers auto-restart protection.
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
2 FB
determined in response to the signal on this pin and the current-sense signal on the SENSE pin.
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
3 SENSE
current limiting.
4 GND Ground
5 GATE The totem-pole output driver. Soft-driving waveform is implemented for improved EMI.
Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the
6 VDD
OVP trigger point.
7 HV For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.

FAN6755 • Rev. 1.0.0 3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit

(1, 2)
VVDD DC Supply Voltage 30 V
VFB FB Pin Input Voltage -0.3 7.0 V
VSENSE SENSE Pin Input Voltage -0.3 7.0 V
VVIN VIN Pin Input Voltage -0.3 7.0 V
VHV HV Pin Input Voltage 700 V
PD Power Dissipation (TA＜50°C) 400 mW
ΘJA Thermal Resistance (Junction to Air) 150 °C/W
TJ Operating Junction Temperature -40 +125 °C
TSTG Storage Temperature Range -55 +150 °C
TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 °C
Human Body Model,
All Pins Except HV Pin 4.5
JEDEC: JESD22-A114
ESD kV
Charged Device Model,
All Pins Except HV Pin 1.0
JEDEC: JESD22-C101
Notes:
1. All voltage values, except differential voltages, are given with respect to the network ground terminal.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD with HV pin CDM=1000V and HBM=500V.

FAN6755 • Rev. 1.0.0 4
Electrical Characteristics
VDD=15V, TA=25°C, unless otherwise noted.
Symbol Parameter Conditions Min. Typ. Max. Units

VDD Section
VOP Continuously Operating Voltage 22 V
VDD-ON Start Threshold Voltage 15 16 17 V
VDD-OFF Protection Mode 9 10 11 V
UVLO Normal Mode 6.8 7.8 8.8 V
IDD-ST Startup Current VDD-ON – 0.16V 30 µA
IDD-OP Operating Supply Current VDD=15V, GATE Open 2 mA
IDD-OLP Internal Sink Current VTH-OLP+0.1V 30 60 90 µA
Threshold Voltage on VDD for HV
VDD-OLP 6.5 7.5 8.0 V
JFET Turn-On
VDD-OVP VDD Over-Voltage Protection 25 26 27 V
VDD Over-Voltage Protection
tD-VDDOVP 75 125 200 µs
Debounce Time
Figure 5. VDD Behavior
Continued on the following page…

FAN6755 • Rev. 1.0.0 5

HV Section
Supply Current Drawn from HV VDC=120V, VDD=10µF,
IHV 2.0 3.5 5.0 mA
Pin VDD=0V
HV=700V, VDD=VDD-
IHV-LC Leakage Current after Startup 1 20 µA
OFF+1V
Oscillator Section
Center Frequency 62 65 68
fOSC Frequency in Normal Mode KHz
Hopping Range ±4.5 ±5.2 ±5.9
fOSC-G Green-Mode Frequency 20 23 26 KHz
tH-OP Hopping Period 4.20 5.05 5.90 ms
Frequency Variation vs. VDD
fDV VDD=11V to 22V 5 %
Deviation
Frequency Variation vs.
fDT TA=-40 to 85°C 5 %
Temperature Deviation
VIN Section
VIN-OFF PWM Turn-Off Threshold Voltage 0.66 0.70 0.74 V
VIN-OFF+ VIN-OFF+ VIN-OFF+
VIN-ON PWM Turn-On Threshold Voltage V
0.17 0.20 0.23
VIN-Protect PWM Protect Threshold Voltage 5.1 5.3 5.5 V
tVIN-Protect PWM Protect Debounce Time 60 100 140 µs
Current-Sense Section
VTH-P at Threshold Voltage for Current
VIN=1V 0.80 0.83 0.86 V
VIN=1V Limit
VTH-P at Threshold Voltage for Current
VIN=3V 0.67 0.70 0.73 V
VIN=3V Limit
tPD Delay to Output 100 200 ns
tLEB Leading-Edge Blanking Time 240 290 340 ns
tSS Period During Soft-Start Time Startup Time 4.0 5.5 7.0 ms
Figure 6. VIN vs. VSENSE

FAN6755 • Rev. 1.0.0 6

Feedback Input Section
Input Voltage to Current-Sense
AV 1/4.5 1/4.0 1/3.5 V/V
Attenuation
ZFB Input Impedance VFB =4V 11 15 18 kΩ
VFB-OPEN Output High Voltage FB Pin Open 5.1 5.3 5.5 V
VFB-OLP FB Open-Loop Trigger Level 4.4 4.6 4.8 V
Delay Time of FB Pin Open-loop
tD-OLP 45.0 62.5 70.0 ms
Protection
VFB-N Green-Mode Entry FB Voltage 2.8 3.0 3.2 V
VFB-G Green-Mode Ending FB Voltage VFB-N - 0.6 V

FB Threshold Voltage for Zero-
VFB-ZDCR 1.6 1.8 2.0 V
Duty Recovery
FB Threshold Voltage for Zero-
VFB-ZDC 1.4 1.6 1.8 V
Duty
VFB-ZDCR -
ZDC Hysterisis 0.12 0.15 0.19 V
VFB-ZDC
PWM Frequency
fOSC
fOSC-G
VFB-ZDC VFB-ZDCR VFB-G VFB-N VFB
Figure 7. VFB vs. PWM Frequency

FAN6755 • Rev. 1.0.0 7

GATE Section
DCYMAX Maximum Duty Cycle 60 75 90 %
VGATE-L Gate Low Voltage VDD=15V, IO=50mA 1.5 V
VGATE-H Gate High Voltage VDD=12V, IO=50mA 8 V
tr Gate Rising Time VDD=15V, CL=1nF 100 ns
tf Gate Falling Time VDD=15V, CL=1nF 30 ns
IGATE-
Gate Source Current VDD=15V, GATE=6V 700 mA
SOURCE
VGATE-
Gate Output Clamping Voltage VDD=22V 18 V
CLAMP_1
Over-Temperature Protection Section (OTP)

(4)
TOTP Protection Junction Temperature 135 °C
(5)
TRestart Restart Junction Temperature TOTP-25 °C
Notes:
4. When activated, the output is disabled and the latch is turned off.
5. The threshold temperature for enabling the output again and resetting the latch after over-temperature
protection has been activated.

FAN6755 • Rev. 1.0.0 8
Typical Performance Characteristics
Figure 9. Operation Supply Current (IDD-OP)

Figure 8. Startup Current (IDD-ST) vs. Temperature
vs. Temperature
Figure 10. Start Threshold Voltage (VDD-ON) Figure 11. Minimum Operating Voltage (VDD-OFF)
vs. Temperature vs. Temperature
Figure 12. Supply Current Drawn from HV Pin (IHV) Figure 13. HV Pin Leakage Current After Startup
vs. Temperature (IHV-LC) vs. Temperature
Figure 14. Frequency in Normal Mode (fOSC) Figure 15. Maximum Duty Cycle (DCYMAX)
vs. Temperature vs. Temperature
FAN6755 • Rev. 1.0.0 9
Typical Performance Characteristics
Figure 16. FB Open-Loop Trigger Level (VFB-OLP) Figure 17. Delay Time of FB Pin Open-Loop Protection
vs. Temperature (tD-OLP) vs. Temperature
VIN-ON
VIN-OFF
Figure 18. PWM Turn-Off Threshold Voltage (VIN-OFF & Figure 19. VDD Over-Voltage Protection (VDD-OVP)
VIN-ON) vs. Temperature vs. Temperature
Figure 20. VIN vs. VLIMIT

FAN6755 • Rev. 1.0.0 10
Functional Description
Startup Current Gate Output / Soft Driving

For startup, the HV pin is connected to the line input The BiCMOS output stage is a fast totem-pole gate
(1N4007 / 100KΩ recommended) or bulk capacitor driver. Cross conduction has been avoided to minimize
through a resistor, RHV. Startup current drawn from pin heat dissipation, increase efficiency, and enhance
HV (typically 3.5mA) charges the hold-up capacitor reliability. The output driver is clamped by an internal
through the diode and resistor. When the VDD capacitor 18V Zener diode to protect power MOSFET transistors
level reaches VDD-ON, the startup current switches off. At against undesirable gate over voltage. A soft driving
this moment, the VDD capacitor only supplies the waveform is implemented to minimize EMI.
FAN6755 to maintain VDD before the auxiliary winding of
the main transformer to provide the operating current. Soft Start
For many applications, it is necessary to minimize the
Operating Current inrush current at startup. The built-in 5.5ms soft-start
Operating current is around 2mA. The low operating circuit significantly reduces the startup current spike
current enables better efficiency and reduces the and output voltage overshoot.
requirement of VDD hold-up capacitance.
Slope Compensation
Green-Mode Operation The sensed voltage across the current-sense resistor is
The proprietary green-mode function provides an off- used for peak-current-mode control and pulse-by-pulse
time modulation to reduce the switching frequency in current limiting. Built-in slope compensation improves
light-load and no-load conditions. The on time is limited stability and prevents sub-harmonic oscillation.
for better abnormal or brownout protection. VFB, which is FAN6755 inserts a synchronized positive-going ramp at
derived from the voltage feedback loop, is taken as the every switching cycle.
reference. Once VFB is lower than the threshold voltage,
switching frequency is continuously decreased to the Constant Output Power Limit
minimum green-mode frequency of around 23KHz.
For constant output power limit over universal input-
voltage range, the peak-current threshold is adjusted by
Current Sensing / PWM Current Limiting the voltage of the VIN pin. Since the VIN pin is
Peak-current-mode control is utilized to regulate output connected to the rectified AC input line voltage through
voltage and provide pulse-by-pulse current limiting. The the resistive divider, a higher line voltage generates a
switch current is detected by a sense resistor into the higher VIN voltage. The threshold voltage decreases as
SENSE pin. The PWM duty cycle is determined by this VIN increases, making the maximum output power at
current sense signal and VFB, the feedback voltage. high-line input voltage equal to that at low-line input.
When the voltage on the SENSE pin reaches around The value of R-C network should not be so large that it
VCOMP=(VFB–0.6)/4, a switch cycle is terminated affects the power limit (shown in Figure 21). Usually, R
immediately. VCOMP is internally clamped to a variable and C should be less than 100Ω and 470pF,
voltage around 0.83V for output power limit. respectively.
Leading-Edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)

The turn-on and turn-off thresholds are fixed internally
at 16V and 7.8V in normal mode. During startup, the
hold-up capacitor must be charged to 16V through the
startup resistor to enable the IC. The hold-up capacitor
continues to supply VDD before the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 7.8V during startup. This
UVLO hysteresis window ensures that the hold-up Figure 21. Current-Sense R-C Filter
capacitor is adequate to supply VDD during startup.

FAN6755 • Rev. 1.0.0 11
VDD Over-Voltage Protection Limited Power Control
VDD over-voltage protection prevents damage due to The FB voltage is saturated HIGH when the power
abnormal conditions. Once the VDD voltage is over the supply output voltage drops below its nominal value and
over-voltage protection voltage (VDD-OVP), and lasts for shut regulator (KA431) does not draw current through
tD-VDDOVP, the PWM pulses are disabled. When the VDD the opto-coupler. This occurs when the output feedback
voltage drops below the UVLO, PWM pulses start loop is open or output is short circuited. If the FB
again. Over-voltage conditions are usually caused by voltage is higher than a built-in threshold for longer than
open feedback loops. tD-OLP, PWM output is turned off. As PWM output is
turned off, VDD begins decreasing since no more energy
Brownout Protection is delivered from the auxiliary winding.
Since the VIN pin is connected through a resistive When VDD goes below the turn-off threshold (~7.8V),
divider to the rectified AC input line voltage, it can also the controller is totally shut down. VDD is charged up to
be used for brownout protection. If VIN is less than 0.7V, the turn-on threshold voltage of 16V through the startup
the PWM output is shut off. When VIN reaches over resistor until PWM output is restarted. This protection
0.9V, the PWM output is turned on again. The feature continues as long as the over loading condition
hysteresis window for ON/OFF is around 0.2V. The persists. This prevents the power supply from
brownout voltage setting is determined by the potential overheating due to overloading conditions.
divider formed with RUpper and RLower. Equations to
calculate the resistors are shown below: Noise Immunity
RLower Noise on the current sense or control signal may cause
VIN = × VAC 2 , (unit = V ) (1) significant pulse-width jitter, particularly in continuous-
RLower + RUpper conduction mode. Slope compensation helps alleviate
this problem. Good placement and layout practices
should be followed. Avoiding long PCB traces and
Thermal Overload Protection component leads, locating compensation and filter
Thermal overload protection limits total power components near the FAN6755, and increasing the
dissipation. When the junction temperature exceeds TJ= power MOS gate resistance improve performance.
+135°C, the thermal sensor signals the shutdown logic
and turns off most of the internal circuitry. The thermal
sensor turns internal circuitry on again after the IC’s
junction temperature drops by 25°C. Thermal overload
protection is designed to protect the FAN6755 in the
event of a fault condition. For continual operation, do
not exceed the absolute maximum junction temperature
of TJ = +150°C.

FAN6755 • Rev. 1.0.0 12
Applications Information
R6
C7 12V1 12V P1
R7 L2
N18 1 2
12V
C5
1 C10 R8
F1 + C8 + C9
2
2
N1 N1A N2
BD1 3
R1
3
CN1 C1
2
L M1 L1 4 1 N4 4 TX1 12 N17 D1
1 C3
N28 11
2 R4
ZD1 N21
3 C4
R3
AC IN R2 C2 8 R5 C6 5V1 5V P2
4
L3
N20 1 2
3
5V
11
N N3 C11 N5 N6 6 7
D3 1 1
+ R14
VIN 2
2
N7 10 R17
2 9 3 C15
D4 + C13 + C14
2
R13 C12 D5
R9
2
N8 P3
1
Q1 SGND
N30
R16
2
N10 1 N9
R10
D2 R11 N29
3
R15
R12
HV
1
VIN
U1
1 8
VIN HV
FB 2 7 VDD R20
FB NA 5V1
R19
1
3 6 N12 N13
SENSE VDD U2 R22
4 5 GATE
GND GATE
C16 12V 5V
FAN6755 R28 C18 + C19
C17
SENSE
C20 R23 R24 R25
2
R21
N14 N15
K
U3
R N16
R18
R26 R27
A
Figure 22. 44W Flyback 12V/2A, 5V/4A Application Circuit

FAN6755 • Rev. 1.0.0 13
Build of Materials
Designator Part Type Designator Part Type
BD1 BD 4A/600V Q1 MOS 9A/600V
C1 YC 2200pF/Y1 R1 R 1.5MΩ 1/4W
C2 YC 2200pF/Y1 R2 R 1.5MΩ 1/4W
C3 XC 0.33µF/300V R3 R 10MΩ 1/4W
C4 NC R4, R5, R6, R7 R 47Ω 1/4W
C5 YC 2200pF/Y1 R8, R17, R25, R27 NC
C6 CC 2200pF/100V R9 R 50KΩ 1/4W
C7 CC 1000pF/100V R10 R 50KΩ 1/4W
C8 EC 1000µF/25V R11 R 0Ω 1/8W
C9 EC 470µF/25V R12 R 47Ω 1/8W
C10 CC 100pF/50V R13 R 100KΩ 1/8W
C11 EC 100µF/400V R14 R 0Ω 1/4W
C12 C 1µF/50V R15 R 10KΩ 1/8W
C13 EC 1000µF/10V R16 R 1Ω 1/8W
C14 EC 470µF/10V R18 R 0Ω 1/8W
C15 CC 100pF/50V R19 R 100Ω 1/8W
C16 C 1nF/50V R20 R 1KΩ 1/8W
C17 C 470pF/50V R21 R 4.7KΩ 1/8W
C18 EC 47µF/50V R22 R 7.5KΩ 1/8W
C19 C 0.01µF/50V R23 R 120KΩ 1/8W
C20 C 0.1µF/50V R24 R 15KΩ 1/8W
D1 FYP1010 R26 R 10KΩ 1/8W
D2 1N4148 R28 R 0.43Ω 2W
D3 FR107 TX1 800µH(ERL-28)
D4 FR103 U1 IC FAN6755
D5 FYP1010 U2 IC PC817
ZD1 P6KE150A U3 IC TL431
F1 FUSE 4A/250V
M1 VZ 9G
L1 13mH
L2 Inductor (2µH)
L3 Inductor (2µH)

FAN6755 • Rev. 1.0.0 14
Physical Dimensions
5.00 3.81
4.80 A
0.65TYP
3.81
8 5
B
6.20 1.75TYP
5.80 4.00 3.85 7.35
3.80
PIN ONE 1 4
INDICATOR
1.27
(0.33) 1.27
0.25 M C B A
LAND PATTERN RECOMMENDATION
0.25 SEE DETAIL A
0.10
0.25
1.75 MAX C
0.19
0.51 0.10 C
0.33 OPTION A - BEVEL EDGE
0.50 x 45¢X
0.25
R0.10 GAGE PLANE
R0.10 0.36
OPTION B - NO BEVEL EDGE
8¢X NOTES: UNLESS OTHERWISE SPECIFIED
0¢X A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,
DATED MAY 1990 EXCEPT PIN# 7 IS REMOVED.
0.90 SEATING PLANE B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
0.406 (1.04) FLASH OR BURRS.

D) STANDARD LEAD FINISH:
200 MICROINCHES / 5.08 MICRONS MIN.
DETAIL A LEAD/TIN (SOLDER) ON COPPER.
SCALE: 2:1
E) DRAWING FILENAME : M07AREV2
Figure 23. 7-Lead, Small Outline Package (SOP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

FAN6755 • Rev. 1.0.0 15

FAN6755 • Rev. 1.0.0 16

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FAN6755 — Highly Integrated Green-Mode PWM Controller

For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 1. Typical Application

Internal Block Diagram

Figure 2. Functional Block Diagram

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 3. Top Mark

Figure 4. Pin Configuration (Top View)

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Symbol Parameter Min. Max. Unit

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Symbol Parameter Conditions Min. Typ. Max. Units

Figure 5. VDD Behavior

Continued on the following page…

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Symbol Parameter Conditions Min. Typ. Max. Units

tVIN-Protect PWM Protect Debounce Time 60 100 140 µs

Figure 6. VIN vs. VSENSE

Continued on the following page…

Symbol Parameter Conditions Min. Typ. Max. Units

VFB-G Green-Mode Ending FB Voltage VFB-N - 0.6 V

VFB-ZDC VFB-ZDCR VFB-G VFB-N VFB

Figure 7. VFB vs. PWM Frequency

Continued on the following page…

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Symbol Parameter Conditions Min. Typ. Max. Units

Over-Temperature Protection Section (OTP)

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 9. Operation Supply Current (IDD-OP)

Figure 20. VIN vs. VLIMIT

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Startup Current Gate Output / Soft Driving

Leading-Edge Blanking (LEB)

Under-Voltage Lockout (UVLO)

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

0.25 SEE DETAIL A

0.33 OPTION A - BEVEL EDGE

8¢X NOTES: UNLESS OTHERWISE SPECIFIED

0¢X A) THIS PACKAGE CONFORMS TO JEDEC

0.406 (1.04) FLASH OR BURRS.

Figure 23. 7-Lead, Small Outline Package (SOP)

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

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