MPMC
MPMC
MPMC
a. Two
b. Three
c. Four
d. Five
Ans:c
a. One or two
c. One only
d. Two or three
Ans:b
3. Which one of the following register of 8085 microprocessor is not a part of programming model?
a. Instruction register
c. Status register
Ans:c
Stack pointer
address latch
Program counter
Ans:c
d) B and C register
Ans:A
6. Which of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-
bit register?
A 1 ,3 and 4
B. 2 ,3 and 4
C. 1,2 AND 3
D.NONE OF THESE
Ans:c
7. In 8085 microprocessor system with memory mapped I/O, which of the following is true?
C There can be maximum of 256 input devices and 256 output devices
D. Arithmetic and logic operations can be directly performed with the I/O data
a.To indicate to user that the microprocessor is working and is ready for use.
b.To provide proper WAIT states when the microprocessor is communicating with a slow
peripheral device.
c.To slow down a fast peripheral device so as to communicate at the microprocessor’s device.
I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag
a.(I) only
a.Program Counter (PC) specifies the address of the instruction last executed
12. The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of
the following?
a.Clock cycle
b.Memory cycle
c.Machine cycle
d.Instruction cycle
(co2)
a.10
b.16
c.8
d.NONE OF THESE
A. Mode1, Mode2
C. . Mode0, Mode1
D. . Mode0
A port C
B, . port B
C port A
D NONE OF THESE
A 4
B, 8
C 6
D NONE OF THESE
A 4
B,8
C 16
D 32
18 What is the meaning of the keyboard debounce unit debouncing the key entry.
A .wait for 10 ms
B, .wait for 10 s
C .wait for 1 ms
D NONE OF THESE
19 A typical 4K bit dynamic RAM chip has an internally arranged bit array of dimension
a. 64 * 64
b. 12*12
c. 32*32
d.8*8
A In-service register
B, Increase-service register
C In-standard register
D In-service rom
display
C used to count the key board matrix and
display
display
22. What is the priority of the IR0 and IR7 in the fully nested mode in 8259?
A IR7has the highest priority and IR0 has the lowest one
B, IR7 has the mid priority and IR7 has the lowest one
C IR0 has the highest priority and IR7 has the lowest one
D none of these
23. ___________ register stores the bits required to mask the interrupt inputs in 8259.
A ISR
B, IER
C IVR
D IMR
A Direct
B,Indirect
C Absolute
D none of these
(co3)
A Program ,data
B, Control, data
C Alu, data
D None of these
a) 1 byte
b) 2 bytes
c) 1 bit
d) 2 bit
27Which of the following bits is a bit of the status register that allows the microcontroller to
operate in its low power mode?
a) Z
b) Reserved
c) CPU off
d) N
d) they have one or more registers hard wired to the commonly used values
a) 4
b) 8
c) 16
d) 24
a) true
b) false
c) cant be said
a) one cycle
b) two cycles
c) four cycles
d) eight cycles
33. There are _____ number of addressing modes found for the source and _____ number of
modes for the destination part.
a) 4,4
b) 2,4
c) 4,2
d) 2,2
a) Format1 addressing
b) Format2 addressing
c) Jump addressing
a) source register
b) destination register
36 Indirect mode and the indirect auto increment mode have which common operator in them
a) +
b) –
c) @
d) &
(co4)
a) true
b) false
c) cant be said
b) more than one interrupt can share the same vector address
c) most interrupts are maskable
a) GIE=0
b) GIE=1
d) GIE=0 & 1
a) LPM0
b) LPM3
c) LPM4
42 Waking a device simply means that switching that device’s operation from a low power mode
to an active mode.
a) true
b) false
c) cant be said
a) MCLK
b) ACLK
c) CLK
b) an internal timer
c) clock to the LCD and can & also used as an interval timer
a) it is a 16 bit register
(co5)
a) CACTL1
b) CACTL2
a) 8-10 bits
b) 10-12 bits
c) 12-16 bits
d) 16-32 bits
a) The converters
53 SPI, I2C, Asynchronous serial communication are the means of communicating a processor
with its associate partners?
a) true
b) false
c) cant be said
a) less
b) same
c) more
a) SPI
b) I2C
a) yes
b) no
c) cant be said
58 In an asynchronous mode of transmission, usually the data is sent along with the
a) CLK
b) MISO
c) SDA