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    Maharana Prtap Group of Institutions Kanpur UNIT-3 (CS/EE)

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    The document contains 30 multiple choice questions about the Intel 8255 Programmable Peripheral Interface (PPI) chip and the Intel 8237 Direct Memory Access (DMA) controller chip. Some key points covered are: - The 8255 PPI has 3 ports (A, B, C) that can be configured in different modes and for input/output. - The 8237 DMA controller can perform read, write and verify transfers and uses signals like HRQ, DACK, and HLDA to coordinate bus access with the CPU. - It has multiple channels that can use fixed or rotating priority schemes to arbitrate between simultaneous transfer requests. - Registers like the current address register, current

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    Maharana Prtap Group of Institutions Kanpur UNIT-3 (CS/EE)

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    QQQQQQQQQQQAQ
    45 views3 pages
    The document contains 30 multiple choice questions about the Intel 8255 Programmable Peripheral Interface (PPI) chip and the Intel 8237 Direct Memory Access (DMA) controller chip. Some key points covered are: - The 8255 PPI has 3 ports (A, B, C) that can be configured in different modes and for input/output. - The 8237 DMA controller can perform read, write and verify transfers and uses signals like HRQ, DACK, and HLDA to coordinate bus access with the CPU. - It has multiple channels that can use fixed or rotating priority schemes to arbitrate between simultaneous transfer requests. - Registers like the current address register, current

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    UNIT-3

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    The document contains 30 multiple choice questions about the Intel 8255 Programmable Peripheral Interface (PPI) chip and the Intel 8237 Direct Memory Access (DMA) controller chip. Some key points covered are: - The 8255 PPI has 3 ports (A, B, C) that can be configured in different modes and for input/output. - The 8237 DMA controller can perform read, write and verify transfers and uses signals like HRQ, DACK, and HLDA to coordinate bus access with the CPU. - It has multiple channels that can use fixed or rotating priority schemes to arbitrate between simultaneous transfer requests. - Registers like the current address register, current

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    45 views3 pages

    Maharana Prtap Group of Institutions Kanpur UNIT-3 (CS/EE)

    Uploaded by

    QQQQQQQQQQQAQ
    The document contains 30 multiple choice questions about the Intel 8255 Programmable Peripheral Interface (PPI) chip and the Intel 8237 Direct Memory Access (DMA) controller chip. Some key points covered are: - The 8255 PPI has 3 ports (A, B, C) that can be configured in different modes and for input/output. - The 8237 DMA controller can perform read, write and verify transfers and uses signals like HRQ, DACK, and HLDA to coordinate bus access with the CPU. - It has multiple channels that can use fixed or rotating priority schemes to arbitrate between simultaneous transfer requests. - Registers like the current address register, current

    Copyright:

    © All Rights Reserved
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    of 3

    MAHARANA PRTAP GROUP OF INSTITUTIONS KANPUR

    UNIT- 3(CS/EE)

    1. In 8259 PIC, the register that stores all the interrupt requests in the register_____

    A: Interrupt Request Register B: In-Service Register C: Priority resolver D: Interrupt Mask


    Register

    2.In 8255 PPI, BSR mode is where individual bits of __________can be set/reset.

    A: Port B B: Port C C: Port A D: Port A & Port B

    3.In 8255, under the I/O mode of operation we have __ modes. Under which mode will have the
    following features i) A 5 bit control port is available. ii) Three I/O lines are available at Port C.

    a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2

    4.What must be the contents of the control word of Intel 8255 for Mode 0 (operation) and for the
    following ports configuration : Port A-output, Port B-output, Port Clower-Output, Port Cupper-
    input (A) 85 H (B) 86 H (C) 87 H (D) 88 H

    5.Which of the following mode of 8255 is Strobed Bi-directional I/O?

    A. Mode 0 B. Mode 1 C. Mode 2 D. Mode 4

    6.In SFNM which of the following statement is correct?

    A)When servicing an interrupt request from slave, the slave is not allowed to place any further
    requests. B) When servicing an interrupt request from a slave , the slave the slave is allowed to
    place further request C) Sometimes A sometimes B D) Cannot predict

    7.In automatic rotation , the device , after being serviced , receives the ________ priority

    A Lowest B Highest C Intermediate D Cannot predict

    8.Which port of 8255 works in all three modes

    Port A Port B Port C

    9.Which port of the 8255 PPI is capable of performing the handshaking function with the
    interfaced devices?

    a. Port A
    b. Port B
    c. Port C
    D.All of the above

    10. The 8237 is able to accomplish the operation of

    a) verifying DMA operation b) write operation c) read operation d) all of the mentioned

    11.The 8237 can accomplish three types of operations and they are

    A) verify DMA operation B) write operation C) read operation

    12.The bus is available when the DMA controller receives the signal

    a) HRQ b) HLDA c) DACK d) all of the mentioned

    13. To indicate the I/O device that its request for the DMA transfer has been honoured by
    theCPU, the DMA controller pulls

    a) HLDA signal b) HRQ signal c) DACK (active low) d) DACK (active high)

    14. If more than one channel requests service simultaneously, the transfer will occur as

    a) multi transfer b) simultaneous transfer c) burst transfer d) none of the mentioned

    15. The continuous transfer may be interrupted by an external device by pulling down the signal

    a) HRQ b) DACK (active low) c) DACK (active high) d) HLDA Answer

    16 . The number of clock cycles required for a 8237 to complete a transfer is

    a) 2 b) 4 c) 8 d) none of the

    17 . In 8237, if each device connected to a channel is assigned to a fixed priority then it is said to
    be in

    a) rotating priority scheme b) fixed priority scheme c) rotating priority and fixed priority scheme
    d) none of the mentioned

    1 8. The priority of the channels varies frequently in a) rotating priority scheme b) fixed priority
    scheme c) rotating priority and fixed priority scheme d) none of the mentioned

    1 9. The register of 8237 that can only be written in is a) DMA address register b) terminal count
    register c) mode set register d) status register

    20. The operation that can be performed on the status register is

    a) write operation b) read operation c) read and write operations d) none of the mentioned

    21. The block of 8237 that decodes the various commands given to the 8237 by the CPU is
    a) timing and control block b) program command control block c) priority block d) none of the
    mentioned

    22. The priority between the DMA channels requesting the services can be resolved by

    a) timing and control block b) program command control block c) priority block d) none of the
    mentioned

    2 3. The register that holds the current memory address is

    a) current word register b) current address register c) base address register d) command register

    24. The register that holds the data byte transfers to be carried out is

    a) current word register b) current address register c) base address register d) command register

    25. When the count becomes zero in the current word register then a) input signal is enabled b)
    output signal is enabled c) EOP (end of process) is generated d) start of process is generated

    2 6. The current address register is programmed by the CPU as

    a) bit-wise b) byte-wise c) bit-wise and byte-wise d) none of the mentioned

    27. Which of these register‟s contents is used for auto-initialization (internally)?

    a) current word register b) current address register c) base address register d) command register

    28. The register that maintain an original copy of the respective initial current address register
    and current word register is

    a) mode register b) base address register c) command register d) mask register

    29. The register that can be automatically incremented or decremented, after each DMA transfer
    is a) mask register b) mode register c) command register d) current address register

    30. Which of the following is a type of DMA transfer?

    a) memory read b) memory write c) verify transfer d) all of the mentioned

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