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1. In 8085 microprocessor, how many interrupts are maskable.

a. Two

b. Three

c. Four

d. Five

Ans:c

2. In an instruction of 8085 microprocessor, how many bytes are present?

a. One or two

b. One, two or three

c. One only

d. Two or three

Ans:b

3. Which one of the following register of 8085 microprocessor is not a part of programming model?

a. Instruction register

b. Memory address register

c. Status register

d. Temporary data register

Ans:c

4. In a Microprocessor, the address of the new next instruction to be executed is stored in

Stack pointer

address latch

Program counter

General purpose register

Ans:c

5 The term PSW Program Status word refers

a) Accumulator & Flag register

c) Accumulator & Instruction register

d) B and C register

Ans:A

6. Which of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-
bit register?

A 1 ,3 and 4

B. 2 ,3 and 4

C. 1,2 AND 3

D.NONE OF THESE

Ans:c

7. In 8085 microprocessor system with memory mapped I/O, which of the following is true?

A Devices have 8-bit address line

B. Devices are accessed using IN and OUT instructions

C There can be maximum of 256 input devices and 256 output devices

D. Arithmetic and logic operations can be directly performed with the I/O data

8. In an intel 8085A microprocessor, why is READY signal used?

a.To indicate to user that the microprocessor is working and is ready for use.

b.To provide proper WAIT states when the microprocessor is communicating with a slow
peripheral device.

c.To slow down a fast peripheral device so as to communicate at the microprocessor’s device.

d.None of the above

9. consider the following

I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag

Which one of the above flags is/are present in 8085 microprocessor?

a.(I) only

b.(I) & (II)

c.(II) & (III)

d.(I) ,(III) & (IV)

a.Accumulator, temporary register, arithmetic and logic circuits

b.Accumulator, arithmetic, logic circuits and five flags

c.Accumulator, arithmetic and logic circuits

d.Accumulator, temporary register, arithmetic, logic circuits and five flags

11. Which of the following statements for Intel 8085 is correct?

a.Program Counter (PC) specifies the address of the instruction last executed

b.PC specifies the address of the instruction being executed

c.PC specifies the address of the instruction to be executed

d.PC specifies the number of instructions executed so far

12. The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of
the following?

a.Clock cycle

b.Memory cycle

c.Machine cycle

d.Instruction cycle

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13. 8259 supports ________ devices for interruption

a.10

b.16

c.8

d.NONE OF THESE

14. Name the modes in which port A of 8255 can be operated.

A. Mode1, Mode2

B, . Mode0, Mode1, Mode2

C. . Mode0, Mode1

D. . Mode0

15. Which port of 8255 is used in handshaking?

A port C

B, . port B
C port A

D NONE OF THESE

16. . 8254 supports _______ number of Programmable Counter Modes

A 4

B, 8

C 6

D NONE OF THESE

17. The size of the counters in 8254 is ____.

A 4

B,8

C 16

D 32

18 What is the meaning of the keyboard debounce unit debouncing the key entry.

A .wait for 10 ms

B, .wait for 10 s

C .wait for 1 ms

D NONE OF THESE

19 A typical 4K bit dynamic RAM chip has an internally arranged bit array of dimension

a. 64 * 64

b. 12*12

c. 32*32

d.8*8

20. ISR in 8259 stands for ________.

A In-service register

B, Increase-service register

C In-standard register

D In-service rom

21. What is the use of scan lines in 8279?

A used to scan the only display

B, used to scan the key board matrix and

display
C used to count the key board matrix and

display

D used to create the key board matrix and

display

22. What is the priority of the IR0 and IR7 in the fully nested mode in 8259?

A IR7has the highest priority and IR0 has the lowest one

B, IR7 has the mid priority and IR7 has the lowest one

C IR0 has the highest priority and IR7 has the lowest one

D none of these

23. ___________ register stores the bits required to mask the interrupt inputs in 8259.

A ISR

B, IER

C IVR

D IMR

24. All jump/branch instructions in 8085 use ____________addressing

A Direct

B,Indirect

C Absolute

D none of these

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25. . Von Neumann architecture has ____________and ____________ memory is same.

A Program ,data

B, Control, data

C Alu, data

D None of these

26. The status register in MSP430 consists of

a) 1 byte

b) 2 bytes

c) 1 bit

d) 2 bit
27Which of the following bits is a bit of the status register that allows the microcontroller to
operate in its low power mode?

a) Z

b) Reserved

c) CPU off

d) N

28 What is actually done to improve the efficiency of a RISC processor?

a) instructions are reduced

b) they have two or more processors inbuilt connected between

c) they have many instructions that are interrelated to each other

d) they have one or more registers hard wired to the commonly used values

29Their are_______________ number of emulated instructions found in the MSP430?

a) 4

b) 8

c) 16

d) 24

30 Pre increment addressing is available in MSP430?

a) true

b) false

c) cant be said

d) depends on the conditions

31 dadd instruction can act as _____________

a) valid BCD addition

b) valid adder with carry

c) all of the mentioned

d) none of the mentioned

32. mov.w R3, R4 takes _________

a) one cycle

b) two cycles

c) four cycles
d) eight cycles

33. There are _____ number of addressing modes found for the source and _____ number of
modes for the destination part.

a) 4,4

b) 2,4

c) 4,2

d) 2,2

34 MSP430 describes reti instruction as ___________

a) Format1 addressing

b) Format2 addressing

c) Jump addressing

d) None of the mentione

35 Indirect register mode is used by _________

a) source register

b) destination register

c) source & destination register

d) none of the mentioned

36 Indirect mode and the indirect auto increment mode have which common operator in them

a) +

b) –

c) @

d) &

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37MSP430 uses vectored interrupts?

a) true

b) false

c) cant be said

d) depends on the conditions

38Which of the following is true?

a) interrupts are required to wake a CPU from sleep

b) more than one interrupt can share the same vector address
c) most interrupts are maskable

d) all of the mentioned

39 What is the function of ________interrupt keyword.

a) it is used to enable the interrupt

b) it is used to disable the interrupt

c) it is used to assign a particular address to a vector

d) all of the mentioned

40 For enabling any interrupt, firstly

a) GIE=0

b) GIE=1

c) None of the mentioned

d) GIE=0 & 1

41 Which of the following are the low power modes?

a) LPM0

b) LPM3

c) LPM4

d) All of the mentioned

42 Waking a device simply means that switching that device’s operation from a low power mode
to an active mode.

a) true

b) false

c) cant be said

d) depends on the conditions

43 The only clock that runs in the LPM3 is the ___________

a) MCLK

b) ACLK

c) CLK

d) None of the mentioned

44 P1.3 is the ___________

a) input CCI1A to Timer_A

b) is connected to the voltage reference VREF of SD16_A

d) are digital inputs with pull-up resistors

45 Which out of the following is the main function of a Watchdog timer?

a) control the compare mode

b) control the capture mode

c) protection from failures to the system

d) all of the mentioned

46 Basic Timer1 can provide __________

a) clock for the LCD

b) an internal timer

c) clock to the LCD and can & also used as an interval timer

d) none of the mentioned

47 Which of the following is correct about WDTCTL?

a) it is a 16 bit register

b) it is guided against accidental writes that require a password

c) a reset will occur if a value with an incorrect password is written to WDTCTL

d) all of the mentioned

48 WDTIFG flag gets cleared if

a) if is interrupt had occurred

b) if the interrupt is serviced

c) if there can be no interrupt

d) all of the mentioned

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49 Comparator_A+ is controlled by which of the following peripheral registers?

a) CACTL1

b) CACTL2

c) CACTL1 & CACTL2

d) None of the mentioned

50 Flag CAIFG is raised,

a) at a low level triggered pulse

b) at a high level triggered pulse

d) at the falling or rising edge of the pulse

51 The successive approximation converters have a resolution of _________

a) 8-10 bits

b) 10-12 bits

c) 12-16 bits

d) 16-32 bits

52 ADC10 and ADC12 are _________

a) The converters

b) SAR modules available in the MSP430

c) Sigma delta modules available in the MSP430

d) Comparator modules available in the MSP430

53 SPI, I2C, Asynchronous serial communication are the means of communicating a processor
with its associate partners?

a) true

b) false

c) cant be said

d) depends on the condition

54 SPI needs______ wires than I2C?

a) less

b) same

c) more

d) depends on the conditions

55 Timer_A is used in _________

a) SPI

b) I2C

c) Asynchronous Serial Communication

d) All of the mentioned

56 Pull-up resistors Rp keep the lines at VCC when _____________

a) all the drivers are active

b) none of the drivers are active

d) none of the drivers is at sleep

57 Is baud rate selected in I2C?

a) yes

b) no

c) cant be said

d) depends on the conditions

58 In an asynchronous mode of transmission, usually the data is sent along with the

a) the start bit

b) the stop bit

c) the start & stop bit

d) none of the mentioned

59 BITCLK16 is the ________

a) sampling clock in the undersampling mode

b) sampling clock in the oversampling mode

c) quantising clock in the undersampling mode

d) quantising clock in the oversampling mode

60 The I2C bus uses which of the following lines?

a) CLK

b) MISO

c) SDA

d) All of the mentioned