RD/RDC Series Converters Applications Manual MN-19220XX-001

RD/RDC
Series Converters
Applications Manual
MN-19220XX-001
(RDC-19220/2, RDC-19220/2S, RDC-19224,
RD-19230, RD-19240 Series)
The information provided in this Applications Manual is believed to be accurate;

however, no responsibility is assumed by Data Device Corporation for its use, and no
license or rights are granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
Please visit our Web site at www.ddc-web.com for the latest information
105 Wilbur Place, Bohemia, New York 11716-2426
For Technical Support – 1-800-DDC-5757 ext. 7771

Headquarters U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358
Southeast U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610
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United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
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Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web – http://www.ddc-web.com
U
®
All rights reserved. No part of this manual may be

reproduced or transmitted in any form or by any
means, electronic, mechanical, photocopying, Rev K, March, 2007
recording, or otherwise, without the prior written
permission of Data Device Corporation. © 1998 Data Device Corporation
RECORD OF CHANGE
Revision Date Pages Description
E 11/2003 All Major rewrite
F 05/2005 All Major rewrite
G 06/2005 Cover Page Added applicable product numbers to title.
H 07/2005 All Remove all Space notations other typos
J 04/2006 All Major Update, Remove Class K
K 03/2007 Various Replace Figure 8, various copy changes
PURPOSE
The purpose of this application manual is to aid engineers and technicians in the proper
application of the RD/RDC Series Synchro/Resolver-to-Digital converters. This manual is
divided into sections, each of which are described briefly below:
The Introduction gives a brief overview of different operating modes. Common applications are
shown and discussed.
The Basics and Series Overview sections detail the general operation of the converter including
required power supplies, input and reference signals, and timing.
A System Design section offers a design checklist and discusses some common parameters to
consider when designing with the RDC-19220/2/4, RDC-19220/2S, RD-19230, and RD-19240
series converters.
The Enhancements section contains discussions such as performance versus design decisions,
and ‘changing resolution on-the-fly.’ Sample calculations are provided to aid in modeling the
converter in specific applications.
A Testing and Troubleshooting section is provided to aid in diagnosing performance problems

and common pitfalls to be avoided.
The Synchro/Resolver Conversion Theory Section discuss Synchro/Resolver conversion

concepts.
Finally, the Mechanical Specifications section consists of outline drawings and pin-out tables for
the converters, as well as the relevant thin-film resistor networks and transformers
recommended.
Data Device Corporation i RD/RDC Series Manual

Attention!
The RD/RDC Converters are static-sensitive devices and should be

handled at static-safe workstations.
Data Device Corporation ii RD/RDC Series Manual

Table of Contents
PURPOSE ..................................................................................................................................................... I
HOW TO USE THIS GUIDE ........................................................................................................................IX

Text Usage............................................................................................................................................... ix
Symbols and Icons................................................................................................................................... ix
Special Handling and Cautions................................................................................................................. x
Trademarks ............................................................................................................................................... x
INTRODUCTION .......................................................................................................................................... 1
Package Options....................................................................................................................................... 4
THE BASICS ................................................................................................................................................ 5
Power Supplies ......................................................................................................................................... 6
+5 and –5 Volt Operation ...................................................................................................................... 7
+5 Volt Only Operation .......................................................................................................................... 7
Typical -5 Volt Circuits........................................................................................................................... 7
Input Signal Conditioner Options .............................................................................................................. 8
Input Signal Configurations ....................................................................................................................... 9
Signal Connections ................................................................................................................................... 9
Synchro Mode Connect S1, S2, S3....................................................................................................... 9
Resolver Mode Connect ........................................................................................................................ 9
Resistor Tolerance and Imbalance Matching.......................................................................................... 10
Direct 2v Resolver And X-Volt Resolver.............................................................................................. 13
Differential Resolver ............................................................................................................................ 16
Synchro Input ...................................................................................................................................... 18
Linear Variable Differential Transformer (LVDT)................................................................................. 19
Rescaling Example For 3-Wire LVDT.............................................................................................................. 21
-Full-Scale Travel Example (-FS) .................................................................................................................... 22
Scaling Circuit for a 2-Wire LVDT.................................................................................................................... 23
Rescaling Example For 2-Wire LVDT.............................................................................................................. 24
Inductosyn® .......................................................................................................................................... 26
DC Inputs............................................................................................................................................. 28
Reference Input Configurations .............................................................................................................. 29
Reference Input ................................................................................................................................... 29
Synthesized Reference ....................................................................................................................... 30
Quadrature Voltage and Phase-Shift .................................................................................................. 31
Additional Sources of Error.................................................................................................................. 32
Phase-Shift Correction (RDC-19220/2/4) (For converters without synthesized ref) .......................... 33
Transformer Isolation........................................................................................................................... 34
Mandatory External Components ........................................................................................................... 36
Calculating External Component Values............................................................................................. 36
Component Value Selection Programs................................................................................................... 40
External Component Selection Guidelines ............................................................................................. 40
Design Guidelines for Bandwidth Components................................................................................... 43
Optional Bandwidth Components (RD-19230 and RD-19240) ............................................................... 44
Shift (RD-19230 and RD-19240)............................................................................................................. 44
UP /DN (RD-19230 and RD-19240)........................................................................................................ 45
Benefit of Switching Resolution on the Fly (RD-19230 and RD-19240) ................................................. 45
Switch On the Fly Implementation (RD-19230/RD-19240) ................................................................. 46
Data Device Corporation iii RD/RDC Series Manual

TABLE OF CONTENTS
Dual Bandwidths ..................................................................................................................................47

Transfer Function And Bode Plot ............................................................................................................49
Type II Tracking Converters ....................................................................................................................52
Resolution Control (RDC-19220/2/4, RDC-19220/2S “A” & “B” & RD-19230, RD-19240 “D1” & “D2”)..54
Binary-To-Decimal Conversion................................................................................................................55
Encoder Emulation (RDC-19220/2/4 Series) ..........................................................................................56
Encoder Emulation (RD-19230 & RD-19240 Series) ..............................................................................58
Clarification of A_QUAD_B , U/B and ZIP_EN Functions ..................................................................58
Velocity Output ........................................................................................................................................61
Velocity Ripple .....................................................................................................................................63
Using Velocity Output to Monitor Speed ..............................................................................................63
Built-In Test (BIT).....................................................................................................................................64
Timing ......................................................................................................................................................65
Converter Busy (CB) Timing ................................................................................................................65
Timing ......................................................................................................................................................66
Timing For Reading Digital Output Data..............................................................................................66
Data Transfer To an 8-Bit Bus ......................................................................................................................... 66
Data Transfer To a 16-Bit Bus ......................................................................................................................... 68
Interfacing the RD/RDC with an IBM PC/XT/AT®............................................................................................ 69
RD/RDC to IBM PC/XT/AT Theory of Operation ............................................................................................. 69
SYSTEM DESIGN.......................................................................................................................................72
Typical System Design Example Using the RDC-19220/2/4 ..................................................................72
Grounding Tips ........................................................................................................................................77
Layout Considerations.............................................................................................................................77
Transient Protection.................................................................................................................................78
ENHANCEMENTS ......................................................................................................................................80
Bandwidth ................................................................................................................................................80
Bandwidth vs. Resolution.....................................................................................................................80
Bandwidth vs. Carrier Frequency.........................................................................................................80
Bandwidth vs. Input Signal Amplitude..................................................................................................80
Bandwidth Optimization .......................................................................................................................81
Acceleration Lag ......................................................................................................................................82
Large Step (179°) Settling Time ..............................................................................................................84
Maximum Tracking Rate and Internal Sampling Frequency ...................................................................86
Changing Resolution On The Fly (RDC-19220/2/4 & RDC-19220/2S Series)........................................87
Changing Resolution On The Fly (RD-19230 & RD-19240 Series) ........................................................88
Error Minimizing for the RDC-19220/2/4 & S Series during Resolution Switching..............................88
Two-Speed Resolver Applications...........................................................................................................90
Two-Speed Resolution.........................................................................................................................91
Two Speed Accuracy ...........................................................................................................................91
User-Written Software..........................................................................................................................92
Synchro/Resolver-to-DC Conversion ......................................................................................................94
SEU/SEL Solutions..................................................................................................................................95
Preface ....................................................................................................................................................95
Suggested Design Approach...................................................................................................................95
TESTING AND TROUBLESHOOTING ......................................................................................................96
Testing the RD/RDC Series Converters in a System ..............................................................................96
Troubleshooting .......................................................................................................................................98
Troubleshooting Checklist....................................................................................................................98
Troubleshooting Symptoms and Solutions ..........................................................................................99
Data Device Corporation iv RD/RDC Series Manual

TABLE OF CONTENTS
SYNCHRO/RESOLVER CONVERSION THEORY.................................................................................. 105
QUALITY REPORTS-MTBF REPORTS.................................................................................................. 111
MECHANICAL SPECIFICATIONS .......................................................................................................... 112

RD/RDC Series Pin Out Tables ............................................................................................................ 117
Transformers......................................................................................................................................... 122
GLOSSARY.............................................................................................................................................. 124
INDEX ....................................................................................................................................................... 126
Data Device Corporation v RD/RDC Series Manual

Lists of Figures
Figure 1. Typical Application........................................................................................................ 1
Figure 2. RDC-19220/2/4 Series Block Diagram ......................................................................... 2
Figure 3. RDC-19220/2S Series Block Diagram.......................................................................... 2
Figure 4. RD-19230/RD-19240 Series Block Diagram ................................................................ 3
Figure 5. Power Supply Set-Up for RD-19230 or RD-19240 (+5VDC P/S Operation)................. 6
Figure 6. Typical -5 Volt Circuits .................................................................................................. 7
Figure 7. DDC-49530 Layout ..................................................................................................... 12
Figure 8. Direct Input To RDC-19220 (40-pin DDIP) ................................................................. 13
Figure 9. Direct Input To RDC-19222 (44-pin J-Lead)............................................................... 14
Figure 10. Typical Connections, 2V Resolver, Direct Input, RD-19230/RD-19240.................... 14
Figure 11. X-Volt resolver, Example using Direct Input to RDC-19220 (40-pin DDIP) ............... 15
Figure 12. Differential Resolver Input using DDC-49530 (11.8 V), 57470 (11.8 V), 49590 (90 V),
or 73089 (2V) ....................................................................................................................... 17
Figure 13. Synchro Input, using DDC-49530 , 57470, 49590, or 73089..................................... 18
Figure 14. LVDT Output vs. Typical RDC-19220 Series Input.................................................... 19
Figure 15. 3-Wire LVDT Scaling Circuit ...................................................................................... 20
Figure 16. LVDT.......................................................................................................................... 21
Figure 17. 3-Wire LVDT Direct Input........................................................................................... 22
Figure 18. 2-Wire LVDT Scaling Circuit ...................................................................................... 23
Figure 19. Inductosyn®-To-Digital Converter System ................................................................ 26
Figure 20. Dual Matched Differential Amplifier ........................................................................... 27
Figure 21. Differential Resolver Input and Reference Scaling Resistors (Example using RDC-
19220) .................................................................................................................................. 29
Figure 22. Quadrature and Harmonics ....................................................................................... 32
Figure 23. Phase Shift Compensation ........................................................................................ 33
Figure 24. Transformer Connection Diagrams............................................................................ 35
Figure 25. Input Wiring – Switch On The Fly Between 12 and 14 Bit Resolution ....................... 47
Figure 26. Benefit of Switching Resolution On the Fly................................................................ 48
Figure 27. Transfer Function Block Diagram .............................................................................. 49
Figure 28. Bode Plot ................................................................................................................... 49
Figure 29. Filtered/Buffered Encoder Emulator .......................................................................... 56
Figure 30. Output Timing ............................................................................................................ 57
Figure 31. Incremental Encoder Emulation Resolution Control .................................................. 60
Figure 32. Incremental Encoder Emulation................................................................................. 60
Figure 33. Timing for Incremental Encoder Emulation Resolution Control ................................. 60
Figure 34. Velocity Specifications ............................................................................................... 62
Figure 35. Velocity Ripple Filter .................................................................................................. 63
Figure 36. Example Of Velocity Output Speed Monitor .............................................................. 63
Figure 37. Converter Busy Timing .............................................................................................. 65
Figure 38. Output Data Latch Configuration ............................................................................... 65
Figure 39. Data Transfer to 8 Bit Bus ......................................................................................... 67
Figure 40. Timing for Data Transfer To 8-Bit Bus (RDC-19220/2).............................................. 67
Figure 41. RD-19230/RD-19240 Timing: CB and INHIBIT ......................................................... 68
Figure 42. Data Transfer To 16-Bit Bus ...................................................................................... 70
Figure 43. PC Application – I/O Read Cycle Timing ................................................................... 70
Data Device Corporation vi RD/RDC Series Manual

LIST OF FIGURES
Figure 44. RD/RDC to PC Connection Diagram ......................................................................... 71

Figure 45. Mandatory External Component Values and Connections ........................................ 73
Figure 46. Reference Input Scaling Resistors ............................................................................ 74
Figure 47. Input Signal Scaling Resistor Placement................................................................... 75
Figure 48. Power Supply Set-up ................................................................................................. 76
Figure 49. Complete System Design Example Circuitry ............................................................. 77
Figure 50. Voltage Transient Suppressor, 90V Synchro Input.................................................... 79
Figure 51. Voltage Transient Suppressor, 90V Resolver Input................................................... 79
Figure 52. Examples of Settling Time ......................................................................................... 85
Figure 53. External Circuitry for Resolution Switching................................................................ 89
Figure 54. Two-Speed Resolvers ............................................................................................... 90
Figure 55. Two-Speed Example using 1:4 Ratio ........................................................................ 90
Figure 56. Synchro/Resolver-to-DC Conversion......................................................................... 94
Figure 57. Sampled Sinusoidal Wave......................................................................................... 99
Figure 58. DDC Components’ Utilization in a Two-Axis Antenna Application.......................... 105
Figure 59. Closed Loop Servo Model ....................................................................................... 108
Figure 60. Resolver-to-Digital Conversion Block Diagram........................................................ 109
Figure 61. RDC-19220 DDIP Ceramic Package....................................................................... 112
Figure 62. RDC-19222 J-LEAD Plastic Package...................................................................... 113
Figure 63. RDC-19222 J-LEAD Ceramic Package ................................................................... 113
Figure 64. RDC-19222S (44 Pin Plastic J-Lead) Mechanical Outline....................................... 114
Figure 65. RD-19230 Mechanical Outline................................................................................. 114
Figure 66. RDC-19224 Mechanical Outline .............................................................................. 115
Figure 67. RD-19240LS Mechanical Outline ............................................................................ 116
Figure 68. RD-19240FS Mechanical Outline ............................................................................ 116
Figure 69. Reference Transformer Mechanical Outline and Schematic (B-246) ...................... 122
Figure 70. Transformer Layout and Schematic (Syn Input - 52034/52035).............................. 122
Figure 71. Transformer Layout and Schematic (Res Input - 52036/52037/52038)................... 123
Figure 72. 60 Hz Transformer Mechanical Outline – (Syn Input – 52039, Ref Input - 24133) .. 123
Data Device Corporation vii RD/RDC Series Manual

Lists of Tables
Table 1. Selection Criteria............................................................................................................ 4
Table 2. Input Signal Configuration Options ................................................................................ 8
Table 3. Resistor Imbalance vs. Output Error............................................................................ 10
Table 4. Precision Thin-film Resistor Network Specifications.................................................... 10
Table 5. DDC-49530 RESISTOR VALUES (11.8 V INPUTS) ................................................... 12
Table 6. Example of LVDT Output ............................................................................................. 21
Table 7. LVDT Resolution Control ............................................................................................. 24
Table 8. Digital Output Of The RD/RDC Series In LVDT Mode................................................. 25
Table 9. Transformers................................................................................................................ 34
Table 10. Maximum Tracking Rate And Carrier Frequency Versus Resolution ........................ 37
Table 11. Tracking / BW Relationship......................................................................................... 38
Table 12. Carrier Frequency (Max) in KHz (Example Only) ....................................................... 40
Table 13. Maximum Tracking Rate (Min) in RPS (Example Only).............................................. 42
Table 14. Tracking / BW Relationship Example.......................................................................... 42
Table 15. Precharge Amplifier Gain Programming ..................................................................... 45
Table 16. Output Data For A Synchro Or Resolver .................................................................... 53
Table 17. Binary Angle Relationships ......................................................................................... 54
Table 18 A_QUAD_B (Pin 30) Function ........................................................................................ 59
Table 19. ZIP_EN (Pin 55) Function ............................................................................................. 59
Table 20. Converter Busy Pulse Width ....................................................................................... 65
Table 21. Converter Busy Pulse Width ....................................................................................... 66
Table 22. Maximum Bandwidth per Resolution .......................................................................... 80
Table 23. Counts per Rotation and Time Constraints For Various Resolutions ......................... 85
Table 24. Binary Look-up Chart .................................................................................................. 91
Table 25. Simulating Angles Using a Single Reference Source ................................................. 96
Table 26. Output Angular Bit Weights for LVDT Inputs .............................................................. 97
Table 27. Synchro Input Swapping ........................................................................................... 104
Table 28. Resolver Input Swapping .......................................................................................... 104
Table 29. RDC-19220/19220S Pin Outs (40-pin) ..................................................................... 117
Table 30. RDC-19222/19222S Pin Outs (44-pin) ..................................................................... 118
Table 31. RDC-19224 Pin Outs (44-pin)................................................................................... 119
Table 32. RD-19230 Pin Outs................................................................................................... 120
Table 33. RD-19240 Pin Outs................................................................................................... 121
Data Device Corporation viii RD/RDC Series Manual

HOW TO USE THIS GUIDE
This User’s Guide employs typographical and iconic conventions to assist the reader in
identifying content. The ‘Scholar Margin’ in the left-hand column of each page contains easily-
identifiable icons to indicate the presence of tips, references, or cautions.
Text Usage
BOLD–indicates important information and table, figure, and chapter references.
BOLD ITALIC–designates DDC Part Numbers.
Courier New–indicates code examples.
<…> - indicates user-entered text or commands.
Symbols and Icons
The Idea/Tip icon signifies useful supplementary information.
The Note Icon signifies important supplementary information.
The Caution icon identifies information to avoid possible damage

to the product.
The Warning icon alerts the reader to hazards that will cause
damage to the product and possible injury to the user.
The Reference icon indicates related material in this User’s

Guide or in another specified document.
The Disk Icon describes software-related information.
Data Device Corporation ix RD/RDC Series Manual

HOW TO USE THIS MANUAL
Special Handling and Cautions

The RD/RDC Converters use state-of-the-art components, and proper care
should be used to ensure that the device will not be damaged by Electrical
Static Discharge (ESD), physical shock, or improper power surges and that
precautions are taken to avoid electrocution.
Ensure that standard ESD precautions are followed. As a minimum, one

hand should be grounded to the power supply in order to equalize the static
potential.
Trademarks
All trademarks are the property of their respective owners.
Data Device Corporation x RD/RDC Series Manual

INTRODUCTION
The RD/RDC Series Converter’s are used for motion control feedback and
position speed monitoring. The three converters are very similar and most
applications and figures shown will apply to all series unless otherwise noted.
RESOLVER IN A SYSTEM
REF
REFERENCE
LEVEL
EQUIPMENT CONDITIONER
WITH RESOLVER 'N' BITS
ROTATING
SHAFT
θ
S1
INPUT
S2 R/D DIGITAL
LEVEL
CONVERTER PROCESSING
CONDITIONER S3
S4
Figure 1. Typical Application
The function of the RD/RDC series is to convert the amplitude signal from a
Synchro or Resolver (or LVDT/RVDT; See the Input Signal Configurations
discussion on page 9) to a digital angle and velocity. For static or slow
moving input changes the converter can be designed into the application
effortlessly. However, where rates of change at the input are high and the
device is part of a control loop, setting of dynamic parameters and bandwidth
should be assessed (see the Enhancements Section).
Data Device Corporation 1 RD/RDC Series Manual

INTRODUCTION
To understand the modes of operation, the following diagram divides the

converter in several portions that will be discussed throughout this manual.
Please note:
external
components are
necessary for
the converter to
operate.
Figure 2. RDC-19220/2/4 Series Block Diagram
Figure 3. RDC-19220/2S Series Block Diagram

INTRODUCTION
Cbw Rb
V V Cbw/10
E E Rb
L L
S S Cbw
RH RL BIT
J J
1 2 Cbw/10
VEL2 VEL1
SYNTHESIZED SHIFT
SIN REFERENCE
-S -
+S +
CONTROL
Please note: COS TRANSFORMER
GAIN DEMODULATOR - VEL
the external -C - +
+C + D1 D0
components are RV
D1
necessary for VDDP
UP/DOWN
HYSTERESIS
PCAP -5 V VCO
the converter to NCAP INVERTER
D0 COUNTER
&
-VCO
operate. VSSP TIMING R CLK
AGND
VDD INTERNAL
DATA R SET
GND LATCH ENCODER
EMULATION
VSS
INH EM EL D1 D0 A QUAD B A U/B CB/ZIP UP/DN

RD-19230 BIT 1 - BIT 16 ZIP_EN
RD-19240 BIT 1 - BIT 14
Figure 4. RD-19230/RD-19240 Series Block Diagram
The most critical portion of the circuit design is the external components. If
the external components are not connected the device will not function.
The RD/RDC component selection software is available to aid in selecting
these components. This is further discussed in the Mandatory External
Components section.
The RD-19230/RD-19240 converters are very similar to the RDC-19220

converter with the exception of the RD-19230 has circuits for a dual
bandwidth, switch on the fly and internal encoder emulation, and max ref
frequency specifications are different.
For product specification tables, refer to our Web site at www.ddc-web.com

to obtain the current data sheets.

Package Options
Table 1. Selection Criteria

Required Package Number Mandatory Use
Power Type Of Pins External Model
Supplies Components Number
+ 5 VDC RS, RB , RV , RDC-19220
DDIP 40
- 5 VDC CBW and CBW/10 RDC-19220S
+ 5 VDC Only
RS, RB, RV ,
OR MQFP 44 RDC-19224
CBW, and CBW/10
±5 VDC
+ 5 VDC Only RS, RB, RV ,
RDC-19222
OR J - Lead 44 CBW, CBW/10 and
RDC-19222S
±5 VDC 47μF*
+ 5 VDC Only RS, RB, RV ,
OR Quad Flat Pack 64 CBW, CBW/10 and RD-19230
±5 VDC 47μF*, 10μF*
+ 5 VDC Only LPCC 64 Pads RS, RB, RV ,
OR CBW, CBW/10 and RD-19240
±5 VDC MQFP 52 47μF*, 10μF*
*for +5V only operation

THE BASICS
This section covers basic design considerations for proper application of the
RD/RDC converters. Below is a summation of the topics covered in the
remainder of the basics section.
Power Supplies
The RDC-19220 and RDC-19220S converters require both +5 VDC and -5
VDC supplies. The RDC-19222/4, RDC-19222S, RD-19230, and the RD-
19240 converters can operate from a single +5 volt supply. This is
accomplished by using the four additional pins to connect two external
capacitors to develop the -5 volt needed for operation.
Input Signal Configurations

The signal input of the device may be configured for:
• 2 Vrms direct SIN/COS input
• resolver
• synchro
• linear variable differential transformer (LVDT)
• Inductosyn®
• DC SIN/COS
Reference Input Configurations

The reference source may require scaling and phase-shift compensation.
Mandatory External Components

See Table 1.
Transfer Function and Bode Plot

The dynamic performance of the converter can be determined from the
transfer function and Bode plot.
Configurations
Consult specific converter data sheet for the following configurations:
• direct/synchro/resolver
• DC
• LVDT position information bit weight
• encoder emulation
• velocity
Built-In Test (BIT)

The built-in test is an output flag that can be used to indicate a fault condition.

THE BASICS
Power Supplies
In addition to the physical package differences, these converters also differ

electrically in their power supply requirements as outlined below:
RDC-19220 and RDC-19220S - 40-pin DDIP (through hole)
• requires both +5 VDC and -5 VDC power supplies to operate
For +5 VDC P/S operation only:
RDC-19222, RDC-19224, RDC-19222S (refer to Figure 48) - 44-pin J-lead

(surface mount) & RD-19230 or RD-19240 (refer to Figure 5)
• requires only a single +5 VDC supply

• has the capability of producing a -5 VDC supply internally
Although the RDC-19222, RDC-19224, RDC-19222S, RD-19230 and RD-

19240 are capable of producing an internal -5 VDC supply, this supply is for
Internal –5V converter use only and should not be used to power any other devices. The
for converter charge pump technique used to generate this negative supply uses an
use only. internal clock that places a charge on a capacitor to convert it from a positive
to a negative pulse train. The pulse train is then filtered to produce a -5 VDC
signal. This causes the +5 VDC current draw to double to 28mA typical,
44mA maximum.
Note: If the RDC-19222, RDC-19224, RDC-19222S, RD-19230, or RD-

19240 is designed in a system that requires very high dynamics (close to the
maximum tracking rate of the desired resolution) the converter should be
used in normal operation mode using both a +5VDC and –5VDC power
supply, instead of using internal charge pump mode circuit.
+5V
VDD
VDD
+ VDDP
47 μF .01μF
PCAP
+ RD-19230
10 μF/10V
NCAP or
VSSP RD-19240
VSS *
VSS
47 μF/10V
.01μF +
GND
AGND
Figure 5. Power Supply Set-Up for RD-19230 or RD-19240 (+5VDC P/S Operation)

THE BASICS
Charge Pump Frequency
To determine the charge pump rate, use an oscilloscope to measure the rate
of the PCAP.
+5 and –5 Volt Operation
Connect the 2 VDD pins to +5 VDC. Connect the 2 VSS pins to –5 VDC.
VDDP, VSSP, PCAP & NCAP are no connect.
+5 Volt Only Operation
Connect as shown in Figure 5. No external –5V supply is needed. Add filter

and charge pump caps as shown.
Typical -5 Volt Circuits
When it is necessary to create a -5V from other supplies, Figure 6 illustrates

several options.
-15 79LO5 -5
3 TERMINAL NEGATIVE REGULATOR
-15 -5
-5V 5.1V
10.2V ZENER
ZENER
-12 -5
6.8V -15V
ZENER
Figure 6. Typical -5 Volt Circuits

THE BASICS
Input Signal Conditioner Options

Table 2. Input Signal Configuration Options
Solid State
Parameter Transformer
Resistors/Thin Films
High Impedance Iso (Voltage
True Signal Iso (Isolation resolver to
Isolation Buffer – resolver to resolver +
resolver + ratio)
ratio)
Common Rejection Mode Best Good
Scott T Capability
Yes Yes
(Synchro to Resolver)
Cost Higher Lower
Size Larger Smaller
• 1 LSB for DDC thin film
packages
Additional Error
1 minute or greater depending on • For discrete resistor
transformer specification. networks use calculations
in Basics section under
resistor tolerance.

THE BASICS
Input Signal Configurations
Signal Connections
Synchro Mode Connect S1, S2, S3

S1 = X
S2 = Z
S3 = Y
Resolver Mode Connect

S3 = +SIN
S1 = -SIN
S2 = +COS
S4 = -COS

THE BASICS
Resistor Tolerance and Imbalance Matching

DDC has custom When using (0.1% tolerance) external resistors to scale down the input line-
thin-film resistor
networks available
to-line voltage, any imbalance of the resistance ratio between the sin and cos
that have very low inputs will create errors in the digital output. Formulas to calculate these
imbalance errors are shown below, and Table 3 lists the values of error for various
percentages. The
DDC-55688-1, DDC-
imbalances for a 16-bit application. Use this table as a guideline when
49530, DDC-57470, considering allowable resistor imbalances for system applications.
DDC-73089, DDC-
57471, and DDC-
49590 are resistor Output error (in degrees) due to resistor imbalance = 45°- tan-1 (1 + tolerance)
networks matched
to 0.02%, which
equates to 1 LSB of
Example:
error for a 16-bit To solve for error due to 1% imbalance (in degrees):
application. Output error (in degrees) due to 1% imbalance = 45°- tan-1 (1 + 1%)
Refer to DDC’s = 45°- tan-1 (1 + 0.01)
Thin-film Resistor
= 45°- tan-1 (1.01)
Network data sheet
available at = 45°- 45.285°
www,ddc-web.com. Output error (in degrees) due to 1% imbalance = - 0.285°
To convert error (in degrees) to error (in LSBs):

Output error (in LSBs) due to 1% imbalance = Output error (in degrees) / 0.0054932°
The bit weight of 1
LSB in 16-bit mode Output error (in LSBs) due to 1% imbalance = - 0.285° / 0.0054932°
is 0.0054932°. Output error (in LSBs) due to 1% imbalance = 52 LSBs
Table 3. Resistor Imbalance vs. Output Error

Imbalance Between Resistors Resultant Error
(%) (LSBs in 16-bit mode)
1 52
0.1 5
0.02 1
0.01 0.5
Table 4. Precision Thin-film Resistor Network Specifications

Specifications are rated over the operating temperature range of -55°C to +125°C
Part Number Input Voltage Output Voltage Package Type
(Vrms) (Vrms)
DDC-55688-1 2 single ended 2 Ceramic DIP
DDC-73089 2 differential 2 Plastic Surface Mount
DDC-49530 11.8 2 Plastic DIP
DDC-57470 11.8 2 Plastic Surface Mount
DDC-49590 90 2 Ceramic DIP
DDC-57471 90 2 Ceramic Surface Mount

THE BASICS
Matching Resistor Imbalance Within 0.02%

to Hold Output Error to 1 LSB
Using DDC-49530 thin film as the example:
1. “R2” Relative to “R1” means the ratio of R2 to R1 is critical and must be

maintained to .02%.
2. R1 tolerance specification is 0.1% of 70.8k and an actual value measured

must be used for the relative values.
3. “R2” value (12k) must be offset to be relative to R1.
Example:
1. R1 (70.8K) actually measured = 70.8354K = (Within 0.1% spec)
2. R2 is relative to R1
3. R2 required = 12K
4. R2 Offset calculation is as follows:
5. R2 = Relative resistor actual value x (Resistor value to be calculated /

Relative resistor value)
6. R2 = 70.8354K x (12K / 70.8K) = 12.006K
7. R2 installed must be 12.006k +/- 0.02%
Next relative value to calculate is R4 (Note that the data sheet listing is in alpha
order, not working order)
1. R4 (70.8K) is relative to R1
2. R1 (70.8K) actually measured = 70.8354K
3. R4 required = 70.8K
4. R4 Offset calculation is as follows:
5. R4 = Relative resistor actual value x (Resistor value to be calculated /

Relative resistor value)
6. R4 = 70.8354K x (70.8K / 70.8K) = 70.8354K
7. R4 installed must be 70.8354K +/- 0.02%

THE BASICS
Next relative value to calculate is R3, which is relative to R4.
1. R4 must be measured for calculation
2. R3 offset must be calculated
3. Installed R3 must be within 0.02% of calculated offset value.
Table 5. DDC-49530 RESISTOR VALUES (11.8 V INPUTS)

R1 70.8k 0.1 50
R2 R1 12k 0.02 3
R3 R4 12k 0.02 3
R4 R1 70.8k 0.02 3
R5 R1 70.8k 0.02 3
R6 R1 35.4k 0.02 3
R7 R6 6.9282k 0.02 3
R8 R6 5.0718k 0.02 3
R9 R11 5.0718k 0.02 3
R10 R11 6.9282k 0.02 3
R11 R1 70.8k 0.02 3
Figure 7. DDC-49530 Layout

THE BASICS
EXTERNAL
REF
LO HI
R1 R2 RB CBW
VELOCITY
R3 R4 CBW/10 Rv
5 4 7 8
S3 10k Ω -R +R -VSUM VEL

12 +S
6
14
-S -VCO
13 23 TO 38
SIN DIGITAL
10
S1 COS 16 OUTPUT
11
-C RDC-19220
22
10k Ω CB
9 +C 21 BIT
S2
S4 19 A GND
RESOLVER GND Rc
20 +5v -5v Rs
17 16
1 2 3 18 39
40 15 30kΩ 30kΩ
Notes:
INH EL
1) Resistors selected to limit Vref peak to between 1 V and 5 V. 1000pf 1000pf EM
2) External reference LO is grounded, then R3 and R4 are not .01μf .01μf
needed, and -R is connected to GND. A B
{
3) Refer to the RDC-19220 Data Sheet for the digital output.
4) See the thin-film resistor network DDC-55688-1 data sheet. +5v -5v RESOLUTION
5) Same for RDC-19224 but pin-outs are different. CONTROL
Figure 8. Direct Input To RDC-19220 (40-pin DDIP)
Direct 2v Resolver And X-Volt Resolver

Figure 8 shows a 2 Vrms direct SIN/COS input (also known as a single-
All ac ended input). The SIN output pin is tied directly to the -S input pin and the
voltages are COS output pin is tied directly to the -C input pin. A 10 kΩ, 1% current limiting
rms values. resistor is recommended on the +S and +C input to the RDC-19220 series
(see Figure 8 and Figure 9). All ac voltages are rms values.
Direct input is not recommended for high noise environments or where the
resolver transducer is a long distance from the converter. In these cases the
Common Mode Rejection (CMR) of a differential input will reduce the effects
of noise.

THE BASICS
EXTERNAL
REF
LO HI
R1 R2 RB CBW
VELOCITY
R3 R4 CBW/10 Rv
30kΩ 30kΩ
6 7 18 19 9 10
10kΩ -R +R RSR C VEL
S3 14
+S 8
16 -VCO
-S
15
SIN 29 to 44
12
S1 COS DIGITAL
13
RDC-19222 OUTPUT
-C 16
10k Ω 11
+C 26
CB
S2 27 BIT
S4 A GND
21
RESOLVER GND -CAP +CAP (-5c)-5v(+5c) +5v

POWER
23 25 22 17 26 2
24 3 4 5 1 20 SUPPLY
+5v
Notes: 47u f
1) Resistors selected to limit Vref peak to between 1 V and 5 V.
10uf 0.01uf 0.01uf
+
2) External reference LO is grounded, then R3 and R4 are not
+ INH EM
needed, and -R is connected to GND.
3) Refer to the RDC-19220 series data sheet for the pin 47uf A B EL
numbers of the digital output.
{
4) See the thin-film resistor network DDC-55688-1 data sheet.
RESOLUTION
CONTROL
Figure 9. Direct Input To RDC-19222 (44-pin J-Lead)
EXTERNAL
REF
LO HI
R1 R2
R3 R4
See Note 3. RL RH
+S
S3 -S
SIN
Note: The external BW components
S1 COS as shown in Figure 3
-C are necessary for the R/D to
function.
See Note 3.
+C
S2
S4 A GND RD-19230/RD-19240
RESOLVER GND
Notes:
1) Resistors selected to limit Vref peak to between 1.5 V and 5 V.
2) External reference LO is grounded, then R3 and R4 are not
needed, and -R is connected to GND.
3) 10k ohms, 1% series current limit resistors are recommended for SIN, COS, and Ref inputs when no voltage adjustments are
needed.
Figure 10. Typical Connections, 2V Resolver, Direct Input, RD-19230/RD-19240

THE BASICS
When the resolver output is higher than 2 Vrms the signals need to be scaled
down using the following equations, and as shown in Figure 11 below.
To avoid loading the resolver,

R2 should be 10 kΩ minimum.
R2 2
=
R1 + R2 VRESOLVER(rms)
R1 + R2 ratio errors will result in 2 cycle angular errors. For example, a 0.1%
ratio error equates to 0.029 peak error.
Figure 11. X-Volt resolver, Example using Direct Input to RDC-19220 (40-pin DDIP)

THE BASICS
Differential Resolver
A differential input signal will provide better stability than a single-ended
input. The circuit in Figure 10 applies to resolvers that have a signal output of
2 Vrms or higher. For devices with a signal output lower than 2 Vrms, a pre-
amplifier circuit should be used to provide gain, rather than using resistors to
increase the internal gain (please refer to information regarding Inductosyns).
Resistors should not be used to increase the gain for an output signal lower
than 2 Vrms for two reasons: 1. Noise on the signal lines will be gained up
Preferred Mode and become part of the signal, causing accuracy errors, and 2. Setting the
of Operation gain larger than 1/3 will introduce errors due to internal offsets.
The resistors used to scale down the resolver signals need to be precision
resistors matched to each other. DDC offers thin-film resistor networks that
are matched to within 0.02%.
The DDC-49530 and DDC-57470 are set-up to scale 11.8 Vrms down to 2
Vrms. The DDC-49590 and DDC-57471 are set-up to scale 90 Vrms down to
2 Vrms single ended. The DDC-55688-1 and DDC-73089 are 2 Vrms to 2
Vrms. Refer to the Thin-film Resistor Network data sheet for specifications
(available at www.ddc-web.com).

THE BASICS
Please Note:
The External -REF
Components in SIGNAL AC
this example are +REF

necessary for
the converter to R1 R2
operate.
R3 R4
SIN -REF +REF EXTERNAL

3 SIN COMPONENTS
Ri Rf -S -VSUM
S1 1
2 -S
+R Ri RDC 19220 CBW
S3 6 +S
-R S1 +S SERIES
5
S3 CBW/10
S4 Rf
RB
RESOLVER S2 A GND 4 COS
VEL
13 VELOCITY
Ri COS
16 Rf -C
S4 15
RV
Ri +C -C
S2 7
8 10
+C -VCO
Rf
12
R1-4 SELECTED TO LIMIT V REF TO BETWEEN 2V AND 4V PEAK
Figure 12. Differential Resolver Input

using DDC-49530 (11.8 V), 57470 (11.8 V), 49590 (90 V), or 73089 (2V)
For custom resolver voltages:
Examples of Component Calculations
1. 2V in, need gain of 1, use 10k for Rf & Ri

Gain = RF
Ri
2. 4V in, need gain of 0.5, Ri = 20k, Rf = 10k

To Calculate Ri:
Select 10k for Rf
Ri = Rf x 0.5 x (input L-L volt)
Ri = 10k x 0.5 x (input L-L volt)

THE BASICS
Note: Input options affect DC offset gains and therefore affect carrier
frequency ripple and jitter. Offset gains associated with differential mode
(offset gain for differential configuration = 1+Rf/Ri) and direct mode (offset
gain for direct configuration = 1) show differential mode will always be higher.
Higher DC offsets cause higher carrier frequency ripple due to the
demodulation process. This carrier frequency ripple rides on top of the DC
error signal, causing jitter. A higher carrier frequency versus bandwidth ratio
will help to decrease ripple and jitter associated with offsets.
In summary, R/Ds with differential inputs are more susceptible to offset

problems than R/Ds in single-ended mode. R/Ds in higher resolutions, such
as 16 bit, will further compound offset issues due to higher internal voltage
gains. Although the differential configuration has a higher DC offset gain, the
differential configuration's common mode noise rejection makes it the
preferred input option. The tradeoffs should be considered on a design to
design basis. (Also refer to FAQ-G1Q-021)
Synchro Input
A synchro produces a three-phase (S1, S2, and S3) Y configuration ac output
from the reference excitation. The three-wire configuration of a synchro, like a
differential resolver input, cannot interface directly to the RD/RDC series.
Figure 13 uses a resistor network to scale a synchro input on a RD-19220
example.
-REF
SIGNAL AC
+REF
R1 R2
R3 R4
-REF +REF
3
SIN -VSUM
Rf
1 Ri 2
RDC 19220 Cbw
-S
6 Ri SERIES
5 +S Cbw/10
+R Rb
-R S1
S3 Rf
4
VEL VELOCITY
A GND
SYNCHRO S2
14 COS
Ri Rv
16
Rf
7 Ri 8 3 15
15
-C
Ri/2 -VCO
9 10 +C
Rf
3
11
Figure 13. Synchro Input, using DDC-49530 , 57470, 49590, or 73089

THE BASICS
Linear Variable Differential Transformer (LVDT)

The output signals of a LVDT are two linear functions (see Figure 14, detail
A) whereas the resolver is a non-linear sinusoidal form (see detail C). The
RD/RDC series has the appropriate input pins available to scale a 3-wire
LVDT to optimize performance as an LVDT-to-digital converter.
The theory of using a LVDT can also be applied to the implementation of a

RVDT input.
The converters resolution control lines should be a combination of logic 0,

logic 1 or -5V as shown in Table 7.
In comparing Figure 14, detail A & B, you can see that the LVDT is scaled so
that the lower output voltage limit is scaled to equal zero and the upper
output voltage limit is scaled to equal 2 V.
Figure 14. LVDT Output vs. Typical RDC-19220 Series Input

THE BASICS
The upper and lower output voltage levels could apply to a limited linear
range on the LVDT. With the output of the LVDT rescaled, the RD/RDC
series will interpret the LVDT with bits 1 and 2 for over range conditions,
similar to the first quadrant (0° to 90°) in the resolver mode (see Figure 14,
detail C).
Figure 15 shows the scaling circuit for a 3-wire LVDT.
Please note:
the external
components are
necessary for
the converter
to operate.
Figure 15. 3-Wire LVDT Scaling Circuit
The following calculations apply to the circuit in Figure 15.
1 1 a
b= = SIN = − 1V + (VA − VB)
VANULL VBNULL 2
2 a
a= COS = − 1V − (VA − VB)
(VA − VB)MAX 2
Notes:
1. R’ > 10k Ohms
2. Considerations for the value of R is LVDT loading.
3. RMS values are given.

THE BASICS
4. Use the absolute value of Va and Vb to calculate resistance values. Use

the calculated sign of Va and Vb to calculate Sin and Cos. Calculations
shown are based on full scale travel being on the Va side of the LVDT.
Rescaling Example For 3-Wire LVDT

Figure 16 shows the LVDT with the slider position at –Full-scale, Null, and
+Full-scale.
Figure 16. LVDT
Table 6. Example of LVDT Output

- Full - 1/2 Full Null + 1/2 Full + Full
Scale Scale Scale Scale
VB-GND 3.6 4.3 4.9 5.5 6.1
VA-GND 6.1 5.5 4.9 4.3 3.6
The following is an example of a typical 3-wire LVDT calculation for rescaling

the input for the RDC-19220 series.
1 1 1
b= = b= = 0.204
VA NULL VBNULL 4 .9
2 2
a= a= = 0. 8
(VA − VB )MAX (6.1 − 3.6)
R = 100 kΩ, aR = 80 kΩ, bR = 20 kΩ, R’ = 10 kΩ

THE BASICS
-Full-Scale Travel Example (-FS)

Following is a calculation example showing the relationship to scaling that
generates a digital code of 000 000 000 000 = 0° = -FS:
At –FS
a
sin = −1V + (VA − VB )
2
0.8
sin = −1V + (6.1 − 3.6)
2
sin = −1V + 1
sin = 0V
Note: sin=0V at 0°, refer to Figure 14, Detail C
a
cos = −1V − (VA − VB )
2
0.8
cos = −1V − (6.1 − 3.6)
2
cos = −1V − 1
cos = −2V (see note below)
Note: Per Figure 15, the +REF signal is set to –2V, so this calculated cos
voltage in the above example looks like a positive 2V.
Note: cos=max V at 0°, refer to Figure 14, Detail C
+S -S SIN
AGND
-REF
+REF
+C -C COS
Figure 17. 3-Wire LVDT Direct Input

THE BASICS
Scaling Circuit for a 2-Wire LVDT.
C1
SIN
C1 and C2 aR
should be chosen
2 WIRE LVDT -S
to minimize R
-
phase-shift R
REF IN +S
between +S R
and +C inputs. + FS = 2 V
C2 aR
COS
bR R
R
2R
R -C
-
2R
+C
R
+ 2V R
bR
+REF
-REF
Figure 18. 2-Wire LVDT Scaling Circuit
Note: op-amps with low DC offset (<1 mV) should be chosen.
The following calculations apply to the circuit in Figure 16:
aR = 2V
VOUTMAX
R
VINMAX bR = 2V
R

THE BASICS
Rescaling Example For 2-Wire LVDT

The following is an example of a typical 2-wire LVDT calculation for rescaling
the input to the RD/RDC series.
Reference (VIN) = 3.5 V
Output LVDT Range (VOUT) = ±500 mV
R = 10 kΩ
aR
(0.5) = 2 therefore, aR = 40kΩ
10kΩ
bR
(3.5) = 2 therefore, bR = 5.7kΩ
10kΩ
For LVDT mode, the resolution control lines are as follows:

RDC 19220/2 and RDC-19220/2S Series have A & B control lines.
RD 19230/RD-19240 Series have D1 & D0 control lines.
Table 7. LVDT Resolution Control

LVDT Resolution Control
Resolution (bits)
B or D1 A or D0
8 -5V 0
10 0 -5V
12 1 -5V
14 -5V -5V
Note: Tying a resolution control line to -5 V puts the converter into a linear
mode. When using the RDC-19222, RDC-19222S, RD-19230, or RD-19240
internal charge pump, the internally-generated -5 V may be used for the
resolution control lines.
In LVDT mode:
bit 16 is the LSB for 14-bit resolution
Refer to Table 8 for the digital output codes for the RD/RDC Series Converter
in LVDT mode.

THE BASICS
Table 8. Digital Output Of The RD/RDC Series In LVDT Mode

Digital Output Bit
LVDT Output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+ Over Full Scale 0 1 X X X X X X X X X X X X X X
+ Full Travel - 1 LSB 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+ 0.5 Travel 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
+ 1 LSB 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
Null 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
- 1 LSB 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
- 0.5 Travel 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
- Full Travel 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- Over Full Travel 1 1 X X X X X X X X X X X X X X
Full LSBs LSBs LSBs LSBs
MSB
Scale 8 Bit 10 Bit 12 Bit 14 Bit
Note 1: If using the RD/RDC series to replace the DTC-19300, bit 3 should be inverted.
Note 2: The RD-19240 has 2 less bits of resolution available.
Note 3: Accuracy specifications below for (2-wire) LVDT mode, null to + full scale travel (45° degrees)
4 Min part = 0.15% + 1 LSB of full scale “resolution set”.
Accuracy specifications below for (3-wire) LVDT mode, null to + full scale travel (90° degrees)
Note that these accuracy specifications are for the converter and do not consider front end and
external resistance tolerances.
Note 4: Data output is Binary Coded in LVDT mode. The most negative stroke of the LVDT is represented
by ALL ZERO’s and the most positive stroke of the LVDT is represented by all ONES. The most
significant 2 bits (2 MSBs) may be used as over range indicators. Positive over-range is indicated by code
“01” and negative over-range is indicated by code “11”.

THE BASICS
Inductosyn®
A linear or rotary Inductosyn® consists of a slider and a scale. As the slider
moves over the scale there is a low voltage electrical output proportional to
the distance moved. Inductosyns usually are excited by a 5 kHz to 20 kHz
frequency. The OSC-15801 is an oscillator that was designed with a high
frequency output and a 90° phase shift, which is needed for Inductosyn®-to-
digital conversion (see Figure 19).
INDUCTOSYN
INDUCTOSYN SLIDER
SCALE
DUAL
MATCHED
INDUCTOSYN RESOLVER
QUADRATURE 2 Vrms
TO
PREAMPS
POWER DIGITAL
OSCILLATOR CONVERTER DIGITAL
OSC-15801 OUTPUT
PA OUT
RH RL
REF OUT CHASSIS GROUND

-90
CIRCUIT GROUND
90˚ PHASE
SHIFTED
QUADRATURE
OUTPUT
Figure 19. Inductosyn®-To-Digital Converter System
Note: Figure 19 will convert each pitch to 360° of digital data. A means to track
See DDC’s counts will be needed for multiple pitches. Using an RD-19230 and A quad B
Synchro/Resolver zero index pulse for counting pitches is one possible solution.
Conversion
Handbook “Using
an R/D with an Note that inductosyns typically have a (+ or -) 90-degree phase shift from
inductosyn” for input to output. This requires an oscillator with a 90-degree phase-shifted
further information.
second output to be connected to the RD converter reference so that the RD
input and reference will be in phase. DDC has two oscillators to cover +90 or
–90 degree phase shifts needed. See the OSC-15801 for -90PS and the
OSC-15802 for +90PS.

THE BASICS
Figure 20 shows a dual matched preamplifier diagram that is recommended

for use to amplify an Inductosyn® output for the signal input to the RD/RDC
series (2 Vrms, ±10%). The R3 and R4 resistors should be trimmed to match
the gain of the +SIN and +COS channels. This is done by measuring the
differential voltage at the input of the op amp closest to the slider (+SIN and
+COS). The output voltage is measured to determine the gain. Resistors R3
and R4 are selected to match the output gain of +SIN and +COS as close as
possible. A high accuracy digital voltmeter is recommended for the final
output readings. Capacitors C1 and C2 are used to block any DC voltage.
C1 RA1
RA2 RA2
RA1 +15V
_ _
R3 RA1
TBD
U1 U1
RA1
+ +
GND
RA2
CHASSIS GROUND
CIRCUIT GROUND
RA2 C2 RA1 RA2
+
RA1
_ _
R4 RA1
U1 TBD U1
RA1
+ +
RA2
NOTES: Parts List

1. For lower input levels use Harris HA-5114 U1 Harris HA-5104
RA1 Beckman 698 3 R3300
RA2 Beckman 698 3 R5KD or 699 3 R5KD
C1,2 22µF 2VDC
R3,4 TBD (NOT USUALLY NEEDED)
Figure 20. Dual Matched Differential Amplifier

THE BASICS
DC Inputs
As noted in the specifications tables of the appropriate data sheets, the RDC-
19220/2/4, RD-19230, and RD-19240 will accept DC inputs.
1. DC input operation is from 0° to 180° or 180° to 359° only, due to the

possibility of an unstable false null, i.e., 180° hangup. The false null condition
will only happen on power up and an instantaneous 180° step, therefore once
the converter moves it will go to the correct answer. In real world applications
where an instantaneous 180° change is impossible, the converter will always
be correct within 360°. The problem arises at power up in real systems. If the
converter powers up at exactly 180° from the applied input, the converter will
not move. This is very unlikely, although it is theoretically possible. This
condition is most often encountered during wraparound verification tests,
simulations, or troubleshooting.
2. It is recommended that the synthesized reference option be disabled for

DC input operation on the RD-19230 and RD-19240. Disable the synthesized
reference by connecting DSR to ground through a 10 ohm resistor.
3. The reference input must be set to DC by tying RH to +5V and RL to

ground or -5V.
4. Set the COS and SIN inputs such that the maximum signal is equal to 1.8
VDC. For example, at 90° the SIN and 0° for COS the input should equal to
1.8 VDC. This will keep the BW hysteresis consistent with AC operation.
5. Input offsets will affect accuracy. Verify the COS and SIN inputs do not
have DC offsets. If offsets are present, a differential op amp configuration can
be used to minimize differential offset problems.
6. BIT output is undetermined during DC operation and should not be used.
7. Choose the bandwidth value of the converter based on the rate of change
of the systems input amplitude variation. It should be large enough to
minimize it’s effect on the system dynamics. Note that if the bandwidth is too
high the system will be more susceptible to noise.
8. The accuracy of a converter using a DC input will be degraded from the

rated accuracy. Consider the best case where the input is single ended and
no additional DC offsets are present on the input of the converter - the
accuracy will degrade by approximately 2 arc minutes. For example, if a part
is rated at 2 arc minutes, a DC input will degrade the accuracy to
approximately 4 arc minutes.

THE BASICS
Reference Input Configurations
Reference Input
The reference that is used to excite the Synchro/Resolver is used as an input
to the RD/RDC series. The conversion technique utilizes the reference for
phase information in the demodulator section of the converter. This ensures
quadrature rejection of the Synchro/Resolver signals. For example, the
resistors R1 and R2 should be selected as follows:
For the RDC-19220/2S, RD-19230 and RD-19240, R1 through R4 selected to

limit V ref to between 1.5V and 5V peak. For RDC-19220/2/4, R2 thru R4
selected to limit V ref to between 1.0V and 5V peak.
X R1+ R2
=
2Vrms R2
where X is the reference excitation in Vrms, R3 = R1 and R4 = R2
If the external reference low is tied to ground (single-ended), then R3 and R4

are not needed and -R is connected to GND.
Note: For circuits where no voltage adjustment is needed add a 10k ohm
series resistor for turn on current surge protection.
-REF
SIGNAL AC
+REF
R1 R2
R3 R4
-REF +REF
3
SIN -VSUM
Rf
1 Ri 2
RDC 19220 Cbw
-S
6 Ri SERIES
5 +S Cbw/10
+R Rb
-R S1
S3 Rf
4
VEL VELOCITY
A GND
SYNCHRO S2
14 COS
Ri Rv
16
Rf
7 Ri 8 3 15
15
-C
Ri/2 -VCO
9 10 +C
Rf
3
11
Figure 21. Differential Resolver Input and Reference Scaling Resistors

(Example using RDC-19220)

THE BASICS
Synthesized Reference
The synthesized reference section of the RDC-19220/2S, RD-19230, and
RD-19240 eliminates errors caused by quadrature voltage which is due to a
phase shift between the reference and the signal lines. Quadrature voltages
in a resolver or synchro are by definition the resulting 90° fundamental signal
in the nulled out error voltage(e) in the converter. Due to the inductive nature
of synchros and resolvers, their signals typically lead the reference signal
(RH and RL) by about 6°.
When a uncompensated reference signal is used to demodulate the control

transformer’s output, quadrature voltages are not completely eliminated. The
converter synthesizes its own COS ( ωt + α ) reference signal from the
SIN θ − COS ( ωt + α ) , COS θ − COS ( ωt + θ ) signal inputs and from the
COS ωt reference input. The phase angle of the synthesized reference is
determined by the signal input. The reference input is used to choose
between the +180° and –180° phases. The synthesized reference will always
be exactly in phase with the signal input, and quadrature errors will therefore
be reduced. The synthesized reference circuit also eliminates the 180° false
error null hang up.
Due to the inductive nature of resolvers, the output signals typically lead the
reference by 6°, and a 6° phase shift will cause problems for a 1 arc minute
accuracy converters. A synthesized reference will always be exactly in phase
with the signal input, therefore eliminating accuracy error caused by phase
shift up to 45°.

THE BASICS
Quadrature Voltage and Phase-Shift

Quadrature voltages in a resolver or a synchro are by definition the resulting
Quadrature is the 90° fundamental frequency present in the synchro/resolver signal. The
90° out-of-phase inductive nature of synchros and resolvers and the capacitive nature of signal
portion of the paths will induce quadrature into the signal. This portion is present in the
signal. error voltage (e) in the converter (see Figure 2, Figure 3, and Figure 4).
The “e” voltage is demodulated, which eliminates the effect of the quadrature
in the signals. However, a digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift between the
converter signals (SIN, COS) and the reference inputs. The magnitude of this
error is given in the following formula:
The magnitude of error is in radians
null voltage + speed voltage

Magnitude of Error = • Tanα
(static) F.S. signal
The Magnitude of Error (Dynamic) Quadrature voltage is in volts (as specified

by the synchro or resolver manufacturer; it may also be referred to as null
voltage).
F. S. signal = full scale signal in volts
α = signal-to-reference phase shift
An example of the magnitude of error is as follows:
Let:
Quadrature voltage = 11.8 mV
F. S. Signal = 11.8 V
α = 6°
Speed Voltage = 0V
Then: magnitude of error = 0.36 min ≈ 1 LSB in the 16th bit.

THE BASICS
Additional Sources of Error

Note: Quadrature is composed of static quadrature (null voltage) which is
specified by the synchro or resolver supplier plus the speed voltage which is
determined by the following formula:
⎛ ( Rotational Speed ) ⎞
(SpeedVoltage) = ⎜⎜ ⎟⎟ • (F .S .Signal )
⎝ (Carrier Frequency) ⎠
where:
Speed voltage is the quadrature due to rotation
Rotational speed is the RPS (revolutions per second) of the synchro or

resolver
Carrier frequency is the reference in Hz.
Fundamental
Quadrature
Third Harmonic
OUTPUT
TIME
Second
Harmonic
Figure 22. Quadrature and Harmonics

THE BASICS
Phase-Shift Correction (RDC-19220/2/4)

(For converters without synthesized ref)
Correcting for the phase shift between the reference and input will improve
accuracy and quadrature rejection. A circuit should be used to lead or lag the
reference into the converter to compensate for phase shift between the signal
and the reference, and to reduce the effects of the quadrature is illustrated in
Figure 23. To minimize accuracy error correct phase shift to less than 6
degrees.
LAG
R
For a ref signal
that leads the
inputs {+ REF
- REF
C
+ REF
- REF
LEAD
C
For a ref signal
that lags the
inputs {
+ REF
- REF
R
+ REF
- REF
tan¢ = Xc Where ¢ = desired phase-shift

R
Xc = 1 Where f = carrier frequency

2pƒc Where c = capacitance
Figure 23. Phase Shift Compensation

THE BASICS
Transformer Isolation
System requirements often include electrical isolation from the
synchro/resolver and reference signals. DDC has transformers available for
use with the RD/RDC Series Converters. These transformers reduce the
voltage to the required 2 Vrms for a direct connection. The reference
transformers provide isolation of the reference signal.
Table 9. Transformers
ANGLE
FREQ IN OUT LENGTH WIDTH HEIGHT Available
P/N TYPE ACCURACY
(HZ)* (VRMS)* (VRMS)** (IN) (IN) (IN) FROM
***
52034 S-R 400 11.8 2 1 0.81 0.61 0.3 Beta
52035 S-R 400 90 2 1 0.81 0.61 0.3 Beta
52036 R-R 400 11.8 2 1 0.81 0.61 0.3 Beta
52037 R-R 400 26 2 1 0.81 0.61 0.3 Beta
52038 R-R 400 90 2 1 0.81 0.61 0.3 Beta
B-426 Reference 400 115 3.4 N/A 0.81 0.61 0.32 Beta
52039-X Synchro 60 90 2 1 1.1 1.14 .42 DDC
24133-X Reference 60 115 3/6**** N/A 1.125 1.125 .42 DDC
* ±10% Frequency (Hz) and Line-to-Line input voltage (Vrms) tolerances

** 2 Vrms Output Magnitudes are -2 Vrms ±0.5% full scale
*** Angle Accuracy (Max Minutes)
**** 3 Vrms to ground or 6 Vrms differential (±3% full scale)
Dimensions are for each individual main and teaser
60 Hz Synchro transformers are active (requires ±15 Vdc power supplies)
400 Hz transformer temperature range: -55°C to +125°C
60 Hz transformer (52039-X, 24133-X) temperature ranges: add to part number -1 or -3,
-1 = -55°C to +85°C
-3 = 0 to +70°C
The following transformers can be ordered directly from DDC, Tel (631) 567-5600:
P/N 52039-X, 24133-X
The following transformers can be ordered directly from Beta Transformer Technology Corporation
(BTTC), Tel (631) 244-7393:
P/N 52034, 52035, 52036, 52037, 52038, and B-426.
Refer to Figure 24 for transformer connection diagrams. Refer to the

Transformer section on Page 122 for the mechanical drawings.

THE BASICS
1 6
RH +R
EXTERNAL B-426
5 10
REFERENCE RL -R
LO HI
OR
RB CBW
RH +R 60 hz
24133
RL -R CBW/10 RV
+15 V -VS
+15V -15V
-S SIN -R +R -VSUM VEL
S1 -VCO
RH +S
RL 1 10
S3 TIA DIGITAL
3 6 OUTPUT
+C RDC-19220
S4 16
11 20 -C
TIB COS CB
S2
15 16 BIT
AGND
52036(11.8V) INH
OR EM
52037(26V) GND Rs Rc
OR EL
52038(90V)
A B +5V -5V 30K Ω 30K Ω
OR
}
SYNCHRO INPUT
RESOLUTION
CONTROL
S1 +S
RL RH 1 10
S3
3 TIA
5 6
+C
11 20
S2 TIB
15 AGND
16
GND
52034(11.8V)
OR
52035(90V)
Figure 24. Transformer Connection Diagrams

THE BASICS
Mandatory External Components

The RD/RDC series converters use a type II tracking loop in it’s feedback. It
Please note:
is necessary to include five external components (three resistors and two
the external
components are
capacitors). These components set the bandwidth (BW) of the converter and
necessary for the the scaling of the velocity output. DDC has Component Selection Software
converter to available to calculate the values of these components based on the desired
operate. carrier frequency, resolution, bandwidth, and maximum tracking rate. The
software performs the calculations as discussed below. It is available from
the DDC Web site (www.ddc-web.com), through local sales offices or by
contacting the factory. The RD-19230/RD-19240 converters have a second
set of BW components for switch on the fly or dual BW applications.
Calculating External Component Values

When choosing external component parameters, the following six
considerations should be taken into account:
1 - The system requirements need to be considered to set the bandwidth

(BW) and tracking rate (TR). For the greatest noise immunity, select the
minimum BW and TR the system will allow.
2 - The maximum tracking rate per resolution and the maximum carrier
frequency per resolution are as follows:

THE BASICS
Table 10. Maximum Tracking Rate And Carrier Frequency Versus Resolution
Resolution Resolution
RC RS
PART NUMBER Or Or 10 12 14 16 10 12 14 16
RSET RCLK MAX TRACKING RATE *** CARRIER
*** IN RPS FREQUENCY
MAX IN KHZ
RDC-19220/2S,
30 kΩ*
RD-19230,
or 30 kΩ 1152 288 72 18** 10 10 5 5**
RD-19240
Open
SERIES
RD-19220/2 30 kΩ*
SERIES or 30 kΩ 1152 288 72 18 20 11 7 5
Open
* the use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
** 16-Bit mode not available on RD-19240.
*** Extended tracking rates and carrier frequencies per resolution are
available. Use the component calculation software for extended dynamic
needs.

THE BASICS
3- To minimize temperature effects, use tighter accuracy and temperature

drift resistors and capacitors.
DDC's External Component Value Selection software can be used to

estimate component tolerance effects on parameters. After entering desired
parameters and obtaining the calculated component results, the component
values can be modified, and the user can then view the effect on the original
parameters.
4- The TR to BW ratio must be less than or equal to the ratios listed in Table
11. If the TR & BW ratio is greater than the listed ratio, a spin-around
condition may occur. Spin-around is a condition when the converters digital
output continually counts, and never settles on an angle.
When using the
charge pump
Table 11. Tracking / BW Relationship
feature the
maximum negative RPS(Max)/BW Resolution
voltage on velocity 1 10
is –3.5V.
0.45 (*0.50) 12
0.25 14
0.125 16
* = RD-19230/RD-19240 ONLY
5- When using the built-in -5 V inverter or the charge pump (RDC-19222/S,

RD-19230, and RD-19240 only), the maximum tracking rate should be scaled
for a velocity output of 3.5 V max. Use the following equation to determine
the tracking rate to be used in the equation to calculate Rv by hand for
reference only. Always use the Component Selection Software for final
component selection values.
Tracking rate used in calculation = [TR (required) x (4.0)]/3.5
6-The calculations for the components are as follows:
Converter Maximum Tracking Rate *

RV = 55kΩ • (1)
Application Maximum Tracking Rate
* Preferred values to use as “converter maximum tracking rate” in the above

equation are as follows (tracking rate is listed in revolutions per second
[RPS]):

THE BASICS
3.2 • FS ( Hz ) * * • 10 8
CBW ( pF ) = (2)
RV • ( FBW ) 2
where FBW = bandwidth frequency
** The value of Fs (internal converter sampling frequency) is dependent

on the value of Rs. The value of Fs = 67 kHz when Rs = 30 kΩ.
0.9
R B (kΩ ) = (3)
CBW • FBW
where RB = bandwidth component
Example Using The Calculations:
Carrier Frequency = 2 kHz

Resolution = 16 Bits
Bandwidth = 100 Hz
Maximum Tracking = 10 rps
from equation 1: R V (Ω) = 55k 18rps = 100 kΩ

10 rps
from equation 2: C BW (µF)= 3.2 67000 Hz 108 =0.022µF
100k (100 Hz) 2
from equation 3: R B(Ω) = 0.9 = 410 kΩ
22µF 100 Hz

THE BASICS
Component Value Selection Programs

DDC has a component value selection spreadsheet available to aid our
customers in their design work. The user enters system specifications data
into the spreadsheet, and component values are generated. The Excel
spreadsheet is for use with Windows 3X/2000/XP and Windows NT, and can
be downloaded from the DDC Web site at www.ddc-web.com.
External Component Selection Guidelines

The external component calculation software requires inputting four dynamic
parameters. These parameters are Carrier Frequency, Resolution,
Bandwidth, and Maximum Tracking Rate. The example below will guide you
through a rough check of your dynamic parameter selections before using the
software calculation program. Using your specific component data sheet,
take your four dynamic parameters and follow the guidelines below before
inputting the values into the component selection software.
The following will be used as our example four dynamic parameters:
Carrier Frequency = 5Khz,
Bandwidth (BW) = 130 Hz,
Resolution = 16-bits,
Maximum Tracking Rate = 15 rps
1st check: Ensure that the resolution will be acceptable for the carrier
frequency. Use the maximum carrier frequency lookup table. The example
below shows that the chosen resolution of 16-Bits will be acceptable for a
5 kHz carrier frequency.
Table 12. Carrier Frequency (Max) in KHz (Example Only)

RC/RSET RS/RCLK
RESOLUTION
(Ω) (Ω)
10 12 14 16
30k**or
30k 10 10 7 5
open
23k 30k 10 10 10 7
23k 20k 10 10 10 10
23k 15k 10 10 * *
*Not Recommended
** The use of high quality thin-film resistor will provide better temperature stability
than leaving open.

THE BASICS
2nd check: Ensure that the resolution will not exceed the rps maximum
tracking rate. Use the maximum tracking rate lookup table. The example
below shows that the chosen resolution of 16-Bits will be acceptable for
15rps.

THE BASICS
Table 13. Maximum Tracking Rate (Min) in RPS (Example Only)

RC/RSET RS/RCLK
RESOLUTION
(Ω) (Ω)
10 12 14 16
30k**or
30k 1152 288 72 18
open
23k 20k 1200 432 108 27
23k 15k * 576 * *
*Not Recommended
** The use of high quality thin-film resistor will provide better temperature stability
than leaving open.
3rd check: Now for a 5 kHz frequency being used at 16-bit resolution, we
need to select the bandwidth. Per the specific component data sheets
dynamic characteristics table, locate the maximum BW selectable for 16-bit
mode. For this example, 300 Hz is the maximum. Per BW component general
guidelines, the BW to Frequency rule is no greater than ¼. In this case the
dynamic characteristics table will take precedence since 300 is much less
than ¼ of 5 kHz. So, for this example we will pick an arbitrary BW of 130 Hz
for noise rejection.
Dynamic Characteristics
Resolution Bits 10 12 14 16
Tracking Rate (min) rps 1152 288 72 18
Bandwidth (Closed Loop) Hz 1200 1200 600 300
(at maximum bandwidth)
4th check: Tracking to Bandwidth ratio verification. Use the Tracking to

Bandwidth relationship table (see Table 14 for an example) and verify that for
the resolution picked, the tracking rate to BW ratio is not exceeded. For 16-bit
resolution at 15 rps and a 130 Hz BW, then 15/130 = 0.115 which does not
exceed the maximum ratio of 0.125 listed for 16-bit resolution mode.
Table 14. Tracking / BW Relationship Example

RPS (MAX) / BW RESOLUTION
1 10
0.50 12
0.25 14
0.125 16
After verifying that the four dynamic parameters will operate in your system,
use these parameters in the component selection software to calculate
resistor and capacitor values.

THE BASICS
Note: If resistor values are calculated as high Meg ohm resistors, recheck
entered dynamic parameters. If a parameter is entered much lower than the
maximum allowed value, then relaxing the parameter will impact resistor
values. As an example, if the maximum rps allowed entry is 15 and 5 was
entered, raise the rps entry value to 15 and recalculate components.
Design Guidelines for Bandwidth Components

Bandwidth should be less than or equal to ¼ of the carrier frequency
reaching maximum limits of 1200Hz at 10 and 12 bits resolution, 600 Hz at
14 bits resolution and 300 Hz at 16 bits resolution (note 1). Verify all
maximum limits per the converter data sheet being used. Normally,
bandwidth (BW) should be set for ¼ of the transducer “Resolver, Synchro”
carrier frequency. This is for best noise immunity and converter dynamics to
react to angle changes quickly. Selecting a lower BW will give you a better
noise immunity but slows down the parts response. Selecting a higher BW
will give you faster response to changes but can allow more noise through
which can effect the data angle accuracy, as the converter may interpret
noise as angle movement.
At 10-bits of resolution, the tracking rate can never exceed the bandwidth, but
may be equal to the bandwidth, as there is a 1:1 ratio. Maximum tracking
rates are maximum converter tracking rates and not necessarily maximum
Resolver/Synchro tracking rates. Maximum tracking rates of the converter are
absolute maximum tracking rates achievable and not intended for standard
operation. If changing resolution, divide the 10 bit resolution maximum
tracking rate by 4 for every resolution increase desired (Example: For 12 bit
resolution the maximum tracking rate is 288 RPS. For 14 bit resolution the
maximum tracking rate is 1152/4/4 = 72 RPS, For 16 bit resolution the
maximum tracking rate is 1152/4/4/4 = 18 RPS).
Notes:
1. Choosing Bandwidths outside of the maximum specifications may work,

but component values for resistance may be very high (Meg’s) or
capacitance may be very low (pico’s). These values may now be affected by
part or circuit variation of internal resistance or capacitance of which the
characteristics of desired BW and Tracking rates may vary through
production from the verified design. If exceeding these maximum rates then
testing and verification of each converter’s response dynamics is required.
Lot to lot variances may cause performance differences between converters
or converters and PCB. It is not recommended that you exceed the maximum
specification values per data sheet unless each part is tested and verified to
be within desired BW and tracking rate characteristics.
2. For a Tracking Rate guideline, choose a reference frequency at least 10X

the maximum system velocity. For example, if the system maximum velocity

THE BASICS
= 30rps, then the reference frequency should be 300-400 Hz.
3. Exceeding the maximum carrier frequency per the converters dynamic

characteristics will cause the accuracy to degrade. This is not quantified
because it is outside tested specification parameters.
4. Reference the Bandwidth section in the Enhancements chapter of this

book. Bandwidth and step response design must consider noise immunity
tolerances.
Optional Bandwidth Components (RD-19230 and RD-19240)

The RD-19230/RD-19240 converters provide the option of using a second set
of bandwidth components. The second set of components can be used for
switch-on-the-fly or dual-bandwidth applications. The SHIFT and UP /DN
inputs are used when switching bandwidth components, and their operation
is described below. Refer to the block diagram, Figure 4.
Shift (RD-19230 and RD-19240)

The SHIFT pin is an input that chooses between the VEL1 and VEL2
bandwidth components. This pin has an internal pull-up to +5V. When the
SHIFT pin is left open, or a logic 1 is applied, the VEL1 components are
selected. When a Logic 0 is applied, the VEL2 components are selected. The
deselected set of bandwidth components are driven by an amplifier, with
programmable gain, that follows the velocity amplifier. This amplifier can be
used to pre-charge the deselected set of components to the voltage level that
is expected after a change in resolution. (See description in the Benefit of
Switching Resolution on the Fly section.)

THE BASICS
UP /DN (RD-19230 and RD-19240)

The UP /DN input selects the gain of the amplifier driving the de-selected set
of bandwidth components. UP /DN has three input states. See Table 15 to
relate input to gain.
Table 15. Precharge Amplifier Gain Programming

PU/DN GAIN FUNCTION
Logic 0 4 Preset Resolution to
Increase
Logic 1 1/4 Preset Resolution to
Decrease
-5V 1 Dual Bandwidth
Benefit of Switching Resolution on the Fly

(RD-19230 and RD-19240)
Switching resolution on the fly can be used in applications that require high
resolution for accurate position control, and tracking rates or settling times
that are faster than the high resolution mode will allow.
The converter can track four times faster for each step down in resolution
(i.e., a step from 16 bits to 14 bits). The velocity output will be scaled down by
a factor of four with each step down in resolution. For example, if the velocity
output is scaled such that 4 Volts = 10 RPS in 16 bit resolution, then the
same converter will output 1 Volt for 10 RPS in 14 bit resolution. To avoid
glitches in the velocity output, the second set of bandwidth components can
be pre-charged to the expected voltage, and switched in using the SHIFT
input at the same time the resolution is changed. This will allow for a smooth
velocity transition, resulting in reduced errors and minimal settling time after
the change.
Figure 26 shows the way the converter behaves during a change in

resolution while tracking at a constant velocity. The first illustration shows the
benefits of switching in pre-charged components while changing resolution.
The second illustration shows the result without the benefits of switching on
the fly.
The signals that have been recorded are:
1) VEL: velocity outputs pin on the converter
2) ERROR: this is the analog representation of the error between the input
and the output of the converter
3) D0: an input resolution control line to the converter

THE BASICS
4) BIT : built-in test output pin of the converter
When this system uses the switch resolution on the fly implementation,
the velocity signal immediately assumes the pre-charged level of the
second set of components, resulting in small errors and reduced settling
times. Notice that the BIT output, in Figure 26, does not indicate a fault
condition.
When this system type does not use the switch resolution on the fly
implementation, large errors and increased settling times result. The
errors exceed 100 LSBs causing the BIT to flag for a fault condition.
Switch On the Fly Implementation (RD-19230/RD-19240)

The following steps detail switching resolution on the fly.
1) The SHIFT pin should be controlled synchronously with the change in

resolution. When shift is logic high, the VEL1 components will be
selected. When shift is logic 0, the VEL2 components will be selected.
2) The second set of BW components (CBW2, RB2, CBW2/10) should

typically be of the same value as the first set (CBW1, RB1, CBW1/10,)
and should be installed on VEL2 and VEL SJ2.
Note: Each set of bandwidth components must be chosen to insure that

the tracking rate to BW ratio (listed in Table 11) is not exceeded for the
resolution in which it will be used.
3) UP/DN will program the gain of the pre-charged components/amplifier.

If the resolution is going to increase, (UP/DN logic 0) the gain of the pre-
charge amplifier will be set to 4. If the resolution is going to decrease
(UP/DN logic 1) the gain of the pre-charge amplifier will be set to ¼. The
gain of the pre-charge amplifier should be programmed prior to switching
the resolution of the converter, allowing enough time for the components
to settle to the pre-charged level. This time will depend on the time
constant of the bandwidth components being charged. If switching is
limited to two adjacent resolutions (i.e., 12 and 14) then the pre-charge
amplifier can be set up to continuously maintain the appropriate velocity
voltage on the deselected components, resulting in the fastest possible
switching times. See Figure 25 for an example of the input wiring
connections necessary for switching on the fly between 12- and 14-bit
resolution.

THE BASICS
GND
D1
RD-19230/RD-19240
Control D0
SHIFT
UP/DN
Figure 25. Input Wiring – Switch On The Fly Between 12 and 14 Bit Resolution
Dual Bandwidths
With the second set of BW component pins, the user can set two bandwidths
for the converter and choose between them. To use two bandwidths, proceed
as follows:
1) Tie UP /DN to pin GND.
2) Choose the two bandwidths following the guidelines in the General Setup
Considerations; the RV resistor must be the same value for both bandwidths.
3) Use the SHIFT pin to choose between bandwidths. A logic 1 selects the
VEL1 components and a logic 0 selects the VEL2 components.

THE BASICS
With Switch Resolution on the Fly Implemented
0V
VEL
-5V
ERROR 0˚
5V
D0
0V
5V
BIT
0V
ERROR = 13.6 LSBs per box
Without Switch Resolution on the Fly Implemented
0V
VEL
-5V
ERROR 0˚
5V
D0
0V
5V
BIT
0V
ERROR = 1500 LSBs per box

Figure 26. Benefit of Switching Resolution On the Fly
Note: Depending on the bandwidth, step error may be greater. Less velocity
or movement will lessen the error glitch shown in the graph. The graph shows
a worst-case condition based upon one bandwidth and tracking rate setup.
Worst case is when the overshoot on the velocity hits the saturation point as
per the graph.

THE BASICS
Transfer Function And Bode Plot

The RD/RDC series transfer function block diagram and bode plots (open
and closed loop) are shown in Figure 27 and Figure 28.
VELOCITY
OUT
ERROR PROCESSOR
VCO
CT A1 S + 1
RESOLVER + A2 DIGITAL
e B
INPUT S POSITION
(θ) S S +1
- 10B OUT (φ)
H=1
Figure 27. Transfer Function Block Diagram

-1
2d
b/o
(CRITICALLY DAMPED)
ct
GAIN = 4
2A
OPEN LOOP ω (rad/sec)
B A -6
db 10B
(B = A/2) /oc
t
GAIN = 0.4
f BW = BW (Hz) = 2A
π
2A 2 2A
CLOSED LOOP ω (rad/sec)
Figure 28. Bode Plot

THE BASICS
The dynamic performance of the converter can be determined from the

transfer function (see Figure 27).
The open loop transfer function is as follows:
⎛S ⎞
A 2 ⎜ + 1⎟
Open loop transfer function= ⎝B ⎠
⎛ S ⎞
S2 ⎜⎜ + 1⎟⎟
⎝ 10 B ⎠
2
Where A is the gain coefficient and A = A1A2
and B is the frequency of lead compensation
The components of gain coefficient are error gradient, integrator gain, and
VCO gain. These can be broken down as follows (see Figure 2, Figure 3,
and Figure 4):
- error gradient = 0.011 volts per LSB (ct + error amp + demod with
2 Vrms input)
CSFS
- integrator gain = volts per second per volt
1.1CBW
1
- VCO gain = LSBs per second per volt
1.25RVCVCO
where: CS = 10 pF
FS = 67 kHz when Rs = 30 kΩ (RDC-19220/2/4 Series)
FS = 100 kHz when Rs = 20 kΩ ( RDC-19220/2/4 Series)
FS = 134 kHz when Rs = 15 kΩ ( RDC-19220/2/4 Series)
CVCO = 50 pF (RDC-19220/2 Series)
where:FS = 67 kHz for R CLK = 30Ω (RDC-19220/2S, RD-19230 & RD-

19240 Series)
100 kHz for R CLK = 20Ω (RDC-19220/2S, RD-19230 & RD-19240 Series)
125 kHz for R CLK = 15Ω (RDC-19220/2S, RD-19230 & RD-19240 Series)
RV, RB, and CBW are selected by the user to set velocity scaling and
bandwidth.

THE BASICS
Once the external component values are known, the A1 and A2 can be
calculated as follows:
1
A1 = 0.011•
Ri • CBW • 1.1
1
A2 =
RV • CCVO • 1.25
1
Ri =
CS • FS
where:
CS = 100pF
A 2 = A1A 2
A
and B =
2
Example:
Given the following parameters, determine A1 and A2:
Reference: 2.4 kHz
Resolution: 16 Bits
Bandwidth: 300 Hz
Maximum Tracking:18 RPS
External component values are determined using the component selection

software and are as follows:
Rv = 54 kΩ
CBW = 4390 pF
CBW/10 = 439 pF
RB = 683 kΩ
RC = 30 kΩ

THE BASICS
RS = 30 kΩ
Therefore, from the equations on page 51: 4
1
Ri =
(100pF)(67kHz)
1
A1 = 0.011•
(1.5 • 10 ) • (4390 • 10−12 ) • (1.1)
6
A1 = 1.52
1
A2 =
(54 • 10 ) • (50 • 10−12 ) • (1.25)
3
A 2 = 296,000
Type II Tracking Converters

The RD/RDC series converters are Type II tracking converters. The benefit in
using this technique is the ability to obtain digital position and analog velocity
data. The device has a control transformer that develops an error signal
between the input position angle θ and the data in the internal up/down
counter φ. This error is integrated to yield a velocity voltage. This voltage is
then input to the voltage-controlled oscillator (VCO) which drives the up/down
counter. As the internal error approaches zero, the output of the up/down
counter φ will be equivalent to the input position angle θ. The RDC-19220/2/4,
RDC-19220/2S, & RD-19230 series produce up to 16 bits of digital position
data, and the RD-19240 produces up to 14 bits of digital position data.

THE BASICS
Table 16 lists a method of interpreting the digital output (φ).

Binary Output
Coding.
Table 16. Output Data For A Synchro Or Resolver
Input in 16 Bit Digital Output (φ) (1 = MSB, 16 = LSB)
Degrees (Hex)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0° (0000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15° (0AAB) 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1
30° (1555) 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
45° (2000) 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
60° (2AAB) 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1
75° (3666) 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1
90° (4000) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
120° (5555) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
135° (6000) 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
180° (8000) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
240° (AAAB) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1
270° (C000) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
285° (CAAB) 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1
300° (D555) 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
315° (E000) 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
330° (EAAB) 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1
345° (F555) 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1
359° (FFFF) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

THE BASICS
Further interpretation of the digital output φ is straightforward once the bit

weights are known. As shown in Table 17 the bit weight of bit 16, in degrees,
is 0.0054932°, bit 15 is 0.0109863°, and so on. For more examples see the
Binary-to-Decimal Conversion section.
Table 17. Binary Angle Relationships

n
Resolution 2 LSB As % Degrees/Bit Minutes/ Radians/Bit
In Bits Of Full Bit
Scale
0 1 100 360 21600 6.28318531
1 2 50 180 10800 3.14159265
2 4 25 90 5400 1.57079633
3 8 12.5 45 2700 0.78539816
4 16 6.25 22.5 1350 0.39269908
5 32 3.125 11.25 675 0.19634954
6 64 1.5625 5.625 337.5 0.09817477
7 128 0.78125 2.8125 168.75 0.04908739
8 256 0.390625 1.40625 84.375 0.02454369
9 512 0.1953125 0.703125 42.1875 0.01227185
10 1024 0.09765625 0.3515625 21.09375 0.00613592
11 2048 0.04882813 0.1757813 10.54688 0.00306796
12 4096 0.02441406 0.0878906 5.27344 0.00153398
13 8192 0.01220703 0.0439453 2.63672 0.00076699
14 16384 0.00610352 0.0219727 1.31836 0.00038350
15 32768 0.00305176 0.0109863 0.65918 0.00019175
16 65536 0.00152588 0.0054932 0.32959 0.00009587
To interpret the digital output for a LVDT input refer to Table 7 & Table 8.
Resolution Control (RDC-19220/2/4, RDC-19220/2S “A” & “B” &

RD-19230, RD-19240 “D1” & “D2”)
These inputs are used to program the output resolution. As resolution is
reduced, i.e., switched from 16 to 14 bits, pairs of bits are removed from the
output circuitry beginning with the LSB (bit 16). These unused bit pairs are
set to zero. Additionally, as resolution is reduced dynamic performance
capabilities increase by a factor of four due to the internal gain switching.

THE BASICS
Binary-To-Decimal Conversion
Conversion from binary to decimal angular data is simply a matter of adding
all the decimal angular weights for all of the binary bits which are set to logic
1.
For example, if the converter is set for 16-bit resolution and the binary
measurement is:
MSB (Bit 1) 0110110000000000

LSB (Bit 16)
The decimal angle will be:
(from degrees/bit column in Table 17)
(0 • 180) Bit 1 is logic low
+(1 • 90)Bit 2 is logic high
+(1 • 45)Bit 3 is logic high
+(0 • 22.5)Bit 4 is logic low
+(1 • 11.25) Bit 5 is logic high
+(1 • 5.625) Bit 6 is logic high
+(0 • All Other Bit Weights) All remaining Bits are logic low
Total = 151.875°
If the 16-bit binary value is treated as a decimal integer (in this example, it
has the hex value of 6C00H and the decimal value of 27648), the decimal
angle, in degrees, can be calculated by the following formula:
Angle, in degrees = 360 • Decimal Integer Value
65536

THE BASICS
Encoder Emulation (RDC-19220/2/4 Series)

There are systems that may require an incremental encoder output. The
RDC-19220 can be used to convert resolver signals into incremental encoder
Replacing
encoder with
signals. Figure 29 illustrates the additional external components needed for
resolver. an encoder output.
R2 U2D
2k 74AC86
13
C2 11
RDC-19220 220 pF A
12
U2A
74AC86 R1 U2B
LSB +1 2 2k 74AC86
3 4
1 C1 6 B
LSB 220 pF 5
R3 U2C
2k 74AC86
9
CB/NRP
C3 8
120 pF 10 NRP
EL
D1
1N4148
-5 V
NOTE: CMOS LOGIC IS RECOMMENDED. TTL AND TTL
COMPATIBLE LOGIC WILL SKEW THE DELAYS.
Figure 29. Filtered/Buffered Encoder Emulator

THE BASICS
Tying EL to -5v changes the function of the converter busy (CB) output of the
converter to a Zero Index (ZI) or North Reference Pole (NRP) and the LSBs
are enabled. The Inhibit INH input can not be used to freeze the data on the
output lines because the A quad B (or incremental encoder signals) will be
lost.
The timing of the A, B and ZI output is dependent on the rate of change in

which the synchro/resolver is spinning (RPS or °/s) and the resolution of the
converter. Figure 30 shows the timing for the incremental encoder (number
of counts per revolution). The calculations for the timing and the number of
counts per rotation are as follows:
n
Counts = 2 ; n = resolution in bits
360°
t=
(Counts) (Velocity{ °/s})
360°
T=
Velocity (°/s)
A(LSB+1)
2t
B(X-OR
LSB & LSB+1)
ZI(CB) t
0
0 T 359.95
0
Figure 30. Output Timing

THE BASICS
Encoder Emulation (RD-19230 & RD-19240 Series)

The RD-19230 and RD-19240 can be programmed to encoder emulation
mode by connecting the A _ QUAD _ B input to GND. The U/B output pin
becomes B (LSB XOR LSB + 1). The A (LSB + 1) and B output signals can
be used in control systems that are designed to interface with incremental
optical encoders. To enable the Zero Index pulse, ZIP _ EN should be tied to
GND.
The resolution of the incremental outputs is latched from the D0 and D1

inputs on the low going edge of A _ QUAD _ B . The resolution of the parallel
data outputs may be changed any time after the encoder resolution is latched
(see Figure 33).
Note: The encoder resolution must be less than or equal to the resolution of
the parallel data outputs. Refer to Figure 31.
The timing of the A, B and ZIP (or North Reference Pole [NRP]) output is
dependent on the rate of change of the synchro/resolver position (rps or
degrees per second) and the encoder resolution latched into the RD-19230
and RD-19240 (refer to Figure 32). The calculations for the timing are:
n = encoder resolution latched into RD-19230 or RD-19240
t = 1 / ( 2n* Velocity(RPS))
T = 1 / ( Velocity(RPS))
Clarification of A_QUAD_B , U/B and ZIP_EN Functions

The RD-19230 and RD-19240 are tracking converters that are designed with
a Type II closed servo loop. The Type II closed servo loop has an internal
incremental integrator. This integrator acts as an up-down position counter.
An AC error (e) within the RD-19230 and RD-19240 represents the difference
between θ (current angle to be digitized) and φ (the angle stored in digital
form in the up-down counter). Because they are Type II closed loop
servomechanisms, the converters are continuously attempting to null the
error to zero. This is accomplished by counting up or down 1 LSB until φ is
equal to θ thus having an error of zero.
When A _ QUAD _ B is logic 0, encoder emulation mode is selected (i.e. The

U/B output [Pin 29] is programmed to B). The encoder emulator resolution is
set on the falling edge of A _ QUAD _ B (see Table 18).

THE BASICS
When A _ QUAD _ B is logic 1, encoder emulation mode is not selected (i.e.,

The U/B output is set to U, which indicates the direction of the internal
position counter).
Table 18 A_QUAD_B (Pin 30) Function

A Quad_B (Pin 30) Function U/B (Pin 29)
0 B
1 U
Table 19. ZIP_EN (Pin 55) Function

ZIP_EN (Pin 55) CB/ZI (Pin 31)
0 ZI
1 CB
Note: U indicates the direction of the counter. It stands for “UP”. If the RD-
19230/RD-19240 is at a static angle awaiting a new angle θ, U indicates the
direction the counter was going to get to the current angle φ. As the error is
approaching zero, the internal analog circuitry voltage may over shoot before
settling - which would then indicate an incorrect direction. Because of this
over shoot, the U output should not be relied on after settling to a static state.
Only during active resolver movement will the U output state be reliable. U is
a logic 1 when going in the positive direction (increasing angle). It is a logic 0
when going in the negative direction (decreasing angle). This is the same as
it is in the RDC-19220.
ZIP _ EN chooses between the CB and Zero Index pulse outputs and is
independent of encoder emulation mode. A logic 1 enables the CB pulse, a
logic 0 enables the Zero Index pulse (see Table 19).
Note: When the RD-19230 is set for 16-bit mode, the LSB is bit 16. When the
RD-19230 is set for 14-bit mode, the LSB is bit 14 and bits 15 and 16 are set
to logic “0”. This is also the same for the RD-19240 except it will only operate
in 10-, 12-, 14-bit modes.

THE BASICS
RD-19230
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BIT 16 LSB
1 1 1 1
0 2 4 6
A
Figure 31. Incremental Encoder Emulation Resolution Control
B(X- or LSB & LSB+1)

2t
A (LSB+1)
ZIP (NRP)
t
0 T 359.95
Figure 32. Incremental Encoder Emulation
DATA
D0/D1 VALID
50 nsec
A QUAD B
Figure 33. Timing for Incremental Encoder Emulation

Resolution Control

THE BASICS
Velocity Output
A benefit of using a type II tracking Synchro/Resolver-to-Digital converter is
the analog velocity output. The velocity on the RD/RDC series is scaled by
the mandatory external component RV. If the application is using a +5 V and
a -5 V power supply the maximum tracking rate will be equal to ±4 V (±
depending on the direction of rotation). If the converter is used in +5 V only
mode, the maximum tracking rate should be scaled to ±3.5 V (see Figure 34).
The velocity characteristics have been broken down into four specifications:
1. scale factor error
2. reversal error
3. linearity
4. zero offset
Scale factor error is the gain error for the positive rotation and the gain error
for the negative rotation averaged together. Gain error for either positive or
negative rotation is the average of the percent error between the actual
measured velocity reading and the theoretical velocity output at certain
speeds in that direction. For example, if the percent error at 10 RPS is 5%
and the percent error at 5 RPS is 4% the gain error is 4.5%.
Reversal error, or bipolarity, is half the difference between the positive gain
error and the negative gain error.
Positive or negative linearity is half the difference of the full-scale percent

error and the half-scale percent error.
Zero offset is the measured velocity at a static position (speed of the resolver
= 0 RPS).
When measuring velocity, the return should be with respect to AGND. The
AGND provides a reference for analog signals. (No current drop)

THE BASICS
Velocity Specifications
Velocity
Voltage
Actual Avg
Max Linearity
Actual
Theoretical
Scale Factor
Max RPS
(a)
Velocity Specifications
+V
+ Actual
Theoretical
+ Slope
Offset
-RPS +RPS
Reversal Error ( Bipolarity )
= Difference in + Slope to
- Slope - Slope
- Actual
-V
(b)
Figure 34. Velocity Specifications

THE BASICS
Velocity Ripple
The velocity signal is a DC signal with an ac ripple. This is a by-product of the
conversion technique. The main components of the ripple are carrier
frequency and twice the carrier frequency, which can be filtered as seen in
Figure 35. Set the RC to cut-off below the carrier frequency.
R
VEL +
-
C
(
τ = RC = 1/A
NOTE: Choose an Op-Amp with an offset less than 1mV.
Figure 35. Velocity Ripple Filter
Using Velocity Output to Monitor Speed

The velocity output of the converter has mandatory timing components on the
line which greatly effect the converters function. To use the velocity output
line to monitor speed, you must add a buffer to the line as shown below.
Figure 36. Example Of Velocity Output Speed Monitor

THE BASICS
Built-In Test (BIT)

The BIT pin is a digital output that for normal operation will be a logic high. If
a fault is indicated the BIT output will be a logic low until the fault condition no
longer exists. The BIT will not function for DC applications; It will remain a
logic “0”. The three causes of a fault indication are as follows:
BIT will not
function for DC 1.LOS (Loss of Signal) - this checks the threshold voltage of the input signals
applications.
(+S/-S and +C/-C) to a level of 0.5 volt. If both input signals drop below this
BIT will remain a
logic “0” value, the BIT flag is set low. Because normal angle rotation causes each
because the line to drop below this value (i.e., the SIN input at 0° = 0 volts), it is required
reference is that both signals fall below this value (abnormal condition) before BIT is set.
missing an ac
component. Note: The LOS contains a filter, to filter out the reference. Depending on
specific converter the lowest specified frequency is 47hz (~21ms). The filter
must have a time constant long enough to filter this out. Time constants of
50ms or more are possible.
2. Phase error - to prevent 180° hang up, the input signal

phase is compared to the phase of the reference input. If this condition
fails, the BIT signal is set. This also forces a change into the system to
relieve the error. Therefore, if this was the cause for the BIT , large
changes would occur in the digital output while the system tries to find the
correct answer.
3. Excessive error - if the digital output is more than 100 LSBs different from
the input angle, a BIT is generated. This can happen normally during large
step changes of the input and high accelerations which cause an acceleration
lag. In a static mode this should not be a problem. Since the R/D is an analog
system, the power supply quality is a concern. If the power supply dips, it
may cause the signal level to drop at the output of the input buffer amplifiers.
This may cause the signal level to drop enough to indicate an LOS. Also, the
distortion of the input signal may cause significant error in the error channel.
A 500µs dynamic delay occurs before the excessive error BIT becomes
active. This dynamic delay is responsive to the active filter loop.
4. For only RDC-1922XS, RD-19230, and RD-19240 versions LOR (Loss of

Reference) – Reference input less than 500mv will generate a BIT .

THE BASICS
Timing
Converter Busy (CB) Timing

Each pulse of the converter busy (CB) signal indicates that the tracking
converter output angle is changing 1 LSB. The digital output data is available
in two 8-bit bytes, and can be transferred to an 8- or 16-bit data bus. As
shown in Figure 37, the output data is valid 50 nsec maximum after the
middle of the CB pulse. The CB pulse width is 1/ (40 x Fs) (internal sampling
frequency).
(375 nsec nominal)
CB
*
50 ns
DATA DATA
DATA VALID VALID
* Next CB pulse cannot occur for a minimum of 150 nsec.

Figure 37. Converter Busy Timing
Table 20. Converter Busy Pulse Width

Rs Value Fs: Sampling CB Pulse Data Valid From
(kΩ) Frequency Width Leading Edge Of CB
(kHz) (nsec) (nsec)
30 67 375 238
20 100 250 175
15 134 186 143
Note: Refer to the specific converter data sheet for timing specifications.
EL
Data Latch Data Out
EM
INH
CB
Enable
INH
Figure 38. Output Data Latch Configuration

THE BASICS
Table 21. Converter Busy Pulse Width

Signal Type Description
Output CB: Converter busy pulse. Indicates data is changing by 1 LSB
Input EM: Enable most 8 significant data bits. Used for 8-bit bus data
transfer
Input EL: Enable least 8 significant data bits. Used for 8-bit bus data
transfer
Input INH: Inhibit. Used to inhibit the entire 16-bit data word for a
data read.
Timing
Timing For Reading Digital Output Data

The digital output data of the RD/RDC series is available in two 8-bit bytes.
Each byte is controlled by an enable pin. EM controls bits 1-8, and EL
controls bits 9-16. The data can be transferred to an 8-bit or 16-bit data bus
system.
For an 8-bit system, the MSB and LSB bytes are transferred sequentially. For
a 16-bit system all bits are transferred simultaneously.
When EM and EL are in a valid logic high state, the digital output is in a high
impedance tri-state mode.
Data Transfer To an 8-Bit Bus

Figure 39 and Figure 40 show the connections and timing for transferring the
data from the converter to an 8-bit bus.
Note: The converter INH line may be applied regardless of the CB signal
state, as the INH line will not latch until CB is not busy.
1. The converter Inhibit ( INH ) control is applied and must remain low for a
minimum of 300 nsec before valid data is available.
2. The Enable Most significant byte ( EM ) is set to a low state (logic 0) and
must remain low for a minimum of 150 nsec before the MSB data (bits 1
through 8) is valid and transferred.
3. After EM is set to a high state (logic 1), the Enable Least significant byte
( EL ) is brought low 150 ns minimum before the LSB data (bits 9 through 16)
is valid and transferred.

THE BASICS
4. EL should go high (to logic 1) at least 100 nsec maximum before another
device uses the bus.
5. INH is set high and the data transfer is done. The data refresh cycle can
begin.
(MSB) BIT 1 D7(MSB)

EM
BIT 2 D6
EL
BIT 3 D5
BIT 4 D4
BIT 5 D3 8 BIT BUS
BIT 6 D2
RD/RDC BIT 7 D1
SERIES BIT 8 D0 (LSB)
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
(LSB) BIT 16
INH
Figure 39. Data Transfer to 8 Bit Bus
INH
300 ns MAX
;;;; ;;;
EM 150 ns MIN
;;;;;;;
DATA 1-8
100 ns MAX
VALID
;;;;;; ;
EL 150 ns MAX
;;;;;;;
DATA 9-16
VALID
100 ns MAX
Figure 40. Timing for Data Transfer To 8-Bit Bus (RDC-19220/2)

THE BASICS
Data Transfer To a 16-Bit Bus

The maximum time for the RD/RDC series parallel data outputs Bits 1 (MSB)
through 16 (LSB) to become valid following the INH signal being asserted
low and while EM and EL are set to logic low (or tied to ground) is computed
as follows: The worst-case delay occurs when the INH signal is brought low
simultaneously with the rising edge of the CB (Converter Busy) pulse.
Referring to Figure 41 (a) the maximum CB pulse width is 750 nsec therefore
the maximum time from rising edge to mid-point of this pulse is 375 ns. As
shown in Figure 41 (a), the internal counters increment or decrement will be
50 ns maximum following the mid-point of the CB pulse.
Referring to Figure 41(b), since INH has already been asserted low, the
output of the RD/RDC series transparent latch settles to a valid value within a
maximum of 150 ns after the internal counter value is stable. Therefore, the
overall worst-case delay from INH low to RD/RDC series output data valid =
375 + 50 + 150 = 575 ns. This allows the user to read valid data without
having to monitor the CB pulse.
250 to 750 nsec
CB
50 ns
DATA DATA
DATA VALID VALID
(a)
INHIBIT
150 ns max
(b)
Figure 41. RD-19230/RD-19240 Timing: CB and INHIBIT
Sample 16-bit data read sequence with EM and EL set low:

1. Inhibit (set to Low).
2. Wait 575 ns.
3. Read 16-bit data bus.
4. Inhibit (set to High).
5. Repeat next data read from number 1.

THE BASICS
Interfacing the RD/RDC with an IBM PC/XT/AT®

The converter can be connected to an IBM PC/XT/AT through the IBM PC
Bus located at address HEX 300 through 303. The PC for prototype cards
reserves this location. Figure 44 illustrates the connection to the IBM PC Bus;
Figure 43 illustrates the timing considerations for the interface.
RD/RDC to IBM PC/XT/AT Theory of Operation

1. The port address where the converter is hard wired with jumpers into the
74LS688 address decoder. This address is HEX 300 through 303 and is
reserved for prototype cards.
2. Address line A1 selects the upper or lower of the RD/RDC to be placed on

the Bus. When A1 is high, bits 1-8 are selected.
3. Address line A0 sets and resets the converter INHIBIT line. When A0 is
low, the INHIBIT command INH is invoked.
4. To read the output of the converter, perform the following:
a. Send address HEX 302 to INHIBIT the converter
(hold data stable) and place bits 1-8 on the Bus.
Read and store data on D0 to D7.
b. Send address 300 HEX to keep the converter in
the INHIBIT mode and place bits 9-14 on the Bus.
Read and store data on D0 and D7.
c. Read address 301 HEX or 303 HEX to release the
converter from the INHIBIT mode and prepare for
the next measurement. No valid data will be on the
bus during this command.
5. Since the output data is not valid until 0.5 µs after the INHIBIT command is
invoked, the I/O READY line is held low for this period of time. When I/O
READY returns to the high level, the data on the bus reads on the next
negative clock edge.

THE BASICS
EM EL
(MSB) BIT 1 D15 (MSB)

BIT 2 D14
BIT 3 D13
BIT 4 D12
BIT 5 D11
BIT 6 D10
BIT 7 D9
RD/RDC BIT 8 D8
SERIES 16 BIT BUS
BIT 9 D7
BIT 10 D6
BIT 11 D5
BIT 12 D4
BIT 13 D3
BIT 14 D2
BIT 15 D1
(LSB) BIT 16 D0 (LSB)
INH
Figure 42. Data Transfer To 16-Bit Bus
Figure 43. PC Application – I/O Read Cycle Timing

THE BASICS
BIT 16(LSB)
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10 500 nSEC MIN

PULSE
BIT 9 74LS121
Q
BIT 8
D7 Y1 RD/RDC
BIT 7
D6 Y2
BIT 6
D5 Y3 A2
BIT 5
D4 Y4
BUS DRIVER
BIT 4
D3 Y5 74LS465
BIT 3 74LS467
D2 Y6
BIT 2 INH Q CLK
D1 Y7
BIT 1 (MSB) D
D0 Y8
G EM EL
IBM
BUS
Y1 Y2 Y3 Y4
I/O READ G 74LS374
ALE
A1 A2 A3 A4
G P=Q 3 STATE
A9 P0 Q0 BUFFER
A8 P1 Q1
A7 P2P Q2
ADDRESS ADDRESS
A6 P3 DECODER Q3 SELECTION
74LS688 JUMPERS
A5 P4 Q4
A4 P5 Q5
A3 P6 Q6
A2 P7 Q7
A1
A0
I/O READY
Figure 44. RD/RDC to PC Connection Diagram

SYSTEM DESIGN
Typical System Design Example Using the RDC-19220/2/4
A six step example of how to design the RDC-19220/2/4 Series Converter into a
system is illustrated below.
Step 1. Complete the system design checklist form:

1. Mechanical Options (choose one)
Through Hole configuration.................................................................... select RDC-19220

Surface Mount (S/M) configuration ............................................... select RDC-19222 (303)
2. System DC Power Availability (choose one)

Example System
requires surface
Example system +5 VDC available: Incorporate externally-generated mount components.
supply’s only +5 VDC. -5 VDC supply into circuit design: .......................................... select RDC-19220 The -303 ordering
Because the RDC- option (see ordering
19222 has already or Use the built-in -5 VDC feature: ........................................... select RDC-19222 information in
been chosen based on Mechanical
the mechanical Specifications
configuration, the +/- 5 VDC available: Use both supplies: ............................................ select RDC-19220 section) was chosen
built-in -5 VDC feature because the
must be used. or Use both supplies, and temperature range of
disregard built-in -5 VDC feature .......................................... select RDC-19222 the example system
will not exceed 0°C
to 70°C.
3. Input Requirements (fill in)
Synchro or Resolver ................................................................................. Res Syn/Res

Single Ended or Differential ...................................................................... Diff SE/Diff
Transformer Isolation ............................................................................... No Yes / No
Reference Voltage ................................................................................... 26 Vrms
Choose Resistor
Network to achieve an Carrier Frequency .................................................................................... 2000 Hz
input signal of 2 Vrms Signal Amplitude ...................................................................................... 11.8 Vrms
based on the previous Resistor Network..................................................................................... DDC57470 0
information. ................................................................................................ DDC49530 (11.8 Vrms)
........................................................................................... or DDC57470 (11.8 Vrms S/M)
...................................................................................................... or DDC49590 (90 Vrms)
........................................................................................................ or Other (user defined)
4. Accuracy Requirements (choose/fill in)
Resolution ..........................................................................................10 12 14 16 Bits

Bandwidth restrictions Accuracy ...................................................................................... 2.3 Minutes
are:
BW = 1/4 Fc (see Table 5. Dynamic Characteristics (fill in) to be used in the external component calculation program
11. Tracking rate vs. BW)
Carrier Frequency ......................................................................................... 2000 Hz

Resolution .................................................................................................... 16 Bits
Tracking Rate (MAX) ................................................................................... 10 RPS
Desired Bandwidth........................................................................................ 100 Hz

SYSTEM DESIGN
Typical System Design Example (continued)

Step 2. Calculate values for mandatory external components:
Using the parameters from the previous example checklist, values for the
mandatory external components have been calculated using DDC’s
Component Selection Software and are shown below. For more information
on the mandatory external components and DDC’s Component Selection
Software, see the Basics section.
RV = 100kΩ
CBW = 0.022μF
CBW
= 2200pF
10
RB = 410kΩ
RS = 30kΩ
RC = 30kΩ
RB = CBW =
410k Ω 0.022µf
VELOCITY
CBW =
10 Rv =
2200pf
100k Ω
RS = RC=
30kΩ 30kΩ
18 19 9 10
-VSUM VEL
8
-VCO
RDC-19222 29 to 44
DIGITAL
OUTPUT
16
Figure 45. Mandatory External Component Values and Connections

SYSTEM DESIGN

Step 3. Calculate values for reference input scaling resistors:
Based on the information from the previously completed checklist, the
reference is 26 Vrms. However, as detailed in the Reference Input section of
this manual, the reference input to the RDC-19220 Series Converter must be
scaled down. For this step, refer to Figure 46, and let R1 = R3 and R2 = R4.
For the RDC-19220/2S, RD-19230 and RD-19240 converters, select R1
through R4 to limit the reference to between 1.5V and 5V peak. For the RDC-
19220/2, select R1 through R4 to limit the reference to between 1.0V and 5V
peak.
xVRMS R1 + R 2
Using the formula =
2Vrms R2
where xVRMS = the reference excitation in Vrms and
R2 is given as 10 kOhm
then R1 = R4 = 130 kOhm
Note: For circuits where no voltage adjustment is required add a 10k ohm
series resistor for oscillator turn on protection.
– SIGNAL REF
26 VAC
+SIGNAL REF
R1 = 130k Ω R2 = 10kΩ
R3 = 130k Ω R4 = 10kΩ
7 6
-REF +REF
15
SIN
16
-S
RDC-19222
14 +S
Figure 46. Reference Input Scaling Resistors

SYSTEM DESIGN

Step 4. Install input signal scaling resistors:
Based on the information from item 3 of the checklist, the DDC-57470 thin-film
resistor network is required to scale down the input signals. Refer to Figure 47
for placement of the thin-film network.
Note : For circuits where no voltage adjustment is required add a 10k ohm 1%
tolerance resistor to the SIN and COS line for circuit turn on protection.
57470
3 15
SIN
Rf
1 Ri
S1 16
2 -S
+R Ri
-R S1 S3 6 14 +S
S3
S4 Rf
RESOLVER S2 RDC-19222
A GND 4
13
Rf 12 COS
16 Ri
S4 15
7 Ri 13 -C
S2
8 10 11 +C
Rf
12
Figure 47. Input Signal Scaling Resistor Placement

SYSTEM DESIGN
Step 5. Set-up power supply input:

Based on item 2 of the example checklist form it has been determined that the
RDC-19222 converter will be used with the built-in -5 VDC feature. The
recommended values for external capacitors and their placement are shown
in Figure 48. The power supply 47µf caps shown can be substituted with 10µf
caps if the power supply lines are clean with minimal noise.
29 to 44
DIGITAL
OUTPUT
16
28
CB
RDC-19222 27 BIT
-CAP 23
10 µf
25 +
+CAP
(-5c)-5v(+5c) +5v
22 17 26 2 POWER
3 4 5 1 20 SUPPLY
+5VDC
47u f
0.01uf +
0.01uf
INH EM +
EL 47uf
A B
{
RESOLUTION
CONTROL
Figure 48. Power Supply Set-up
Figure 49 illustrates the example system circuitry with all five steps combined.
Using more than 1 RD/RDC converter on a common bus

Note that when operating more than one RD/RDC converter on a common
bus may result in noise on the velocity output. RD converters on a common
bus can start to talk to each other if the clocks are at the same frequency and
the charge pump mode is used to generate the –5V for the RD. Offset the
Rclock resistors on the RD converters by 3k.

SYSTEM DESIGN

– SIGNAL REF RB = CBW =
410k Ω 0.022µf
26 VAC VELOCITY
+SIGNAL REF CBW =

10 Rv =
2200pf
R1 = 100k Ω 100k Ω
R2 = 10kΩ
RS= RC=
R3 = 100k Ω R4 = 10k 30kΩ 30kΩ
57470 7 6 18 19 9 10
-REF +REF RS RC -VSUM VEL
3 15
SIN 8
Rf -VCO
1 Ri
S1 16
2 -S
+R
Ri
-R S1 S3 6 14 +S 29 to 44
DIGITAL
S3 OUTPUT
S4 Rf 16
RESOLVER S2 A GND 4
RDC-19222
28
CB
13 27
Rf 12 COS BIT
16 Ri
S4 15
7 Ri 13 -C
S2
8 10 11 +C
Rf
AGND GND -CAP +CAP (-5c)-5v(+5c) +5v
12
23 25 22 17 26 2 POWER
21 24 3 4 5 1 20 SUPPLY
+5v
10uf 0.01uf 0.01uf
INH EM
EL
A B
1000pf
{
RESOLUTION
RESISTORS SELECTED TO LIMIT V REF TO BETWEEN 2V AND 4V PEAK 47u f
CONTROL
Figure 49. Complete System Design Example Circuitry
Grounding Tips
When designing with the RD/RDC Series Converter’s, special consideration
should be given to the two ground connections, Ground (GND) and Analog
Ground (AGND). These two internal ground planes help to reduce noise in the
analog input signal from the digital ground currents. The digital inputs and
outputs are referenced to GND, and the resolver inputs and velocity output
are referenced to AGND. To minimize ground loop noise, and therefore
unstable output results, both grounds must be tied together as close to the
converter package as possible.
When using a single-ended resolver, the resolver returns (S1 and S4) should
be connected to AGND. The velocity output can then be measured with
respect to AGND. Additionally, AGND provides a reference for internal analog
signals, with no current drop.
Layout Considerations
As in any analog and digital design, special attention should be given to
routing of digital signals near analog lines. This converter has several high
impedance nodes that should be considered (+S, -S, +C, -C, -VSUM and
–VCO). Mount components as close to these pins as possible and avoid
running digital or other signals near these pins.

SYSTEM DESIGN
Transient Protection
The inputs of the RD/RDC Series are susceptible to overvoltage damage
dependent on the magnitude of the current that is injected into the input. The
failure mode is one where the unit latches, and may damage or destroy the
device. If the current is not excessive (<100 mA) the unit may function
normally after power cycling.
The two summing junctions -C and -S are the most susceptible and will latch
at ±6 mA. The inputs RH, RL, +C and +S show no problem up to 25 mA.
Since the amount of current available for a particular voltage spike is

dependent on the application (depending on the input resistor values), the
best way to determine a potential problem is to analyze the amount of current
which will be generated and injected into the input for each application.
Each power supply input to the RD/RDC Series [+5 V (VDD) and -5 V (VSS)]
Power supply has an internal diode clamp. If there is a possibility that the amount of current
protection.
could exceed the limit, a reversed-biased diode should be installed at the
input to VDD and VSS. If using a single-ended input, a 10 kΩ series resistor is
recommended.
When using a thin-film resistor network for the signal input and additional
resistors to scale the reference voltage, the solid-state signal and reference
inputs are true differential inputs with high ac and DC common rejection. Input
impedance is maintained with power off, therefore, most applications will not
require units with isolation transformers. The recurrent ac peak DC + common
mode voltage should be limited.
Systems using 90 V line-to-line inputs may have voltage transients which

Input exceed the maximum specification for the thin-film resistor network (500 V).
Protection. These transients can destroy the input thin-film resistor network. Therefore, 90
V line-to-line solid-state input (DDC-49590) thin-film may be protected by
installing voltage suppressors as shown in Figure 50 and Figure 51. Voltage
transients are likely to occur whenever the synchro or resolver input is
switched on and off. For instance, a 1000 V transient can be generated when
the primary of a control transmitter (CX) or torque transmitter (TX) driving a
synchro or resolver input is opened.
Direct When direct connect is used (No voltage divider used) for either the input or
Connect ref then (1%) 10k ohm series resistors should be used for turn on protection.
Applications Only one resistor per SIN, COS, REF line is required.

SYSTEM DESIGN
FOR 90 V SYNCHRO INPUTS

S3
CR1 S3 SIN
+S RH
THIN-FILM
S1 CR3 RESISTOR
NETWORK -S
RD/RDC
CR4
CR2 S2 COS
S2
+S
RL
S1 -S
CR1, CR2, CR3, and CR4 are 1.5KE170CA or 1.5KE200C-type

bipolar transient voltage suppressors or equivalent.
Figure 50. Voltage Transient Suppressor, 90V Synchro Input
FOR 90 V RESOLVER INPUTS
S1 S1 SIN
S2 S2 +S RH
CR4 CR5 THIN-FILM
90 V L-L RESISTOR -S
RESOLVER NETWORK RD/RDC CR6
INPUT COS
S3 S3
+S
S4 RL
S4 -S
CR4, CR5, and CR6 are 1.5KE170CA or 1.5KE200C-type

bipolar transient voltage suppressors or equivalent.
Figure 51. Voltage Transient Suppressor, 90V Resolver Input.

ENHANCEMENTS
Parameters vs. Performance
This section details the dynamic characteristics of the RD/RDC Series

Converters, and offers suggestions on how to enhance the performance, and
use in various applications.
Bandwidth
Bandwidth vs. Resolution

As shown in Table 22 the maximum closed loop bandwidth (BW) is limited for
all four resolutions, due to the internal tracking limitations of the converter.
Table 22. Maximum Bandwidth per Resolution

Resolution Maximum Closed
(bits) Loop Bandwidth
(Hz)
10 1200
12 1200
14 600
16 300
Bandwidth vs. Carrier Frequency

The converter must maintain a minimum carrier frequency (fc) to bandwidth
(fBW) ratio of: fc ≥3.5 fBW (fc ≥4fBW is recommended). Choose the lowest possible
bandwidth to reject system noise.
When using the converter in a low frequency or DC system, the bandwidth

should be chosen based on the rate of change of the system’s input amplitude
variation. The bandwidth of the converter should be chosen large enough so
to minimize its effect on the overall system dynamics. Also note that if the
bandwidth is too high the system will be more susceptible to noise.
In high frequency applications the maximum bandwidth is limited as in

Table 22.
Bandwidth vs. Input Signal Amplitude

For proper operation, the converter requires an input signal amplitude of 2
Vrms. Any deviation from this amplitude will affect the bandwidth. A decrease
in the voltage will reduce the bandwidth as well as the accuracy sensitivity by

ENHANCEMENTS
increasing the hysteresis in the converter (there will be missing digital output
codes). An increase in amplitude will increase the BW & decrease the amount
of hysteresis thereby causing jitter on the output digital code. For example, a
50% reduction in signal will lead to a 50% reduction in bandwidth. This is due
to the conversion technique used. An internal voltage-controlled oscillator
(VCO) expects to see a certain voltage per LSB. If this voltage is not
maintained, the amount of hysteresis in the converter will change affecting
normal operation.
Bandwidth Optimization
When using a low-cost monolithic converter for position and velocity feedback,
it is important to understand the dynamic response for a changing input.
When considering a bandwidth value to set to your converter, several
parameters have to be taken into consideration. The ability to track step
responses and accelerations will determine what bandwidth to select. The
lower the bandwidth of the resolver-to-digital converter the greater the noise
immunity; high frequency noise will be rejected. For a small step input, the
bandwidth determines the converter settling time. For a large step input the
maximum velocity, slew rate and bandwidth determine the settling time.

ENHANCEMENTS
Acceleration Lag
The RD/RDC Series Converters use a Type II tracking loop. As the
acceleration increases the converter output signal will lag the input signal by a
In a Type II loop,
constant value, the acceleration constant (Ka). Ka is dependent upon the
acceleration lag is
a constant.
bandwidth and maximum tracking rate as shown in the following example.
EXAMPLE: Find the Acceleration Constant (Ka) and the Acceleration Lag for
a system with the following parameters:
Resolution: 16-Bit
Bandwidth: 100 Hz
Reference: 1000 Hz
Maximum Tracking:10 RPS
To solve for Ka:
Equation 1 : BW =
( 2 )(A ) and Equation 2 : Ka = A 2
π
2
(BW )(π) ⎡ (BW )(π ) ⎤
therefore Equation 3 = A = and Equation 4 = Ka = ⎢ ⎥
2 ⎣ 2 ⎦
From Equation 4 :
2
⎡ (BW )(π ) ⎤
Ka = ⎢ ⎥
⎣ 2 ⎦
2
⎡ (100Hz )(π ) ⎤
Ka = ⎢ ⎥
⎣ 2 ⎦
49,298
Ka =
sec 2
Given :
Acceleration Rate
Equation 5 = ∗ Acceleration Lag =
Ka
* Acceleration lag is in degree’s.

ENHANCEMENTS
To solve for Acceleration Rate that results in 1 LSB of error:
From equation 5 :
Acceleration Rate ( for 1 LSB error ,16 − bit mod e) = (Ka )( Lag for 1LSB error )
Acceleration Rate ( for 1 LSB error ,16 − bit mod e) =
(49,284)(0.0055°)
sec 2
270°
Acceleration Rate ( for 1 LSB error ,16 − bit mod e) =
sec 2
Acceleration lag equals the degrees/bit of the resolution used.
Acceleration rate is the max rate at which the converter will track within 1LSB
of error. In the example, an acceleration of 270°/sec2 will cause 1 LSB of lag.
2
Also written as 270°/S .

ENHANCEMENTS
Large Step (179°) Settling Time

Similar to the acceleration constant (Ka), the large step settling time is also
dependent on the bandwidth and maximum tracking rate used.
Example: Solve for the large step (179°) settling time for a 16-bit mode
system with the following parameters:
Bandwidth: 100 Hz
Maximum Tracking Rate: 10 RPS
360° 3600°
Maximum Tracking Rate= x 10 RPS =
1revolution sec
The settling time due to tracking rate:
tTR = step size = 179° = 49ms

maximum tracking rate 3600°/sec
The settling time due to bandwidth limitations must be added.

(see Figure 52 charts to follow.)
1
Time Cons tan t =
A
A=
(BW )(π)
2
A=
(100 Hz )(π)
2
A = 222 Hz
1
= 4.5 msec
A
Large Step Settling Time = tTR + [(time constant)(tc from Table 23)].
Large Step Settling Time=49ms + [(4.5ms)(11)] = 98.5ms
Therefore, the settling time for a large step in a 16-bit application of the
converter with a 100 Hz bandwidth would be 98.5 msec (This is an
approximation).
Table 23 lists the number of counts per rotation and time constants for various
resolutions.

ENHANCEMENTS
Table 23. Counts per Rotation and Time Constraints For Various Resolutions
Resolution Number of Counts per Rotation Number of Time
(bits) (cpr) Constants (tc)
10 1024 7
12 4096 8
14 16384 10
16 65536 11
ANGLE
179˚ 1 rps
12 bit resolution
100 Hz BW
0˚ time (ms)
500 36
12 bits = 8 time constants
time constant = 1/A
179˚
(RPS)˚/s
ANGLE
179˚ 10 rps
12 bit resolution
100 Hz BW
0˚ time (ms)
50 36
12 bits = 8 time constants
time constant = 1/A
179˚
(RPS)˚/s
1
*If you decrease the BW you increase the settling time constant ( ): BW = 2 A
A
π
Figure 52. Examples of Settling Time

ENHANCEMENTS
Maximum Tracking Rate and Internal Sampling Frequency

The maximum tracking rate (4 V maximum for ±5 V power supplies and 3.5 V
maximum for +5 V power supply only applications) is limited by two factors:
velocity saturation and the maximum internal clock rate (nominally 1,333,333
Hz).
The resistor Rv determines the velocity scaling; it is the input resistor to an

inverting integrator with a 50 pF nominal feedback capacitor. When it
integrates to -1.25 V, the converter counts up 1 LSB and when it integrates
+1.25 V, the converter counts down 1 LSB. When a count is taken, a charge
is dumped on the capacitor such that the voltage on it changes 1.25 V in a
direction to bring it to 0 V. The output counts per second per volt input are
therefore:
Let Rs = 30 kΩ, therefore the internal clock rate is 1,333,333 Hz (or counts-
per-second).
Absolute maximum tracking is calculated as follows:

10
For a 10-bit converter there are 2 , or 1024 counts per rotation.
1,333,333 counts per sec ond

=
1024 counts per rotation
= 1302.08 rps
or
1302.08 rps • 1024 counts per rotation
=
4V max imum velocity voltage
333,333 counts
=
sec • volt
Although this is the absolute maximum rate, it is recommended to only run at

90% of this rate. Therefore the minimum Rv will be limited to 55 kΩ.
Note:
If Rs = 20 kΩ then the internal clock is nominally 2,000,000 Hz
If Rs = 15 kΩ then the internal clock is nominally 2,666,666 Hz

ENHANCEMENTS
Changing Resolution On The Fly (RDC-19220/2/4 & RDC-19220/2S

Series)
A technique used to increase the tracking rate while maintaining low speed
accuracy is to switch the resolution of the converter on the fly (change the
resolution as the rotational rate increases).
Many applications for R/D converters require an output with high resolution,
improved angular position accuracy and improved resolution of the calculated
velocity. The RDC-19220/2/4 & S Series, like most R/D converters, is based
on a type II tracking loop. This loop uses a VCO (voltage-controlled oscillator)
to increment the output code. As the resolution of the output is increased, the
number of counts per rotation is increased. The VCO will be required to
operate at a very high counting rate as the input is changing at a fast speed.
As shown in the maximum tracking rate section of this manual, the VCO limits
the maximum tracking rate of the converter.
To alleviate this limitation, the RDC-19220/2/4 & S Series Converter has the
For some
applications,
ability to change the resolution on the fly (sometimes called gearshifting). This
a velocity feature allows the user to increase the resolution when the input is changing
signal at slow speeds, or decrease the resolution when high tracking rates are
transient required. This change is accomplished by simply changing the digital
caused by resolution controls. The change in resolution will not change the bandwidth of
changing the the converter. However, the change in resolution will introduce a transient in
resolution on the output code as well as the velocity. This is due to internal gain changes
the fly may when the resolution is switched. In applications where this transient is a
not be a problem, the RDC-19220/2/4 & S Series Converter will require additional
problem. external components to make the transition from one resolution to the next
resolution smooth (greatly reducing the transient). Refer to Figure 53 (Note
the RD19230 & RD-19240 has this feature built in).
In a typical type II servo loop the velocity voltage is charged onto the
capacitors used to control the bandwidth (CBW and CBW/10). When the
resolution is increased (i.e., 14-bits to 16-bits) the velocity voltage that is
presented to the VCO must be 4 times larger to achieve the same tracking
rate of 214 counts per revolution vs 216 counts per revolution. The time to
change this voltage is controlled by the RC time constants of the bandwidth
components. This is the time for the velocity voltage to re-scale itself. A
tracking error will result due to this re-scaling period.

ENHANCEMENTS
Changing Resolution On The Fly (RD-19230 & RD-19240 Series)

The RD-19230 & RD-19240 series converters have a second set of bandwidth
components that allow a smooth velocity transition, resulting in reduced errors
and minimal settling time after the change.
For applications requiring switch on the fly, the RD-19230 & RD-19240 series
converters are recommended.
Details on setting up switch on the fly operation are available in the “Basics”
section of this manual, the RD-19230FX & RD-19240FX data sheets and the
application note AN/MFT-3.
Error Minimizing for the RDC-19220/2/4 & S Series during Resolution Switching
By using the external circuitry shown in Figure 53, the error will be reduced.
While one set of bandwidth components are being used in the loop, a second
set of components are being charged to 4 times the velocity voltage and a
third set to 1/4 of the velocity voltage. When the resolution is either increased
or decreased one step (i.e., 14- to 16-bit or 14- to 12-bit) the precharged
bandwidth components are switched into the loop. Since the capacitors are
already charged to the correct velocity voltage this circuit greatly reduces the
error caused by changing resolution.
The circuit shown in Figure 53 allows switching from any of the four possible
resolutions, up or down one resolution step, without generating a significant
error in the output, provided the maximum tracking speed is not exceeded
when switched to a resolution (i.e., 16 bits when input is at 20 RPS). If the
resolution needs to be changed a second step in the same direction (i.e., 12-
bit to 14-bit to 16-bit) sufficient time must be allowed between steps to
precharge the proper bandwidth components, or an error may be generated.
If less resolution is used in the application some components can be

eliminated. Resolution changes can be controlled by using either a micro-
controller to calculate the velocity or comparators on the velocity voltage.
When the velocity reaches the maximum, the resolution can be decreased
one step. When the velocity falls below 1/4 of maximum the resolution can be
increased one step. If the velocity voltage is used to control the resolution
switching, care must be used in selecting the limits at which the switching
occurs to prevent chattering between the two resolutions since the velocity
voltage rescales when the resolution is changed.
DDC’s RD-19230 and RD-19240 converters provide another way to solve this
problem using a on chip switch for a second set of bandwidth components
detailed in the Optional Bandwidth Components section on page Error!
Bookmark not defined. of this manual.

ENHANCEMENTS
R4
30K
R3
RC4741 - 13
U3b 12
14 11 + 10K
-5v
+5v
2 R1
1 - 4
U3a 3 10K
RC4741 +
C1 R2
+5v 100pF 30K
U2
12 VDD 16 GND
14 X0
15 X1 X 13
11 X2
X3
1 Cbw3 Rb3
Y0
5 Y1
Resolution 2 Y 3
Controls 4 Y2
Y3 VEE 7
10 INH 6
-5v
A Cbw3/10
B 9 A
B VSS 8
4052
U1 +5v
12 X0 VDD 16 Cbw2 Rb2
14 X1
15 13
X2 X
11 X3 Cbw2/10
1 Cbw1 Rb1
Y0
5 Y1
2 Y2 Y 3
4 Y3 VEE 7 -5v
10 A INH 6 Cbw1/10
9 B VSS 8
4052
VEL
RS Rv
A B -VSUM VEL -VCO
CT
RESOLVER R1 16 BIT
GAIN DEMOD VCO UP/DOWN
INPUT COUNTER
+1.25V
-
THRESHOLD
DIGITAL
H=1
OUTPUT
RDC-19220/2 & RDC-19220/2S GND A GND
Cbw1 = Cbw2 = Cbw3 = Cbw

Rb1 = Rb2 = Rb3 = Rb
Cbw1/10 = Cbw2/10 = Cbw3/10 = Cbw/10
Figure 53. External Circuitry for Resolution Switching

ENHANCEMENTS
Two-Speed Resolver Applications

To achieve higher resolutions and accuracies, some systems utilize two-
speed resolvers. A two-speed resolver can be a single resolver wound as a
two speed with a coarse output winding (1x) and a fine output winding (nx), or
For more two resolvers with the shafts mechanically geared together to create a coarse
information refer resolver and a fine resolver. In either configuration, conversion of the output
to DDC’s
from a two-speed resolver will require two R to D Series Converters; one
Synchro/Resolver
converter for the coarse measurement and one for the fine measurement (see
Conversion
Handbook.
Figure 54). The converters will output the absolute position of the coarse
winding or resolver and the fine winding or resolver. The output data can be
interpreted by a user-written software program or through hardware using 4-
bit binary adders with carry (5483) as detailed in DDC’s Synchro/Resolver
Conversion Handbook.
Figure 54. Two-Speed Resolvers
The coarse (1x) portion of a two-speed system has a one-to-one relationship;

for one rotation of the system from 0° to 359°, the coarse portion will also
rotate from 0° to 359°. The fine (nx) portion of a two-speed system has a one-
to-n relationship (where n = the number of rotations of the fine to equal one
rotation of the system). Therefore, for one rotation of the system from 0° to
359°, the fine portion will rotate n times from 0° to 359°. See Figure 55.
Figure 55. Two-Speed Example using 1:4 Ratio

ENHANCEMENTS
Two-Speed Resolution
LogX
Resolution derived from 2-speed = ( − 1 ) + (Converter Resolution)
Log2
X = The ratio of the fine shaft compared to the binary look-up chart (Table 24).
For the value of X, use the next highest number listed that is greater than the
fine shaft ratio.
Table 24. Binary Look-up Chart

4 8 16 32 64 128 256 512
(Note : For higher values of X, simply continue to double last listed value)
Example:
For a ratio of 1:30 with a 16-bit converter on the fine channel.

X = 32 therefore:
Log32
( − 1 ) + (16) = 20-bit resolution is achieved.
Log2
For a ratio of 1:14 with a 14-bit converter on the fine channel.

X = 16 therefore:
Log16
( − 1 ) + (14) = 17-bit resolution is achieved.
Log2
Two Speed Accuracy

A multi-speed synchro system consists of two or more synchros or resolvers
geared together, usually with a gear ratio of some whole number. The most
common are two-speed systems with ratios of 1:8, 1:16, 1:32, 1:36 but other
ratios can also be found. To understand how these systems achieve high
accuracy let us examine a typical two-speed system.
In the single-speed case (CT = the transducer used) the system will,
essentially, have an accuracy dependent upon the accuracy of the CT (we will
assume a perfect transducer) and the positional resolution of the servo loop.
Assume we can position the CT with a certain accuracy, say within ± 0.1°. If
we now gear this CT to another with a gear ratio of 1:n (called a “coarse” CT)
where the CT we are positioning rotates n turns for each single turn of the
other, then 0.1° of rotation of the fast CT (called the “fine” CT) will turn the

ENHANCEMENTS
slow CT (called the “coarse” CT) 0.1 ÷ n, so that an inaccuracy in the fine CT
position is effectively divided by the gear ratio (often called the speed ratio).
For greater detail on 2 speed theory review the synchro resolver handbook
which can be downloaded from www.ddc-web.com.
DDC provides 2 speed support in the PCI card family. The SB-36200, SB-
36210, SB-36220 cards contain 2 speed functions.
User-Written Software
The following software example is a concept of one of many possible software
algorithms:
To develop software to interpret two-speed outputs, the coarse angle is used

as the starting point in the calculation. This angle, when multiplied by the
speed ratio, gives a reflected angle. The reflected angle is the angular
distance of rotation for the coarse angle (as measured by the coarse
converter), with respect to the fine angle (as measured by the fine converter).
This is a The number of rotations through 360.0° can be considered the number of
concept of turns, while the remaining rotation value calculated from 0.0° of the last turn is
one of many
the Calculated Fine Angle.
possible
software
algorithms.
The Calculated Fine Angle can be used to determine if the Actual Fine Angle
is acceptable. Initially both gears should align so an angle of 0.0° on the
coarse equals 0.0° on the fine. If the difference between the Calculated Fine
Angle and the Actual Fine Angle is in the range from 135.0° to 225.0°, the
possibility of a gear misalignment is indicated as an error condition.
If the difference between the calculated and actual fine angles is greater than
180° an additional turn of the coarse angle is added to the resultant angle,
since the Actual Fine Angle indicated an additional coarse turn is necessary.
The result is calculated by taking the number of turns calculated from the
Coarse Angle, multiplying by 360.0° to get a rough calculated rotation, then
adding the Actual Fine Angle and any necessary correction value to get an
exact calculated rotation. This calculated rotation, when divided by the speed
ratio, gives the final two-speed output. An example program written to
interpret output data is illustrated below:
IN->COARSE_ANGLE
IN->FINE_ANGLE
IN->SPEED
CORRECTION =0
ERROR_FLAG = CLEAR
REFLECTED_ANGLE = COARSE_ANGLE * SPEED RATIO

ENHANCEMENTS
TURNS = FLOOR ( REFLECTED_ANGLE / 360.0 )

CALCULATED_FINE = REFLECTED_ANGLE - ( TURNS * 360.0 )
ERROR = CALCULATED_FINE - FINE_ANGLE
IF (ERROR>0)
IF (ERROR>135) AND (ERROR<225) ERROR_FLAG = TWOSPEED_ERROR
IF (ERROR>180) CORRECTION = 360.0
ELSE
IF (ERROR<-135) AND (ERROR>-225) ERROR_FLAG = TWOSPEED_ERROR
IF (ERROR<-180) CORRECTION = 360.0
TWOSPEED_ANGLE = (TURNS * 360.0 + FINE_ANGLE + CORRECTION)/SPEED

OUT->TWOSPEED_ANGLE

ENHANCEMENTS
Synchro/Resolver-to-DC Conversion
A technique used to convert Synchro/Resolver information to a DC voltage
that represents an angle is shown in Figure 56. This technique can be
accomplished by connecting the RD/RDC or similar series product as
discussed in earlier sections and interfacing the digital output to a digital-to-
analog converter (DAC). The positive full-scale voltage will represent +180°,
and the negative full-scale voltage will represent -180°. The use of an
RD/RDC has the advantage of eliminating the effects of quadrature signals
and decreasing the noise sensitivity of the Synchro/Resolver-to-DC
conversion.
+5 V +15 V
0.1 µF 0.1 µF
SIN RD/RDC +VCC

-S
+S BIT 1 (MSB) BIT 1 (MSB)
COS
-C VOUT VOUT
+C
RH RH
BIT 16 (LSB) BIT 16 (LSB)
RL RL
A +5 V
B
-VSUM
CBW CBW
ENM BURR BROWN
10 RBW DAC 703
ENL
VEL
RV
-VCO
GND AGND -VCC VDD COMMON
0.1 µF
-15 V +5 V
-5 V
NOTES: 1. CONCEPT DRAWING. SEE MANUFACTURERS' DATA SHEETS FOR COMPLETE INFORMATION.
2. RH AND RL ARE SWAPPED TO PROVIDE 2'S COMPLEMENT OPERATION. NORMAL WIRING OF
RH AND RL PROVIDES OFFSET BINARY OPERATION.
Figure 56. Synchro/Resolver-to-DC Conversion

ENHANCEMENTS
SEU/SEL Solutions
Preface
The RD/RDC series are versatile 16-bit state-of-the-art monolithic synchro,
resolver, or LVDT to digital converters. These single chip monolithics are
CMOS components which need protection from the effects of SEU/SEL or
latchup. The following summary outlines the most common approach used to
protect the converters.
Suggested Design Approach

A 10 ohm resistor should be placed in series with the +/-5 volt power supplies
(or power supply, depending on configuration). Along with the resistor(s), a
2.2µf capacitor should be used for de-coupling of the power supplies (or
power supply).
During an SEU/SEL (latchup condition) the supply current will be limited to

500 mA by the 10 ohm resistor, which protects the monolithic from surge
currents. The resistors power rating is critical. Depending on the impedance
level of the chip during the latched condition, there is a potential for the
resistor to over dissipate. There is no data for the impedance level this chip
presents due to a latchup condition caused by SEU/SEL.
It is therefore suggested that for applications requiring SEU/SEL tolerance,

the power supplies be monitored and either shut down or limited during
latchup condition so not to over dissipate the resistor and the converter. This
can be accommodated by implementing a hardware or software approach of
monitoring the DC power supply (or power supplies) to the monolithic. Since
the monolithic will typically draw 22 to 44 mA max (depending on the
configuration), it is recommended to recycle the power to the hybrid if the
current approaches approximately <100 ma. SEU/SEL testing on this series
has shown that as long as the power is limited, the monolithic will recover
when the power is recycled.
Additional information on this topic is detailed in DDC’s application note

Introduction to Effects of Radiation Applied to RDC-19220 (AN/MFT-4), which
is available at www.ddc-web.com. Information on power reset is also available
by contacting DDC’s applications group at 631-567-5600 X7771 and
requesting document# FAQ-19222-003.

TESTING AND TROUBLESHOOTING
Testing the RD/RDC Series Converters in a System

Once the converter has been designed on a board, the system will require
testing. For applications that use synchro or resolver inputs, a
synchro/resolver simulator can be used to test the system. Please contact
DDC for additional information on available synchro/resolver test simulators.
For a quick, but limited functional test, the reference excitation or a single
oscillator source can be used to test the converter in the system. This test is
achieved by shorting various combinations of the input signals and connecting
these to the reference inputs. The amplitude of the reference or the oscillator
source should be a factor of the intended line-to-line input, as shown in the
reference multiplier column of Table 25. For example, a resolver-based
system with an intended 11.8 VL-L input should have the oscillator set at either
11.8 Vrms or 8.26 Vrms, depending on the input signal connection
combination. Connect shorted inputs to reference inputs as specified in Table
25.
Table 25. Simulating Angles Using a Single Reference Source

System Reference Input Signal Connections Digital
Input Type multiplier Angle
(Vrms) Output
S1 S2 S3 S4
Synchro x 1.0 RL RH RL na 0.000°
x 0.50 RL RH RH na 60.000°
x 0.50 RL RL RH na 120.000°
x 1.0 RH RL RH na 180.000°
x 0.50 RH RL RL na 240.000°
x 0.50 RH RH RL na 300.000°
*Resolver x 1.0 RL RH RL RL 0.000°
Differential x 0.707 RL RH RH RL 45.000°
Mode Only x 1.0 RL RL RH RL 90.000°
x 0.707 RL RL RH RH 135.000°
x 1.0 RL RL RL RH 180.000°
x 0.707 RH RL RL RH 225.000°
x 1.0 RH RL RL RL 270.000°
x 0.707 RH RH RL RL 315.000°
na = not applicable
*Single ended mode can only be tested in the 1st quadrant (0° to 90°) where SIN, COS, and REF are all in phase.

Boards that are designed with an LVDT input can also use a
Synchro/Resolver simulator for testing purposes. To test an LVDT application
using a Synchro/Resolver simulator, the angular bit weights of the R/D
converter, in linear mode, are modified as follows (also see Table 26):
Bit 3: 0.5/0.5 = 1 Arc Tan (1)= 45°
Bit 4: 0.25/0.75 = 0.333 Arc Tan (0.333) = 18.435°
Bit 5: 0.125/0.875 = 0.143 Arc Tan (0.143) = 8.130°
Bit 6: 0.0625/0.9375 = 0.066 Arc Tan (0.066) = 3.814°
Table 26. Output Angular Bit Weights for LVDT Inputs

Bit Angle
3 45°
4 18.435°
5 8.130°
6 3.814°
7 1.848°
8 0.911°
9 0.451°
10 0.225°
11 0.122°
12 0.056°
13 0.028°
14 0.014°
15 0.007°
16 0.00035°
Note: For LVDT Simulation Guidelines see the DSC-11524 Converter Data Sheet.

Troubleshooting
The RD/RDC Series converters present a challenge for troubleshooters when
things go wrong in a system. This section includes a Checklist and a detailed
symptoms and solutions table.
Troubleshooting Checklist
The following checklist offers a starting point for the troubleshooter to follow.
Perform these tests as the first step in problem solving.
1. Check sinusoidal frequency and amplitude of +REF measured with respect

to (w.r.t.) -REF.
2. Check the converter COS pin. It should be a sampled sine wave as shown
in Figure 57 (w.r.t. AGND) for converters without a synthesized reference
such as the RDC-19220/2/4. For converters with a synthesized reference,
such as the RDC-19220/2S, RD-19230 and RD-19240, the sine wave will not
be sampled at those pins.
3. Check the converter SIN pin. It should be a sampled sine wave as shown in
Figure 57 (w.r.t. AGND) for converters without a synthesized reference such
as the RDC-19220/2/4. For converters with a synthesized reference, such as
the RDC-19220/2S, RD-19230 and RD-19240 the sine wave will not be
sampled at those pins.
4. Check the velocity signal (VEL) pin of the converter. It should be a DC

average signal at ground when the system is not rotating. Normally, there will
be noise on this line with a dominant carrier frequency ripple (w.r.t. AGND).
6. Ensure that there is no digital routing near the ±S, ±C, -VCO and -VSUM
pins. These are amplifier summing junction nodes (high impedance) and are
very sensitive to coupling.
7. Check the -5 V signal on pin 17 (if using the devices’ internal -5 volt
feature). It should measure between -4 VDC and -5 VDC.
8. Check the built-in test (BIT) pin. It should be high during normal operation.
9. Check the +5 VDC and –5 VDC power supply lines for excessive noise or
ripple.
10. Verify that AGND & GND are tied together close to the converter chip.
11. Verify that no DC-offsets are present at the converter SIN and COS
inputs.

12. Verify that the bandwidth components are correctly calculated, and
properly installed.
Figure 57. Sampled Sinusoidal Wave
Troubleshooting Symptoms and Solutions

After the checklist has been verified, refer to the troubleshooting list below. If,
after considering the following list, you still require technical support contact
your local applications engineer or the factory at (631) 567-5600 and ask to
speak to a Synchro/Resolver Conversion Applications Engineer.
Further troubleshooting guidelines are available, ask for the following FAQ’s:
FAQ – gcnvtr-016
FAQ – gcnvtr-017

TROUBLESHOOTING SYMPTOMS AND SOLUTIONS

Symptoms & descriptions Solutions
Spin around:
• Digital output continuously changing while the 1. Verify that the mandatory external components are
input is not changing in position. connected properly (see Mandatory External
• BIT pin may be logic 0, indicating fault condition. Components section).
2. Verify that the input signals at the maximum of the
• The VEL output may be at, or ramping to, the
SIN and COS pins are sampled 2 Vrms waveforms
±maximum amplitude.
(see Figure 57)
3. Verify that the signal amplitude between the +REF
and -REF pins measures between 2 and 4 Vpeak.
4. Verify that the power supply (or supplies) is
properly connected and of the correct voltage (see
Power Supplies section).
5. Review the design parameters. Is the bandwidth to
tracking rate ratio violated? (see Mandatory
External Components section). Verify that the
“tracking to BW relationship” ( Table 11 ) (has not
been violated.
BIT (Built-in Test) fault:

1. Check that there are no loss-of-signals (LOS) by
• A logic 0 is measured on BIT pin, indicating a verifying that the +S and +C input signals are
fault indication. connected. If both input signals are simultaneously
less than 0.8 volts the BIT flag will be set to
indicate a fault condition. During normal operation,
angle rotation causes each input line to fall below
0.8 volts at certain intervals in time (i.e., the sine
input at 0° = 0 volts), therefore the BIT flag will set
only if both inputs are below 0.8 volts at the same
time.
2. Check input and reference signals for phase shift
error. The BIT flag will be set if the phase shift
between the input and reference signals is too
large. This condition will also force a change into
the system to correct the error, so large changes
could occur in the digital output while the system
tries to find the correct answer.
3. Check for excessive error in the digital output. If the
digital output has more than 100 LSBs of error from
the input angle the BIT flag will be set.
Excessive error may occur:
♦ normally during large step changes of the input
♦ during high accelerations that cause an
acceleration lag
♦ from input signal distortion
♦ from an excessive phase shift between the


BIT (Built-in Test) fault (cont): reference and the input signals (see Reference
Input section)
4. For RDC-1922XS and RD-19230, RD-19240
versions verify there is no loss of the reference
signal (LOR) ref input less than 500mv.
5. For intermittent BIT faults verify correct input
voltage configuration. An indication of this problem
would be if the BIT faults occur when the SIN and
COS input absolute values are equal. For example,
at 45° the SIN and COS inputs should both be
1.41Vrms ± 10% measured at the converter pins.
Jitter:
• Least significant bits (LSBs) continuously 1. Verify that the correct input voltages at the SIN and
changing, or jittering. COS pins are sampled 2 Vrms waveform.
• BIT logic level is high, indicating normal (See Figure 57 ). SIN is max voltage at 90°, COS is
operation. max voltage at 0°.
2. Verify that there is no excessive phase shifting
between the reference and the input signals, or the
input signals from each other (see Reference Input
section).
3. Ensure that there are no traces near the mandatory
external component connections (specifically +S, -S,
+C, -C, -Vsum and -VCO). This may cause coupling
into the converter.
4. Verify that the carrier frequency is at least 3.5 times
the bandwidth (see Mandatory External Components
section).
5. Check for excessive ripple or noise on the power
supplies.
6. Tie the GND and AGND pins together close to the
converter (see Grounding Tips section).
7. If using a differential input, check resolver for
undesirable coupling of the sampled sine wave
signal. To verify this, ground +S and +C. One
suggestion to alleviate this problem is to use a
single-ended input to buffer the input.
Digital output not responding:
Note: All digital inputs have an internal pull up.
• Digital output does not respond to changes in
input from resolver.
1. Ensure that the EM and EL pins are set to logic 0
or tied to ground (see Timing section).
2. Ensure that INH is allowed to pull up to logic 1, or
is set for a logic 1 after the first position is read.
Additionally, set INH to a logic 0 for a minimum of
300 ns before taking the next reading (see Timing
section).


Digital output not responding (cont): 3. Ensure that VDD is +5 V ±10% and VSS is -4 V
minimum (see Power Supplies section).
4. Verify that the mandatory external components are
connected properly (see Mandatory External
Components section).
Large error in digital output: 1. Verify that the synchro or resolver lines are
connected correctly.
• Error larger than the rated accuracy of the If the synchro is ARINC 407 compliant, X, Y, and Z
converter, and larger than 1° (or > 60 arc should be interpreted as follows:
minutes). X = S1, Y = S3, Z = S2.
(The Z may be grounded).
2. Verify that the reference input polarities are correct.
The high side of the reference should be connected
to RH and the low side should be connected to RL.
If the reference inputs are swapped, the output
error would be approximately 180° (or 10,800 arc
minutes).
3. Verify that the input resistors are correctly scaled to
provide a 2 Vrms signal to the converter input.
4. Ensure that the -5 V supply is between -4 V and
-5 V.
5. Verify that no external circuits are added to the
velocity output of the converter. See the “basic”
section of the manual on velocity.
Inaccuracies: 1. Check for excessive phase shift error between the

reference and signal inputs (see Reference Input
• Error larger than the rated accuracy of the section).
converter, but less than 1° (or < 60 arc minutes). 2. Verify that the input scaling resistors are of
acceptable tolerance. Suitable thin film resistor
networks matched to 0.02% tolerance are available
from DDC. Contact factory for information (see
Resistor Tolerance section).
3. Verify that input signals at the maximum of the SIN
and COS pins are sampled 2 Vrms waveforms (see
Figure 57).
4. Verify that no external circuits have been added to
the velocity output of the converter. See the “Basic”
section of the manual on velocity.
Velocity Ripple:
1. Verify that there is no DC offset on any of the input
• Excessive Ripple on velocity output signals. An offset of as little as 1 - 2mv can cause
the reference frequency to pass onto the VEL
output.
2. Verify that the bandwidth is not set too high.
3. Verify that there is no excessive noise on input
lines.


Velocity Ripple (cont): 4. If using single ended inputs, try using differential
mode inputs for better noise rejection.
5. Use shielded twisted pairs, routed away from higher
voltage current lines.
6. Check for a phase shift between SIN and COS with
respect to each other at the R/D converter.
Quadrature on the input signals can cause ripple,
(see Quadrature Voltage and Phase Shift section).
If a phase shift is present at a static angle of 45°
this could be a function of the resolver, coupling or
routing and must be corrected.
7. Check for excessive phase shift between input
signals and reference signal. Non-synthesized
reference parts should have less than a 6° phase
shift. Synthesized reference parts should have less
than a 45° phase shift.
8. Check the +5, -5 volt power supply lines for
excessive noise or ripple.
9. More than 1 RD on a common bus ? This can
cause erratic issues or noise on the velocity output.
RD converters on a common bus can start to talk to
each other if the clocks are at the same freq and the
charge pump mode is used to generate the –5V for
the RD. Offset the Rclock resistors on the RD
converters by 3K.

Table 27 and Table 28 list the output of the RD/RDC series converters when
the Synchro and Resolver input signal lines are swapped.
Table 27. Synchro Input Swapping

Output Angle (degrees)
Input Angle S2-S3 S1-S3 S1-S2
(degrees) swapped swapped swapped
0 120 0 240
45 75 315 195
90 30 270 150
135 345 225 105
180 300 180 60
225 255 135 15
270 210 90 330
315 165 45 285
Table 28. Resolver Input Swapping

Output Angle (degrees)
Input Angle S1-S3 S2-S4
(degrees) swapped swapped
0 0 180
45 315 135
90 270 90
135 225 45
180 180 0
225 135 315
260 100 280
270 90 270
315 45 225
359 1 181
For further troubleshooting hints contact DDC Applications and request FAQ-gcnvtr-016 and FAQ-gcnvtr-
017.

SYNCHRO/RESOLVER CONVERSION THEORY
The information in this section is provided for the RD/RDC Series user who
wants to know more about how the converter translates analog
Synchro/Resolver signals to a digital word. For general theory on synchro
transducers, resolver transducers, LVDTs, or Digital-to-Synchro/Resolver
converters refer to the DDC Synchro/Resolver Conversion Handbook. This
handbook is available on the DDC Web site.
Introduction
The requirement for velocity and position feedback play an important role in
today’s motion control systems. With the development of low-cost monolithic,
resolver-to-digital converters, a resolver-based system provides design
engineers with the building blocks to handle a wide variety of applications. A
resolver’s small size, rugged design and the ability to provide a very high
degree of angular accuracy under severe conditions, make it an ideal
transducer for absolute position sensing. These devices are also well suited
for use in extremely hostile environments such as continuous mechanical
shock and vibration, humidity oil mist, coolants and solvents. Absolute position
sensing vs. incremental position sensing is a necessity when working in an
environment where there is the possibility of power loss. Whenever power is
supplied to an absolute system, it is capable of reading the current position
immediately, eliminating the need for a go home or reference starting point.
Figure 58 illustrates an example of when DDC components would be used in
a two-axis antenna control application.
Figure 58. DDC Components’ Utilization

in a Two-Axis Antenna Application

Applications
Specific applications require unique profiles to control the speed and acceleration of
the motor to perform the task at hand. By reducing the accelerations and
decelerations which occur during each operation it is possible to lower the cost and
use more efficient motors. Industrial applications include the following:
• Ballscrew • Motor • Robotics

positioning commutation positioning
• Machine vision • X-Y tables • Component

systems insertion
• Remote video • Web guides • Pick and place

controls machines
• Wafer • Electronic • Throttle

Fabrication Steering Control
• Stability
Control

Resolver-to-Digital Converters
For proper operation the RD/RDC Series Resolver-to-Digital converter
requires only five external passive components. These components are used
to set the bandwidth, which controls the speed at which the converter will
react to changes in the inputs, and the maximum tracking rate. Depending on
converter selection resolution can also be programmed to provide 10-, 12-,
14- or 16-bits of parallel data.
Closed Loop Feedback

Absolute Position
A typical closed loop servo model is shown in Figure 59.
An important feature of the resolver-to-digital converter is repeatability. A

repeatability specification of ±1 LSB (least significant bit) in 16-bit mode
provides an accurate measurement to determine position from point to point.
For example, moving from point A to point B, and back to point A, the 16-bit
mode converter will be accurate to within 20 arc seconds of the original
position. The error curve of a resolver-to-digital converter is repeatable within
±1 LSB. The combination of high precision resolvers (±20 arc seconds) and
the resolver-to-digital converter provides accurate, absolute position
information for precision feedback for motion control.
Note: Refer to Figure 60 for the following discussion:
Before the resolver-to-digital conversion, the resolver information is presented

to a solid state resolver conditioner which reduces the signal amplitude to 2
Vrms sine and cosine. The amplitude of one being proportional to the sine of θ
( the angle to be digitized), and the amplitude of the other being proportional
to the cosine of θ. (The amplitudes referred to are, of course, the carrier
amplitudes at the reference frequency, i.e., the cosine wave is actually cos θ
cosωt. The carrier term, cosωt, will be ignored in this discussion, because it
will be removed in the demodulator, and at any rate contains no data). A
quadrant selector circuit in the control transformer enables selection of the
quadrant in which θ lies, and automatically sets the polarities of the sine θ and
cos θ appropriately for computational significance. The sin θ, cos θ outputs of
the quadrant selector are then fed to the sine and cosine multipliers, also
contained in the control transformer. These multipliers are digitally
programmed resistive networks. The transfer function of each of these
networks is determined by a digital input (which switches in proportioned
resistors), so that the instantaneous value of the output is the product of the
instantaneous value of the analog input and the sine (or cosine) of the digitally
encoded angle. If the instantaneous value of the analog input of the sine

multiplier is cos θ, and the digitally encoded “word” presented to the sine
multiplier is φ, then the output code is cos θ sin φ.
Thus the two outputs of the multipliers are:
from the sine multiplier, cos θ sin φ
from the cosine multiplier, sin θ cos φ
These outputs are fed to an operational subtractor at the differencing junction

so that the input fed to the demodulator is:
sin θ cos φ - cos θ sin φ = sin (θ-φ)
The right-hand side of this trigonometric identity indicates that the

differencing-junction output represents a carrier frequency sine wave with an
amplitude proportional to the sine of the difference between θ (the angle to be
digitized) and φ ( the angle stored in digital form in the up-down counter). This
point is the AC error signal referred to as e. The demodulator is also
presented with the reference voltage, which has been isolated from the
ERROR ERROR
POSITION
COMMAND
CONTROLLER AMPLIFIER MOTOR
PLC
POSITION VELOCITY TORQUE

FEEDBACK FEEDBACK FEEDBACK
RESOLVER
RESOLVER-TO-DIGITAL
CONVERTER
POSITION SENSOR
CLOSED LOOP SERVO MODEL
Figure 59. Closed Loop Servo Model
reference source, and appropriately scaled by the reference conditioner. The

output of the demodulator is then, an analog DC level proportional to: sin
(θ-φ). In other words, proportional to the sine of the “error“ between the actual
angular position of the resolver and the digitally encoded angle, φ, which is the
output of the counter. This point, DC error (D), is sometimes brought out as
(D) a test point, while an addition of a threshold detector will give a Built-in test

( BIT ) flag. When the AC error signal exceeds the equivalent ac value of 100
LSBs the BIT flag will indicate a tracking error. This angular error signal is
then fed into the error processor and VCO. This circuit consists essentially of
an analog integrator whose output (the time integral to the error) controls the
frequency of a voltage-controlled oscillator (VCO). The VCO produces clock
pulses that are counted by the up-down counter. The “sense“ of the error (φ
too high or φ too low) is determined by the polarity of (φ), and is used to
generate a control counter signal (U), which determines whether the counter
increments upward or downward. Finally, note that the up-down counter, like
any counter, is functionally an incremental integrator, therefore the tracking
converter constitutes in itself a closed-loop servomechanism (continuously
attempting to null the error to zero) with two integrators in series.
+REF -REF BIT
SIN
-S C BW
S1 - C BW
S2 +S 10 RB
SIGNAL + D R1
S3 CONDITIONER COS CONTROL e
TRANSFORMER GAIN DEMODULATOR VEL
S4 -C
-
+C INTEGRATOR
+ RV
HYSTERESIS
A B
16 BIT VCO
-5 V
UP/DOWN & RS
INVERTER
COUNTER TIMING
E RC
A GND
+5 V DATA
GND LATCH
-5 V
INH EM BIT 1 EL A B CB
THRU
BIT 16
Figure 60. Resolver-to-Digital Conversion Block Diagram
This is called a “Type II“ servo loop, which has decided advantages over Type
1 or Type 0 loops. In order to appreciate the value of a Type II servo behavior
of this tracking converter, consider first that the shaft is not moving. Ignoring
inaccuracies, drifts, and the inevitable quantizing error, the error should be
zero (θ = φ), and the digital output represents the true shaft angle of the
resolver. Now, start the resolver shaft moving, and allow it to accelerate
uniformly, from dθ/dt = 0 to dθ/dt =V. During the acceleration, an error will
develop, because the converter cannot instantaneously respond to the
change of angular velocity. However, since the VCO is controlled by an
integrator, the output of which is the integral of the error, the greater the lag
(between θ and φ), the faster the counter will be called upon to catch up.
When the velocity becomes constant at V, the VCO will have settled to a rate
of counting that exactly corresponds to the rate of change in θ per unit time
and instantaneously θ = φ. Therefore, dφ/dt will always track dθ/dt without a
velocity or position error. The only error will be momentary (transient) error,
during acceleration or deceleration. Furthermore, the information produced by
the tracking converter is always “fresh“ being continually updated, and always
available at the output of the counter. Since dθ/dt tracks the input velocity it
can be brought out as velocity, a DC voltage proportional to the rate of

rotation, which is of sufficient linearity in modern converters to eliminate the

need for a tachometer in many systems.
Velocity (Speed)
Motor speed is monitored by using the velocity output signal generated by the
resolver-to-digital converter. This signal is a DC voltage proportional to the
speed, positive for increasing angles and negative for decreasing angles, with
a linearity specification of .25% typical and a reversal error of .75% typical.
The error processing is performed using the industry standard technique for
type II tracking, resolver-to-digital converter (see Figure 60).
The DC error is integrated yielding a velocity voltage which in turn drives a

voltage-controlled oscillator (VCO). This VCO is an incremental integrator
(constant voltage input to position rate output) which together with the velocity
integrator forms a type II critically damped, servo feedback loop. This
information allows the motor to maintain constant speeds under varying loads
when it is interfaced with a programmable logic controller (PLC). The PLC
based architecture is used for I/O intensive control applications.

QUALITY REPORTS-MTBF REPORTS
MTBF reports for the RD/RDC Series converters are available on request.

MECHANICAL SPECIFICATIONS
PIN NUMBERS
FOR REF ONLY
0.125 ±0.020
(3.18 ±0.508)
0.590 ±0.010 0.115 ±0.010
(14.99 ±0.25) (2.92 ±0.25) 0.050 ±0.010
(1.27 ±0.25)
1 40
0.100 ±0.010 TYP

(2.54 ±0.25)
0.018 ±0.006 TYP

2.000 ±0.020 (0.46 ±0.15)
(50.8 ±0.51)
0.050 ±0.020 TYP

(1.27 ±0.51)
20 21
0.012 ±0.004 TYP

(0.31 ±0.10)
DIMENSIONS SHOWN ARE IN INCHES (MM).

+0.050
0.095 ±0.010 0.600 - 0.020
(2.41 ±0.25) +1.27
(15.25 - 0.51 )
Figure 61. RDC-19220 DDIP Ceramic Package

Figure 62. RDC-19222 J-LEAD Plastic Package
0.075 ±0.010
(1.91 ±0.25) 0.040 x 45˚
CHAMFER
0.500 ±0.010 (1.02)
0.020 x 45˚ (12.70 ±0.25) (3 PLACES)
0.143 ±0.010
(0.51) (3.63)
CHAMFER 0.050 TYP
(ORIENTATION (1.27) 0.095 ±0.007
MARK) (2.41 ±0.18)
6 1 40
7 39
0.630 ±0.020 TYP

(16.00 ±0.51)
0.500 ±0.010
(12.70 ±0.25)
0.017 TYP
(0.43)
17 29
18 28 PIN NUMBERS
FOR REF ONLY
0.075 ±0.010
(1.91 ±0.25) 0.650 SQ ±0.010
(16.51 ±0.25)
0.690 ±0.010 TYP DIMENSIONS SHOWN ARE IN INCHES (MM)

(17.53 ±0.25)
Figure 63. RDC-19222 J-LEAD Ceramic Package

Figure 64. RDC-19222S (44 Pin Plastic J-Lead) Mechanical Outline
0.078+0.004
-0.002
(2.00+0.10
-0.05 )
32 17
0.096MAX
(2.45MAX)
33 16
0.0098MIN,0.0197MAX
(0.25MIN,0.50MAX)
0.0197
0.520±0.010 (0.50)
(13.2±0.25)
RD-19230FX
-XXX 0.394±0.004
(10.00±0.10)
Date Code
48 pin1
0.0098MIN,0.0197MAX
0.096MAX (0.25MIN,0.50MAX)
49 64
(2.45MAX)
*
0.394±0.004
(10.00±0.10) 0.007MAX
(0.17MAX) 0.008
(0.22)
0.520±0.010 0.035+0.006
(13.2±0.25) -0.004
( 0.88+0.15
-0.10 )
Dimensions shown are in inches (millimeters)

Mechanical design done to millimeters
Dimensions shown are to dotted lines
Figure 65. RD-19230 Mechanical Outline

Figure 66. RDC-19224 Mechanical Outline

Figure 67. RD-19240LS Mechanical Outline
12 Eq Sp @
0.026 = 0.312
(0.65 = 7.800)
0.026 0.079 +0.004

-0.002
(0.65) ( 2.00 +0.10 )
-0.05
0.035 +0.006
-0.004
0.520 ±0.010 (0.89 +0.15

-0.10
)
(13.2 ±0.25 )
RD-19240FS
-XXX 0.394±0.004
(10.00 ±0.10)
Date Code
pin1
0.394 ±0.004 0.007

( 10.00 ±0.10) (0.17) 0.012
(0.30)
0.520 ±0.010 0.035+0.006
-0.004
(13.2 ±0.25) ( 0.88 +0.15
-0.10 )
DIMENSIONS ARE IN INCHES (MM)
Figure 68. RD-19240FS Mechanical Outline

RD/RDC Series Pin Out Tables

Table 29. RDC-19220/19220S Pin Outs (40-pin)
No. Name Description No. Name Description
1 A Resolution Control 40 +5V Power Supply
2 B Resolution Control 39 EL Enable LSBs (see
note)
3 INH Inhibit 38 Bit 16 LSB (16-bit mode)
4 +REF +Reference Input 37 Bit 8
5 -REF -Reference Input 36 Bit 15
6 -VCO Neg. VCO Input 35 Bit 7
7 -VSUM Velocity Sum Point 34 Bit 14 LSB (14-bit mode)
8 VEL Velocity Output 33 Bit 6
9 +C Signal Input 32 Bit 13
10 COS Signal Output 31 Bit 5
11 -C Signal Input 30 Bit 12 LSB (12-bit mode)
12 +S Signal Input 29 Bit 4
13 +SIN Signal Output 28 Bit 11
14 -S Signal Input 27 Bit 3
15 -5V Power Supply 26 Bit 10 LSB (10-bit mode)
16 RS Sampling Set 25 Bit 2
17 RC Current Set 24 Bit 9
18 EM Enable MSBs 23 Bit 1 MSB
19 AGND Analog Ground 22 CB Converter Busy
20 GND Ground 21 BIT Built-in Test
Note:
When -5V is applied to pin 1 ( EL ), Converter Busy (CB) becomes Zero Index (ZI), only valid
on non S version.

Table 30. RDC-19222/19222S Pin Outs (44-pin)

1 EL Enable LSBs 44 Bit 16 LSB (16-bit mode)
2 +5V Power Supply 43 Bit 8 Res C
3 A Resolution Control 42 Bit 15
4 B Resolution Control 41 Bit 7 Res 1
5 INH Inhibit 40 Bit 14 LSB (14-bit mode)
6 +REF +Reference Input 39 Bit 6 Res 2
7 -REF -Reference Input 38 Bit 13
8 -VCO 37 Bit 5 Res 3
9 -VSUM Velocity Sum Point 36 Bit 12 LSB (12-bit mode)
10 VEL Velocity Output 35 Bit 4 Res 4
11 +C Signal Input 34 Bit 11
12 COS Signal Output 33 Bit 3 Res 5
14 +S Signal Input 31 Bit 2 Res 6
15 SIN Signal Output 30 Bit 9
16 -S Signal Input 29 Bit 1 MSB Res 7
17 -5V Power Supply 28 CB Converter Busy
18 RS Sampling Set 27 BIT Built-in Test
19 RC Current Set 26 +5C Charge pump
(+5V) connection
20 EM Enable MSBs 25 +CAP Charge pump
connection
21 AGND Analog Ground 24 GND Ground
22 -5C (-5V) Charge pump 23 -CAP Charge pump
connection connection
Notes:
1. When -5V is applied to pin 1 ( EL ), Converter Busy (CB) becomes Zero Index (ZI) and only
valid on non-S version.
2. When using the built-in -5V inverter: connect pin 2 to 26, pins 17 to 22, and a 10µF/10 VDC
capacitor from pin 23 (negative terminal) to pin 25 (positive terminal). Connect a 47µF/10
VDXC capacitor from -5V to GND.

Table 31. RDC-19224 Pin Outs (44-pin)

1 -REF - Reference Input 44 +REF +Reference Input
2 -VCO 43 INH Inhibit
3 -VSUM Velocity Sum Point 42 B
4 VEL Velocity Output 41 A
5 +C Signal Input 40 + 5V Power Supply
6 COS Signal Output 39 EL Enable LSBs
(LSB)
8 +S Signal Input 37 Bit 8
9 SIN Signal Input 36 Bit 15
10 -S Signal Input 35 Bit 7
11 -5V Power Supply 34 Bit 14
12 RS Sampling Set 33 Bit 6
13 RC Current Set 32 Bit 13
14 EM Enable MSBs 31 Bit 5
15 A GND Analog Ground 30 Bit 12
16 -5C (-5V) Charge Pump 29 Bit 4
Connection
17 -CAP Charge Pump 28 BIT 11
Connection
18 GND Ground 27 BIT 3
19 +CAP Charge Pump 26 BIT 10
Connection
20 +5C(+5V) Charge Pump 25 BIT 2
Connection
21 BIT Built-in-Test 24 BIT 9
22 CB Converter Busy 23 BIT 1
(MSB)

Table 32. RD-19230 Pin Outs

No. Name No. Name
1 VEL 33 VDD (+5V)
2 -VCO 34 N/C
3 SJ1 35 Bit 9
4 SJ2 36 Bit 2
5 SHIFT 37 Bit 10
6 VEL2 38 Bit 3
7 TP1(TEST POINT) 39 Bit 11
8 VEL1 40 Bit 4
9 TP2(TEST POINT) 41 N/C
10 +C 42 Bit 12
11 COS 43 Bit 5
12 -C 44 Bit 13
13 +S 45 Bit 6
14 SIN 46 Bit 14
15 -S 47 Bit 7
16 VSS (-5V) 48 Bit 15
17 VSS (-5V) 49 Bit 8
19 R CLK 51 A (LSB + 1)
20 R SET 52 DSR
21 ENM 53 N/C
22 AGND 54 TP5(TEST POINT)
23 VSSP 55 ZIP _ EN
24 NCAP 56 TP6(TEST POINT)
25 GND 57 ENL
26 PCAP 58 VDD (+5V)
27 VDDP 59 UP / DN
28 BIT 60 D0
29 U/B 61 D1
30 A _ QUAD _ B 62 INH
31 CB (ZI) 63 RH
32 Bit 1 64 RL

Table 33. RD-19240 Pin Outs

No. Name
Internally connected to pin 33
Underside Pad (+5v). Connect to +5v or
leave floating. (Note 2)
No. Name No. Name
1 VEL 33 VDD (+5V) Note 2
2 -VCO 34 N/C
3 SJ1 35 Bit 9
4 SJ2 36 Bit 2
5 SHIFT 37 Bit 10
6 VEL2 38 Bit 3
8 VEL1 40 Bit 4
10 +C 42 Bit 12
11 COS 43 Bit 5
12 -C 44 Bit 13
13 +S 45 Bit 6
14 SIN 46 Bit 14 (LSB)
15 -S 47 Bit 7
16 VSS (-5V) 48 N/C
17 VSS (-5V) 49 Bit 8
19 R CLK 51 A (LSB + 1)
20 R SET 52 DSR
21 ENM 53 N/C
22 AGND 54 N/C
23 VSSP 55 ZIP _ EN
24 NCAP 56 TP6(TEST POINT)
25 GND 57 ENL
26 PCAP 58 VDD (+5V)
27 VDDP 59 UP / DN
28 BIT 60 D0
29 U/B 61 D1
30 A _ QUAD _ B 62 INH
31 CB (ZI) 63 RH
32 Bit 1 (MSB) 64 RL
Notes: 1. When using the built-in –5V inverter: connect pad 33 to 58, pad 16 to 17, and a 10 mf/10 VDC
capacitor from pad 24 (negative terminal) to pad 26 (positive terminal). Connect a 47 mf/10
VDC capacitior from –5V to GND. The current drain from the +5V supply doubles. No external
–5V supply is needed.
2. Pad 33 is electrically connected to bottom of package.

Transformers
(See Table 9 for further information)
0.32 MAX 0.61 MAX

(8.13) (15.49)
0.125 MIN
(3.17) 0.09 MAX 0.15 MAX
(2.29) (3.81)
1 2 3 5
0.600 0.81 MAX
T1A (15.24) (20.57)
10 9 8 7 6
0.105 (2.66)
SIDE VIEW 0.100 (2.54) TYP
TOL NON CUM
TERMINALS
0.025 ±0.001 (6.35 ±0.03) DIAM BOTTOM VIEW
0.125 (3.18) MIN LENGTH
SOLDER-PLATED BRASS
Dimensions are shown in inches (mm).
1 6
INPUT OUTPUT
5 10
Figure 69. Reference Transformer Mechanical Outline and Schematic (B-246)
(SEE Table 9)
0.61 MAX
(15.49)
0.61 MAX
(15.49) 0.15 MAX 0.09 MAX
(3.81) (2.29)
0.30 MAX 0.09 MAX 0.15 MAX
(7.62) (2.29) (3.81)
1 3 4 5 11 12 14 15
0.81 MAX
(20.57)
T1A T1B 0.600
(15.24)
10 9 8 7 6 20 19 18 17 16
0.115 MAX
(2.92)
SIDE VIEW 0.100 (2.54) TYP BOTTOM VIEW
TOL NON CUM
TERMINALS
0.025 –0.001 (6.35 –0.03) DIAM BOTTOM VIEW PIN NUMBERS FOR REF. ONLY
0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS
T1A
S1 1 6 -SIN
5
3 10
S3 +SIN
SYNCHRO
RESOLVER
INPUT
T1B OUTPUT
11 16 -COS
S2 15 20 +COS
Figure 70. Transformer Layout and Schematic (Syn Input - 52034/52035)

0.61 MAX
(15.49)
0.61 MAX
(15.49) 0.15 MAX 0.09 MAX
(3.81) (2.29)
0.30 MAX 0.09 MAX 0.15 MAX
(7.62) (2.29) (3.81)
1 3 4 5 11 12 14 15
0.81 MAX
(20.57)
T1A T1B 0.600
(15.24)
10 9 8 7 6 20 19 18 17 16
0.115 MAX
(2.92)
SIDE VIEW 0.100 (2.54) TYP BOTTOM VIEW
TOL NON CUM
TERMINALS
0.025 –0.001 (6.35 –0.03) DIAM BOTTOM VIEW PIN NUMBERS FOR REF. ONLY
0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS
T1A
S1 1 6 -SIN
3 10
S3 +SIN
RESOLVER
RESOLVER
INPUT
T1B OUTPUT
11 16 -COS
S4
S2 15 20 +COS
Figure 71. Transformer Layout and Schematic (Res Input - 52036/52037/52038)
CASE IS BLACK AND

NON-CONDUCTIVE
1.14 MAX 0.25

(28.96) (6.35)
MIN.
• • • • +
S3 S1 +15 V +S
(+15 V) (-R)
*
* * *
1.14 MAX 52039 0.85 ±0.010

(28.96) or (21.59 ±0.25)
24133
(RH) (RL) (V) (+R) (-Vs)

S2 V +C -Vs
*+
• • • •
(BOTTOM VIEW)
0.42
0.13 ±0.03 (10.67)
(3.30 ±0.76) MAX.
0.21 ±0.3
(5.33 ±0.76)
0.175 ±0.010 (4.45 ±0.25)
NONCUMULATIVE
TOLERANCE 0.040 ±0.002 DIA. PIN.
SOLDER PLATED BRASS
+15 V +15 V
Input Output Input Output

RH +R (RH) S1 +S
24133 S2 52039
RL -R (RL) S3 +C
V -Vs V -Vs
(Analog (-15 V) (Analog (-15 V)
Gnd) Gnd)
Figure 72. 60 Hz Transformer Mechanical Outline – (Syn Input – 52039, Ref Input - 24133)

GLOSSARY
Accuracy.....................................A measurement deviation from a calibrated standard.
AGND .......................................... Analog Ground.
BW (Bandwidth) .........................The frequency band in which a system can process information. Also known as the
3dB point.
Bipolarity ....................................The difference between a measurement in one direction and a measurement in the
opposite direction. Also known as reversal error.
BIT ( Built-in test) .......................Digital output that will indicate if a fault condition exists.
Carrier Frequency (fc) ...............Reference or excitation frequency to the position transducer.
Charge Pump..............................A voltage-doubler built into the converter to provide a -5 V supply to the chip.
Coarse Angle..............................In a two-speed system, the reading from the resolver with a 1:1 ratio.
CB (Converter Busy)..................A pulse that is generated for each LSB of change in the converter.
Differential ..................................Input signal that is with respect to another signal (S3-S1), but not to ground.
Differential Linearity…………… Measurement (in LSBs) of the deviation of the digital output from equal step-per-bit
behavior. The worst-case deviation of the smallest or largest step (bit) from the
theoretical (LSB) size, expressed as a percentage of the theoretical (LSB) size, is
the differential non-linearity.
Direct Input (sin/cos) .................Input signal that is with respect to ground.
Encoder.......................................A device used to translate angular position data into a series of digital pulses.
Fine Angle...................................In a two-speed system, the reading from the resolver with a 1:N ratio, where N >1.
GND.............................................Digital Ground.
HOLE...........................................Change data by 1 LSB and converter does not respond with any change. This is
referred to as a hole in data.
Inductosyn® ...............................A device that translates linear or rotational position data into analog signals.
J-lead ..........................................The lead of a device that is J- or hooked-shaped.
Line-to-Line Voltage ..................The measurement (in Vrms) between two signals.
LSB..............................................Least significant bit. In 10-bit resolution this would be bit 10, in 16-bit resolution this
would be bit 16.

GLOSSARY
LVDT (Linear Variable

Differential Transformer) ......... A type of device that changes a linear position into one or more analog signals.
MSB ............................................ Most significant bit. For any bit resolution this would be bit 1.
Over Voltage .............................. A voltage amplitude that is too large for the circuit to operate properly.
Quadrant .................................... An arc of 90°, or one quarter of a circle.
Quadrature ................................. A 90° out of phase portion of a signal, with respect to reference.
Reference ................................... Excitation for position feedback device and converter.
Resolution.................................. Number of bits available for measurement.
Resolver ..................................... Type of transducer whose four-wire output has a direct relationship to the anglular
position of the shaft.. A resolver contains two output windings 90° out of phase.
Reversal Error............................ The difference between a measurement in one direction and a measurement in the
opposite direction. Also known as bipolarity.
RPS
(Revolutions per second) ......... A unit of measure for velocity or tracking rate.
Scale Factor ............................... Accuracy measurement for the velocity output of the RDC-19220 series. Average of
the gain errors or the best fit straight line, for positive and negative rotations.
Speed Ratio................................ The ratio of coarse to fine in a two-speed system.
Synchro ...................................... Type of transducer with a three-wire output having a direct relationship to the
angular position of the shaft. A synchro contains three output windings 120° out of
phase.
TR (Tracking rate)...................... A velocity or speed at which the converter can monitor the changes of the signal
output.
Type II Tracking ......................... A type of servo control loop.
Velocity....................................... The rate of a change in position for a certain time interval.
Vrms ........................................... Root-mean-square, or effective voltage (Vp x 1/√2 ) .
Zero Offset ................................. Voltage or accuracy measurement at 0 (RPS or LSB).

INDEX
A G
A quad B.......................................................... 57 gearshifting .. See resolution: changing on the fly
acceleration lag................................................ 64
I
angular data ..................................................... 55
B
x
bandwidth Icons
and carrier frequency................................... 80 Caution......................................................... ix
and external component values.. 36, 50, 87, 88 Disk.............................................................. ix
and input signal amplitude........................... 81 Idea/Tip ........................................................ ix
and resolution .............................................. 80 Note.............................................................. ix
optimization................................................. 81 Reference ..................................................... ix
bipolarity ......................................................... 61 Warning........................................................ ix
x x
x imbalance matching .........................................10
built-in test................................................... 5, 64 incremental encoder .........................................57
incremental encoder output ..............................56
C
incremental encoder signals .......................56, 57
calculation of external components ........... 36, 73 Inductosyn input.........................................26, 27
x Inductosyn-to-digital conversion .....................26
CBW ........................................................ 4, 50, 51 inhibit .........................................................57, 66
CBW/10 ........................................................... 4, 51 input configurations
4, 38 DC sin/cos input...........................................28
converter busy (CB) ........................................ 57 differential resolver input.............................16
x direct input .............................................13, 15
direct sin/cos input .......................................13
D Inductosyn input...........................................26
DC sin/cos input .............................................. 28 LVDT input..................................................19
differential resolver input ................................ 16 reference input..............................................29
digital output data ............................................ 66 single-ended input ........................................13
digital position data ......................................... 52 synchro input................................................18
direct input........................................... 13, 14, 15
J
direct sin/cos input........................................... 13
x J-lead..............................................................113
E L
electrical static discharge................................... x layout considerations........................................77
enable .............................................................. 66 linearity ............................................................61
encoder emulation ........................................... 56 LVDT
Encoder Emulation .......................................... 56 application testing ........................................97
error digital output code........................................25
accuracy....................................... 16, 100, 102 input .......................................................18, 20
phase.................................................... 64, 100 input scaling ...............................20, 21, 23, 24
30, 31, 32, 100, 102 resolution................................................19, 24
ESD ................................................................... x
M
external components.................. 3, 36, 51, 56, 61
maximum tracking rate ........................36, 38, 61

INDEX
MTBF curves................................................. 111 RS ...................................................................... 4

RV ................................................................ 4, 50
N
S
North Reference Pole (NRP) ........................... 57
x sampling frequency ................................... 39, 86
scale factor error.............................................. 61
P
single 5V power supply..................................... 5
phase error ....................................................... 64 single-ended input ..................................... 13, 16
phase shift compensation................................. 33 software..................................................3, 36, 51
pin out tables.................................................. 117 switching resolution on the fly ........................ 87
power supplies ................................................... 6 synchro ...................................................... 30, 32
power supply protection .................................. 78 as error source ............................................. 31
conversion theory .......................105, 107, 109
Q input ............................................................ 18
quadrature ................................ 29, 30, 31, 32, 33 simulation.................................................... 96
synchro-to-DC conversion .......................... 94
R transformer isolation ................................... 34
RB................................................................. 4, 50 voltage transients......................................... 79
reference input ................................................. 29 T
resistor tolerance.............................................. 10
resistor tolerance and imbalance matching ...... 10 Text Usage ....................................................... ix
resolution ......................................................... 54 tracking rate..................................................... 36
and BW........................................................ 80 transfer function ........................................ 49, 50
and maximum tracking rate ......................... 36 transformers .......................................34, 35, 122
changing on the fly ...................................... 87 troubleshooting................................................ 98
LVDT mode........................................... 19, 24
V
vs. carrier frequency .................................... 36
resolver velocity............................................................ 61
and incremental encoder .............................. 56 and external component values ........50, 86, 87
30, 31, 32 output .................................36, 38, 52, 61, 110
conversion theory ...................... 105, 107, 109 ripple ........................................................... 63
differential ................................................... 16
W
direct input............................................. 13, 15
grounding tips.............................................. 77 x
resolver-to-DC conversion........................... 94
Z
simulation .................................................... 96
transformer isolation.................................... 34 zero index (ZI) ................................................ 57
two-speed..................................................... 90 zero offset........................................................ 61
voltage transients ......................................... 79
reversal error.................................................... 61

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RD/RDC

The information provided in this Applications Manual is believed to be accurate;

Specifications are subject to change without notice.

105 Wilbur Place, Bohemia, New York 11716-2426

For Technical Support – 1-800-DDC-5757 ext. 7771

All rights reserved. No part of this manual may be

A Testing and Troubleshooting section is provided to aid in diagnosing performance problems

The Synchro/Resolver Conversion Theory Section discuss Synchro/Resolver conversion

Data Device Corporation i RD/RDC Series Manual

The RD/RDC Converters are static-sensitive devices and should be

Data Device Corporation ii RD/RDC Series Manual

HOW TO USE THIS GUIDE ........................................................................................................................IX

Data Device Corporation iii RD/RDC Series Manual

Dual Bandwidths ..................................................................................................................................47

Data Device Corporation iv RD/RDC Series Manual

SYNCHRO/RESOLVER CONVERSION THEORY.................................................................................. 105

QUALITY REPORTS-MTBF REPORTS.................................................................................................. 111

MECHANICAL SPECIFICATIONS .......................................................................................................... 112

INDEX ....................................................................................................................................................... 126

Data Device Corporation v RD/RDC Series Manual

Data Device Corporation vi RD/RDC Series Manual

Figure 44. RD/RDC to PC Connection Diagram ......................................................................... 71

Data Device Corporation vii RD/RDC Series Manual

Data Device Corporation viii RD/RDC Series Manual

BOLD ITALIC–designates DDC Part Numbers.

Courier New–indicates code examples.

<…> - indicates user-entered text or commands.

Symbols and Icons

The Idea/Tip icon signifies useful supplementary information.

The Note Icon signifies important supplementary information.

The Caution icon identifies information to avoid possible damage

The Reference icon indicates related material in this User’s

The Disk Icon describes software-related information.

Data Device Corporation ix RD/RDC Series Manual

Special Handling and Cautions

Ensure that standard ESD precautions are followed. As a minimum, one

Data Device Corporation x RD/RDC Series Manual

Figure 1. Typical Application

Data Device Corporation 1 RD/RDC Series Manual

To understand the modes of operation, the following diagram divides the

Figure 2. RDC-19220/2/4 Series Block Diagram

Figure 3. RDC-19220/2S Series Block Diagram

Data Device Corporation 2 RD/RDC Series Manual

operate. VSSP TIMING R CLK

INH EM EL D1 D0 A QUAD B A U/B CB/ZIP UP/DN

Figure 4. RD-19230/RD-19240 Series Block Diagram

The RD-19230/RD-19240 converters are very similar to the RDC-19220

For product specification tables, refer to our Web site at www.ddc-web.com

Data Device Corporation 3 RD/RDC Series Manual

Table 1. Selection Criteria

*for +5V only operation

Data Device Corporation 4 RD/RDC Series Manual

Input Signal Configurations

Reference Input Configurations

Mandatory External Components

Transfer Function and Bode Plot

Built-In Test (BIT)

Data Device Corporation 5 RD/RDC Series Manual

In addition to the physical package differences, these converters also differ