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Electronics and Communication Engineering
Electronics and Communication Engineering
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PULSE AND DIGITAL CIRCUITS
(Electronics and Communication Engineering)
Time: 3 Hours Max. Marks: 75
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(25 Marks)
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1.a) Discuss the response of RC high pass circuit to ramp input voltage. [2]
b) Draw the low-pass circuit and explain its working. [3]
c) Draw the basic circuit diagram of negative peak clamper circuit. [2]
d) Explain the working of an emitter coupled clipper. [3]
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f)
g)
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List different switching times of a diode.
Explain how diode acts as a switch. JJ
What are the commutating capacitors? Why these are used in binary?
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[2]
[3]
[2]
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h) Write a short note on hysteresis. [3]
i) Why totem pole is used in DTL. [2]
j) How do sampling gates differ from logic gates? [3]
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PART-B
(50 Marks)
2.a) Draw the response of the circuit for step input critically damped and over damped cases
for a fixed value of R and C.
b) Explain the working of high-pass RC circuit as a differentiator. [6+4]
OR
3.a) Define the rise time and write the expression of it.
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b) Derive an expression for the output of a high-pass circuit excited by a square input. [4+6]
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List and explain all the switching times of a transistor.
OR
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7.a) Design Transistor switch circuit.
b) Explain in detail about the Silicon-controlled-switch circuits. [5+5]
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8.a) With the help of neat circuit diagram and waveform ,explain the principle of operation of
collector coupled monostable multivibrator.
b) With the help of neat circuit diagram and waveforms, explain the working of a Schmitt
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trigger. [5+5]
OR
9.a) Draw a simple current sweep circuit and explain its working with the help of diagrams.
b) Draw the circuit diagram and waveforms of a transistor bootstrap time base generator and
explain principle of operation. [5+5]
10.a) With help of a neat diagram, explain the working of bidirectional gates using transistors.
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b) Draw and explain a diode AND circuit for negative logic and how it works. How an OR
circuit acts a buffer circuit? [5+5]
OR
11.a) Compare the performance of various logic families.
b) Explain how to cancel a pedestal in a sampling gate with suitable circuit diagram. [5+5]
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