CS5505/6/7/8

Very Low Power, 16-Bit and 20-Bit A/D Converters

Features Description
l Very Low Power Consumption The CS5505/6/7/8 are a family of low power CMOS A/D
- Single supply +5 V operation: 1.7 mW converters which are ideal for measuring low-frequency
signals representing physical, chemical, and biological
- Dual supply ±5 V operation: 3.2 mW processes.
l Offers superior performance to VFCs and
The CS5507/8 have single-channel differential analog
multi-slope integrating ADCs
and reference inputs while the CS5505/6 have four
l Differential Inputs pseudo-differential analog input channels. The
- Single Channel (CS5507/8) and Four-Channel CS5505/7 have a 16-bit output word. The CS5506/8
(CS5505/6) pseudo-differential versions have a 20-bit output word.The CS5505/6/7/8 sample
l Either 5 V or 3.3 V Digital Interface upon command up to 100 output updates per second.

l Linearity Error: The on-chip digital filter offers superior line rejection at
- ±0.0015% FS (16-bit CS5505/7) 50 and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Hz.).
- ±0.0007% FS (20-bit CS5506/8)
l Output update rates up to 100/second The CS5505/6/7/8 include on-chip self-calibration cir-
cuitry which can be initiated at any time or temperature
l Flexible Serial Port
to ensure minimum offset and full-scale errors.
l Pin-Selectable Unipolar/Bipolar Ranges
The CS5505/6/7/8 serial port offers two general-purpose
modes for the direct interface to shift registers or syn-
chronous serial ports of industry-standard
microcontrollers.

ORDERING INFORMATION
See page 30.
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Cirrus Logic, Inc.

Crystal Semiconductor Products Division Copyright  Cirrus Logic, Inc. 1997 MAR ‘95
P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
DS59F4
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com 1
 CS5505/6/7/8

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
3.3V ± 5%; VREF+ = 2.5V(external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a 10nF
to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)

CS5505/7-A CS5507-S
Parameter* Min Typ Max Min Typ Max Units
Specified Temperature Range -40 to +85 -55 to +125 °C
Accuracy
Linearity Error - 0.0015 0.003 - 0.0015 0.003 ±%FS
Differential Nonlinearity - ±0.25 ±0.5 - ±0.25 ±0.5 LSB16
Full Scale Error (Note 3) - ±0.25 ±2 - ±0.5 ±2 LSB16
Full Scale Drift (Note 4) - ±0.5 - - ±2 - LSB16
Unipolar Offset (Note 3) - ±0.5 ±2 - ±1 ±4 LSB16
Unipolar Offset Drift (Note 4) - ±0.5 - - ±1 - LSB16
Bipolar Offset (Note 3) - ±0.25 ±1 - ±0.5 ±2 LSB16
Bipolar Offset Drift (Note 4) - ±0.25 - - ±0.5 - LSB16
Noise (Referred to Output) - 0.16 - - 0.16 - LSB-
rms16
Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the
master clock frequency. Both source resistance and shunt capacitance are therefore critical in
determining the CS5505/6/7/8’s source impedance requirements. For more information refer to the
text section Analog Input Impedance Considerations.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after calibration at the temperature of interest.
4. Total drift over the specified temperature range since calibration at power-up at 25°C.
Recalibration at any temperature will remove these errors.

Unipolar Mode Bipolar Mode

mV LSB’s % FS ppm FS LSB’s % FS ppm FS
10 0.26 0.0004 4 0.13 0.0002 2
19 0.50 0.0008 8 0.26 0.0004 4
38 1.00 0.0015 15 0.50 0.0008 8
76 2.00 0.0030 30 1.00 0.0015 15
152 4.00 0.0061 61 2.00 0.0030 30
VREF = 2.5V

CS5505/7; 16-Bit Unit Conversion Factors

* Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.

2 DS59F4
 CS5505/6/7/8

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a
10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)

CS5506/8-B CS5508-S
Parameter* Min Typ Max Min Typ Max Units
Specified Temperature Range -40 to +85 -55 to +125 °C
Accuracy
Linearity Error - 0.0007 0.0015 - 0.0015 0.003 ±%FS
Differential Nonlinearity Bits
(No Missing Codes) 20 - - 20 - -
Full Scale Error (Note 3) - ±4 ±32 - ±8 ±32 LSB20
Full Scale Drift (Note 4) - ±8 - - ±32 - LSB20
Unipolar Offset (Note 3) - ±8 ±32 - ±16 ±64 LSB20
Unipolar Offset Drift (Note 4) - ±8 - - ±16 - LSB20
Bipolar Offset (Note 3) - ±4 ±16 - ±8 ±32 LSB20
Bipolar Offset Drift (Note 4) - ±4 - - ±8 - LSB20
Noise (Referred to Output) - 2.6 - - 2.6 - LSB-
rms20

Unipolar Mode Bipolar Mode

mV LSB’s % FS ppm FS LSB’s % FS ppm FS
0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12
1.192 0.50 0.0000477 0.47 0.26 0.0000238 0.24
2.384 1.00 0.0000954 0.95 0.50 0.0000477 0.47
4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95
9.537 4.00 0.0003814 3.81 2.00 0.0001907 1.91
VREF = 2.5V

CS5506/8; 20-Bit Unit Conversion Factors

DYNAMIC CHARACTERISTICS
Parameter Symbol Ratio Units
Modulator Sampling Frequency fs fclk/2 Hz
Output Update Rate (CONV = 1) fout fclk/1622 Hz
Filter Corner Frequency f-3dB fclk/1928 Hz
Settling Time to 1⁄2 LSB (FS Step) ts 1/fout s

DS59F4 3
 CS5505/6/7/8

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a
10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)

CS5505/7-A
CS5506/8-B CS5507/8-S
Parameter* Min Typ Max Min Typ Max Units
Specified Temperature Range -40 to +85 -55 to +125 °C
Analog Input
Analog Input Range: Unipolar 0 to +2.5 0 to +2.5 Volts
(VAIN+)-(VAIN-) Bipolar (Note 5) ±2.5 ±2.5 Volts
Common Mode Rejection: dc - 105 - - 105 - dB
50, 60 Hz (Note 6) 120 - - 120 - - dB
Off Channel Isolation - 120 - - 120 - dB
Input Capacitance - 15 - - 15 - pF
DC Bias Current (Note 1) - 5 - - 5 - nA
Voltage Reference (Output)
VREFOUT Voltage - (VA+)-2.5 - - (VA+)-2.5 - Volts
VREFOUT Voltage Tolerance - - 4.0 - - 4.0 %
VREFOUT Voltage Temperature Coefficient - 60 - - 60 - ppm/°C
VREFOUT Line Regulation - 1.5 - - 1.5 - mV/Volt
VREFOUT Output Voltage Noise
0.1 to 10 Hz - 50 - - 50 - µVp-p
VREFOUT: Source Current - - 3 - - 3 µA
Sink Current - - 50 - - 50 µA
Power Supplies
DC Power Supply Currents: ITotal - 340 450 - 340 450 µA
IAnalog - 300 - - 300 - µA
IDigital - 40 - - 40 - µA
Power Dissipation: (Note 7)
SLEEP inactive - 3.2 4.5 - 3.2 4.5 mW
SLEEP active - 5 10 - 10 25 µW
Power Supply Rejection: Positive Supplies - 80 - - 80 - dB
Negative Supplies - 80 - - 80 - dB
Notes: 5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and
VA- supply voltages.
6. XIN = 32.768 kHz. Guaranteed by design and / or characterization.
7. All outputs unloaded. All inputs CMOS levels. SLEEP mode controlled by M/SLP pin.
SLEEP active = M/SLP pin at (VD+)/2 input level.

4 DS59F4
 CS5505/6/7/8

5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+VD+ = 5V ± 10%; VA-= -5V ± 10%;
DGND = 0.) All measurements below are performed under static conditions. (Note 2)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN VIH 3.5 - - V
M/SLP VIH 0.9VD+ - - V
All Pins Except XIN and M/SLP VIH 2.0 - - V
Low-Level Input Voltage: XIN VIL - - 1.5 V
M/SLP VIL - - 0.1VD+ V
All Pins Except XIN and M/SLP VIL - - 0.8 V
M/SLP SLEEP Active Threshold (Note 8) VSLP 0.45VD+ 0.5VD+ 0.55VD+ V
High-Level Output Voltage (Note 9) VOH (VD+)-1.0 - - V
Low Level Output Voltage Iout = 1.6 mA VOL - - 0.4 V
Input Leakage Current Iin - 1 10 µA
3-State Leakage Current IOZ - - ±10 µA
Digital Output Pin Capacitance Cout - 9 - pF
Notes: 8. Under normal operation this pin should be tied to VD+ or DGND. Anytime the voltage on the M/SLP
pin enters the SLEEP active threshold range the device will enter the power down condition. Returning
to the active state requires elapse of the power-on reset period, the oscillator to start-up, and elapse
of the wake-up period.
9. Iout = -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ Iout = -40 µA).

3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;
VA-= -5V ± 10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN VIH 0.7VD+ - - V
M/SLP VIH 0.9VD+ - - V
All Pins Except XIN and M/SLP VIH 0.6VD+ - - V
Low-Level Input Voltage: XIN VIL - - 0.3VD+ V
M/SLP VIL - - 0.1VD+ V
All Pins Except XIN and M/SLP VIL - - 0.16VD+ V
M/SLP SLEEP Active Threshold (Note 8) VSLP 0.43VD+ 0.45VD+ 0.47VD+ V
High-Level Output Voltage Iout = -400 µA VOH (VD+)-0.3 - - V
Low Level Output Voltage Iout = 400 µA VOL - - 0.3 V
Input Leakage Current Iin - 1 10 µA
3-State Leakage Current IOZ - - ±10 µA
Digital Output Pin Capacitance Cout - 9 - pF

DS59F4 5
 CS5505/6/7/8

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;

VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

Master Clock Frequency: Internal Oscillator: -A,B XIN 30.0 32.768 53.0 kHz
-S or 30.0 32.768 34.0 kHz
External Clock: fclk 30 - 163 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times: Any Digital Input (Note 10) trise - - 1.0 µs
Any Digital Output - 50 - ns
Fall Times: Any Digital Input (Note 10) tfall - - 1.0 µs
Any Digital Output - 20 - ns
Start-Up
Power-On Reset Period (Note 11) tres - 10 - ms
Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu - 500 - ms
Wake-up Period (Note 13) twup - 1800/fclk - s
Calibration
CONV Pulse Width (CAL = 1) (Note 14) tccw 100 - - ns
CONV and CAL High to Start of Calibration tscl - - 2/fclk+200 ns
Start of Calibration to End of Calibration tcal - 3246/fclk - s
Conversion
Set Up Time A0, A1 to CONV High tsac 50 - - ns
Hold Time A0, A1 after CONV High thca 100 - - ns
CONV Pulse Width tcpw 100 - - ns
CONV High to Start of Conversion tscn - - 2/fclk+200 ns
Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk - - s
Hold Time BP/UP stable after DRDY falls tbuh 0 - - ns
Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk - s
Notes: 10. Specified using 10% and 90% points on waveform of interest.
11. An internal power-on-reset is activated whenever power is applied to the device, or when coming out
of a SLEEP state.
12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
13. The wake-up period begins once the oscillator starts;
or when using an external fclk, after the power-on reset time elapses.
14. Calibration can also be initiated by pulsing CAL high while CONV=1.
15. Conversion time will be 1622/fclk if CONV remains high continuously.

6 DS59F4
 CS5505/6/7/8

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX VA+ = 5V ± 10%;

VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

Master Clock Frequency: Internal Oscillator: -A,B XIN 30.0 32.768 53.0 kHz
-S or 30.0 32.768 34.0 kHz
External Clock: fclk 30 - 163 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times: Any Digital Input (Note 10) trise - - 1.0 µs
Any Digital Output - 50 - ns
Fall Times: Any Digital Input (Note 10) tfall - - 1.0 µs
Any Digital Output - 20 - ns
Start-Up
Power-On Reset Period (Note 11) tres - 10 - ms
Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu - 500 - ms
Wake-up Period (Note 13) twup - 1800/fclk - s
Calibration
CONV Pulse Width (CAL = 1) (Note 14) tccw 100 - - ns
CONV and CAL High to Start of Calibration tscl - - 2/fclk+200 ns
Start of Calibration to End of Calibration tcal - 3246/fclk - s
Conversion
Set Up Time A0, A1 to CONV High tsac 50 - - ns
Hold Time A0, A1 after CONV High thca 100 - - ns
CONV Pulse Width tcpw 100 - - ns
CONV High to Start of Conversion tscn - - 2/fclk+200 ns
Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk - - s
Hold Time BP/UP stable after DRDY falls tbuh 0 - - ns
Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk - s

DS59F4 7
 CS5505/6/7/8

XIN

XIN/2

CAL
t ccw
CONV
t scl t cal
STATE Standby Calibration Standby

Figure 1. Calibration Timing (Not to Scale)

XIN

XIN/2

A0, A1
t sac t hca
CONV
t cpw
DRDY

BP/UP
t bus t buh
t scn t con
STATE Standby Conversion Standby

Figure 2. Conversion Timing (Not to Scale)

8 DS59F4
 CS5505/6/7/8

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;

VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

SSC Mode (M/SLP = VD+)
Access Time: CS Low to SDATA out (DRDY = low) tcsd1 - - 2/fclk ns
DRDY falling to MSB (CS = low) tdfd - 2/fclk 3/fclk ns
SDATA Delay Time: SCLK falling to next SDATA bit tdd1 - 80 250 ns
SCLK Delay Time SDATA MSB bit to SCLK rising tcd1 - 1/fclk - ns
Serial Clock (Out) Pulse Width High tph1 - 1/fclk - ns
Pulse Width Low tpl1 - 1/fclk - ns
Output Float Delay: CS high to output Hi-Z (Note 16) tfd1 - - 2/fclk ns
SCLK rising to SDATA Hi-Z tfd2 - 1/fclk - ns
SEC Mode (M/SLP = DGND)
Serial Clock (In) fsclk 0 - 2.5 MHz
Serial Clock (In) Pulse Width High tph2 200 - - ns
Pulse Width Low tpl2 200 - - ns
Access Time: CS Low to data valid (Note 17) tcsd2 - 60 200 ns
Maximum Delay time: (Note 18)
SCLK falling to new SDATA bit tdd2 - 150 310 ns
Output Float Delay: CS high to output Hi-Z (Note 16) tfd3 - 60 150 ns
SCLK falling to SDATA Hi-Z tfd4 - 160 300 ns
Notes: 16. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the
current data bit and then go to high impedance.
17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 f clk cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high
sooner than 2 fclk + 200 ns after CS goes low.
18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.

DS59F4 9
 CS5505/6/7/8

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX VA+ = 5V ± 10%; VD+ = 3.3V ±
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

SSC Mode (M/SLP = VD+)
Access Time: CS Low to SDATA out (DRDY = low) tcsd1 - - 2/fclk ns
DRDY falling to MSB (CS = low) tdfd - 2/fclk 3/fclk ns
SDATA Delay Time: SCLK falling to next SDATA bit tdd1 - 265 400 ns
SCLK Delay Time SDATA MSB bit to SCLK rising tcd1 - 1/fclk - ns
Serial Clock (Out) Pulse Width High tph1 - 1/fclk - ns
Pulse Width Low tpl1 - 1/fclk - ns
Output Float Delay: CS high to output Hi-Z (Note 16) tfd1 - - 2/fclk ns
SCLK rising to SDATA Hi-Z tfd2 - 1/fclk - ns
SEC Mode (M/SLP = DGND)
Serial Clock (In) fsclk 0 - 1.25 MHz
Serial Clock (In) Pulse Width High tph2 200 - - ns
Pulse Width Low tpl2 200 - - ns
Access Time: CS Low to data valid (Note 17) tcsd2 - 100 200 ns
Maximum Delay time: (Note 18)
SCLK falling to new SDATA bit tdd2 - 400 600 ns
Output Float Delay: CS high to output Hi-Z (Note 16) tfd3 - 70 150 ns
SCLK falling to SDATA Hi-Z tfd4 - 320 500 ns

10 DS59F4
 CS5505/6/7/8

XIN
XIN/2

CONV

CS tcsd1

STATE Standby Conversion Standby Conversion

DRDY
tph1
SCLK(o) Hi-Z Hi-Z
tcd1 tdd1 tpl1 tfd2
SDATA(o) Hi-Z MSB MSB-1 LSB+1 LSB Hi-Z

STATE (CONV held high) Conversion1 Conversion2

Figure 3. Timing Relationships; SSC Mode (Not to Scale)

DRDY

CS
t csd2 t fd3
SDATA(o) Hi-Z MSB MSB-1 MSB-2
t dd2
SCLK(i)

DRDY

CS
t csd2
SDATA(o) Hi-Z MSB MSB-1 LSB+2 LSB+1 LSB

t dd2 t ph2 t fd4

SCLK(i)
t pl2

Figure 4. Timing Relationships; SEC Mode (Not to Scale)

DS59F4 11
 CS5505/6/7/8

RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Positive Digital VD+ 3.15 5.0 5.5 V
(VA+)-(VA-) Vdiff 4.5 10 11 V
Positive Analog VA+ 4.5 5.0 11 V
Negative Analog VA- 0 -5.0 -5.5 V
Analog Reference Voltage (Note 20) (VREF+)-(VREF-) 1.0 2.5 3.6 V
Analog Input Voltage: (Note 21)
Unipolar VAIN 0 - (VREF+)-(VREF-) V
Bipolar VAIN -((VREF+)-(VREF-)) - +((VREF+)-(VREF-)) V
Notes: 19. All voltages with respect to ground.
20. The CS5505/6/7/8 can be operated with a reference voltage as low as 100 mV; but with a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-.
21. The CS5505/6/7/8 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar
mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds
((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative than 0 Volts.
In bipolar mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds
((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative in magnitude than
-((VREF+)-(VREF-)).

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Min Typ Max Units
DC Power Supplies: Digital Ground (Note 22) DGND -0.3 - (VD+)-0.3 V
Positive Digital (Note 23) VD+ -0.3 - 6.0 or VA+ V
Positive Analog VA+ -0.3 - 12.0 V
Negative Analog VA- +0.3 - -6.0 V
(VA+)-(VA-) Vdiff1 -0.3 - 12.0 V
(VA+)-(VD+) Vdiff2 -0.3 - 12.0 V
Input Current, Any Pin Except Supplies (Notes 24, 25) Iin - - ±10 mA
Analog Input Voltage AIN and VREF pins VINA (VA-)-0.3 - (VA+)+0.3 V
Digital Input Voltage VIND -0.3 - (VD+)+0.3 V
Ambient Operating Temperature TA -55 - 125 °C
Storage Temperature T stg -65 - 150 °C
Notes: 22. No pin should go more positive than (VA+)+0.3V.
23. VD+ must always be less than (VA+)+0.3 V,and can never exceed 6.0V.
24. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.
25. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 mA.
* WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

12 DS59F4
 CS5505/6/7/8

GENERAL DESCRIPTION +5 on the digital. They can also operate with

dual polarity (+5 and -5), or from a single +5
The CS5505/6/7/8 are very low power mono- volt supply on the analog and + 3.3 on the digi-
lith ic CM OS A/D co nverters designed tal.
specifically for measurement of dc signals. The
CS5505/7 are 16-bit converters (a four channel
and a single channel version). The CS5506/8 are THEORY OF OPERATION FOR THE
20-bit converters (a four channel and a single CS5505/6/7/8
channel version). Each of the devices includes a
delta-sigma charge-balance converter, a voltage The front page of this data sheet illustrates the
reference, a calibration microcontroller with block diagram of the CS5505/6.
SRAM, a digital filter and a serial interface. The
CS5505 and CS5506 include a four channel Basic Converter Operation
pseudo-differential (all four channels have the
same reference measurement node) multiplexer. The CS5505/6/7/8 A/D converters have four op-
erating states. These are start-up, calibration,
The CS5505/6/7/8 include an on-chip reference conversion and sleep. When power is first ap-
but can also utilize an off-chip reference for pre- plied, the device enters the start-up state. The
cision applications. The CS5505/6/7/8 can be first step is a power-on reset delay of about
used to measure either unipolar or bipolar sig- 10 ms which resets all of the logic in the device.
nals. The devices use self-calibration to insure To proceed with start-up, the oscillator must
excellent offset and gain accuracy. then begin oscillating. After the power-on reset
the device enters the wake-up period for 1800
The CS5505/6/7/8 are optimized to operate from clock cycles after clock is present. This allows
a 32.768 kHz crystal but can be driven by an the delta-sigma modulator and other circuitry
external clock whose frequency is between (which are operating with very low currents) to
30 kHz and 163 kHz. When the digital filter is reach a stable bias condition prior to entering
operated with a 32.768 kHz clock, the filter has into either the calibration or conversion states.
zeros precisely at 50 and 60 Hz line frequencies During the 1800 cycle wake-up period, the de-
and multiples thereof. vice can accept an input command. Execution of
this command will not occur until the complete
The CS5505/6/7/8 use a "start convert" com- wake-up period elapses. If no command is given,
mand to latch the input channel selection and to the device enters the standby mode.
start a convolution cycle on the digital filter.
Once the filter cycle is completed, the output Calibration
port is updated. When operated with a
32.768 kHz clock the ADC converts and updates After the initial application of power, the
its output port at 20 samples/sec. The throughput CS5505/6/7/8 must enter the calibration state
rate per channel is the output update rate divided prior to performing accurate conversions. During
by th e number of channels being multi- calibration, the chip executes a two-step process.
plexed. The output port includes a serial The device first performs an offset calibration
interface with two modes of operation. and then follows this with a gain calibration.
The two calibration steps determine the zero ref-
The CS5505/6/7/8 can operate from dual polar- erence point and the full scale reference point of
ity power supplies (+5 and -5), from a single +5 the converter’s transfer function. From these
volt supply, or with +10 volts on the analog and points it calibrates the zero point and a gain
DS59F4 13
 CS5505/6/7/8

slope to be used to properly scale the output then high during calibration, the calibration cy-
digital codes when doing conversions. cle will continue as the conversion command is
disregarded. The states of A0, A1 and BP/UP
The calibration state is entered whenever the are not important during calibrations.
CAL and CONV pins are high at the same time.
The state of the CAL and CONV pins at power- If an "end of calibration" signal is desired, pulse
on and when coming out of sleep are recognized the CAL signal high while leaving the CONV
as commands, but will not be executed until the signal high continuously. Once the calibration is
end of the 1800 clock cycle wake-up period. completed, a conversion will be performed. At
Note that any time CONV transitions from low the end of the conversion, DRDY will fall to in-
to high, the multiplexer inputs A0 and A1 are dicate the first valid conversion after the
latched internal to the CS5505 and CS5506 de- calibration has been completed.
vices. These latched inputs select the analog
input channel which will be used once conver- See Understanding Converter Calibration for de-
sion commences. tails on how the converter calibrates its transfer
function.
If CAL and CONV become active (high) during
the 1800 clock cycle wake-up time, the con- Conversion
verter will wait until the wake-up period elapses
before executing the calibration. If the wake-up The conversion state can be entered at the end of
time has elapsed, the converter will be in the the calibration cycle, or whenever the converter
standby mode waiting for instruction and will is idle in the standby mode. If CONV is taken
enter the calibration cycle immediately. The cali- high to initiate a calibration cycle ( CAL also
bration lasts for 3246 clock cycles. Calibration high), and remains high until the calibration cy-
coefficients are then retained in the SRAM cle is completed (CAL is taken low after CONV
(static RAM) for use during conversion. transitions high), the converter will begin a con-
version upon completion of the calibration
At the end of the calibration cycle, the on-chip period. The device will perform a conversion on
microcontroller checks the logic state of the the input channel selected by the A0 and A1 in-
CONV signal. If the CONV input is low the de- puts when CONV transitioned high. Table 1
vice will enter the standby mode where it waits indicates the multiplexer channel selection truth
for further instruction. If the CONV signal is table for A0 and A1.
high at the end of the calibration cycle, the con-
verter will enter the conversion state and
perform a conversion on the input channel which A1 A0 Channel addressed
was selected when CONV transitioned from low 0 0 AIN1
to high. The CAL signal can be returned low 0 1 AIN2
any time after calibration is initiated. CONV can 1 0 AIN3
also be returned low, but it should never be 1 1 AIN4
taken low and then taken back high until the
calibration period has ended and the converter is Table 1. Multiplexer Truth Table
in the standby state. If CONV is taken low and
then high again with CAL high while the con- The A0 and A1 inputs are latched internal to the
verter is calibrating, the device will interrupt the 4-channel devices (CS5505/6) when CONV
current calibration cycle and start a new one. If rises. A0 and A1 have internal pull-down cir-
CAL is taken low and CONV is taken low and cuits which default the multiplexer to channel

14 DS59F4
 CS5505/6/7/8

AIN1. The BP/UP pin is not a latched input. The terminated and a new conversion will be initi-
BP/UP pin controls how the output word from ated.
the digital filter is processed. In bipolar mode
the output word computed by the digital filter is Voltage Reference
offset by 8000H in the 16-bit CS5505/7 or
80000H in 20-bit CS5506/8 (see Understanding The CS5505/6/7/8 uses a differential voltage ref-
Converter Calibration). BP/UP can be changed erence input. The positive input is VREF+ and
after a conversion is started as long as it is stable the negative input is VREF-. The voltage be-
for 82 clock cycles of the conversion period tween VREF+ and VREF- can range from 1 volt
prior to DRDY falling. If one wishes to intermix minimum to 3.6 volts maximum. The gain slope
measurement of bipolar and unipolar signals on will track changes in the reference without re-
various input channels, it is best to switch the calibration, accommodating ratiometric
BP/UP pin immediately after DRDY falls and applications.
leave BP/UP stable until DRDY falls again. If
the converter is beginning a conversion starting The CS5505/6/7/8 include an on-chip voltage
from the standby state, BP/UP can be changed at reference which outputs 2.5 volts on the VRE-
the same time as A0 and A1. FOUT pin. This voltage is referenced to the
VA+ pin and will track changes relative to VA+.
The digital filter in the CS5505/6/7/8 has a Fi- The VREFOUT output requires a 0.1 µF capaci-
nite Impulse Response and is designed to settle tor connected between VREFOUT and VA+ for
to full accuracy in one conversion time. There- stability. When using the internal reference, the
fore, the multiplexer can be changed at the VREFOUT signal should be connected to the
conversion rate. VREF- input and the VREF+ pin should be con-
nected to the VA+ supply. The internal voltage
If CONV is left high, the CS5505/6/7/8 will per- reference is capable of sourcing 3 µA maximum
form continuous conversions on one channel. and sinking 50 µA maximum. If a more precise
The conversion time will be 1622 clock cycles. reference voltage is required, an external voltage
If conversion is initiated from the standby state, reference should be used. If an external voltage
there may be up to two XIN clock cycles of un- reference is used, the VREFOUT pin of the in-
certainty as to when conversion actually begins. ternal reference should be connected directly to
This is because the internal logic operates at one VA-. It cannot be left open unless the 0.1 µF ca-
half the external clock rate and the exact phase pacitor is in place for stability.
of the internal clock may be 180° out of phase
relative to the XIN clock. When a new conver-
sion is initiated from the standby state, it will CS5505/6/7/8
take up to two XIN clock cycles to begin. Actual +VA VA+
conversion will use 1624 clock cycles before LT1019, 2.5V
DRDY goes low to indicate that the serial port REF43 VREF+
or
has been updated. See the Serial Interface Logic LM368
section of the data sheet for information on read- VREF-
ing data from the serial port. VREFOUT
-VA VA-
In the event the A/D conversion command
(CONV going positive) is issued during the con-
version state, the current conversion will be Figure 5. External Reference Connections

DS59F4 15
 CS5505/6/7/8

CS5505/6/7/8 ages for the A/D. The differential input voltage

+VA VA+ can also have any common mode value as long
VREF+ as the maximum signal magnitude stays within
0.1 µF
VREF- the supply voltages.
VREFOUT

-VA VA-
The A/D converter is intended to measure dc or
low frequency inputs. It is designed to yield ac-
curate conversions even with noise exceeding
Figure 6. Internal Reference Connections the input voltage range as long as the spectral
components of this noise will be filtered out by
External reference voltages can range from 1.0
the digital filter. For example, with a 3.0 volt
volt minimum to 3.6 volts maximum. The com-
reference in unipolar mode, the converter will
mon mode voltage range of the external
accurately convert an input dc signal up to
reference can allow the reference to lie at any
3.0 volts with up to 15% overrange for 60 Hz
voltage between the VA+ and VA- supply rails.
noise. A 3.0 volt dc signal could have a 60 Hz
Figures 5 and 6 illustrate how the CS5505/6/7/8
component which is 0.5 volts above the maxi-
converters are connected for external and for in-
mum input of 3.0 (3.5 volts peak; 3.0 volts dc
ternal voltage reference use, respectively.
plus 0.5 volts peak noise) and still accurately
convert the input signal (XIN = 32.768 kHz).
Analog Input Range
This assumes that the signal plus noise ampli-
tude stays within the supply voltages.
The analog input range is set by the magnitude
of the voltage between the VREF+ and VREF-
The CS5505/6/7/8 converters output data in bi-
pins. In unipolar mode the input range will equal
nary format when converting unipolar signals
the magnitude of the voltage reference. In bipo-
and in offset binary format when converting bi-
lar mode the input voltage range will equate to
polar signals. Table 2 outlines the output coding
plus and minus the magnitude of the voltage ref-
for the 16-bit CS5505/7 and the 20-bit CS5506/8
erence. While the voltage reference can be as
in both unipolar and bipolar measurement
great as 3.6 volts, its common mode voltage can
modes.
be any value as long as the reference inputs
VREF+ and VREF- stay within the supply volt-

CS5505 and CS5507 (16 Bit) CS5506 and CS5508 (20 Bit)
Unipolar Input Output Bipolar Input Unipolar Input Output Bipolar Input
Voltage Codes Voltage Voltage Codes Voltage
>(VREF - 1.5 LSB) FFFF >(VREF - 1.5 LSB) >(VREF - 1.5 LSB) FFFFF >(VREF - 1.5 LSB)
VREF - 1.5 LSB FFFF VREF - 1.5 LSB VREF - 1.5 LSB FFFFF VREF - 1.5 LSB
FFFE FFFFE
VREF/2 - 0.5 LSB 8000 -0.5 LSB VREF/2 - 0.5 LSB 80000 -0.5 LSB
7FFF 7FFFF
+0.5 LSB 0001 -VREF + 0.5 LSB +0.5 LSB 00001 -VREF + 0.5 LSB
0000 00000
<(+0.5 LSB) 0000 <(-VREF + 0.5 LSB) <(+0.5 LSB) 00000 <(-VREF + 0.5 LSB)
Note: VREF = (VREF+) - (VREF-); Table excludes common mode voltage on the signal and reference inputs.
Table 2. Output Coding

16 DS59F4
 CS5505/6/7/8

Understanding Converter Calibration 8000H (16-bit) or 80000H (20-bit) and multi-

plies the LSB size by two. This means that the
Calibration can be performed at any time. A bipolar measurement range is not calibrated from
calibration sequence will minimize offset errors full scale positive to full scale negative. Instead
and set the gain slope scale factor. The delta- it is calibrated from the bipolar zero scale point
sigma modulator in the converter is a differential to full scale positive. The slope factor is then
modulator. To calibrate out offset error, the extended below bipolar zero to accommodate the
converter internally connects the modulator dif- negative input signals. The converter can be
ferential inputs to an internal VREF- voltage and used to convert both unipolar and bipolar signals
measures the 1’s density output from the modu- by changing the BP/UP pin. Recalibration is not
lator. It stores the digital code representation for required when switching between unipolar and
this 1’s density in SRAM and remembers this bipolar modes.
code as being the zero scale point for the A/D
conversion. The converter then connects the Converter Performance
negative modulator differential input to the
VREF- input and the positive modulator differ- The CS5505/6/7/8 A/D converters have excellent
ential input to the VREF+ voltage. The 1’s linearity performance. Calibration minimizes the
density output from the modulator is then re- errors in offset and gain. The CS5505/7 devices
co rded. The converter uses the digital have no missing code performance to 16-bits.
representation of this 1’s density along with the The CS5506/8 devices have no missing code
digital code for the zero scale point and calcu- performance to 20-bits. Figure 7 illustrates the
lates a gain scale factor. The gain scale factor is DNL of the 16-bit CS5505. The converters
stored in SRAM and used for calculating the achieve Common Mode Rejection (CMR) at dc
proper output codes during conversions. of 105 dB typical, and CMR at 50 and 60 Hz of
120 dB typical.
The states of A0, A1 and BP/UP are ignored
during calibration but should remain stable The CS5505/6/7/8 can experience some drift as
throughout the calibration period to minimize temperature changes. The CS5505/6/7/8 use
noise. chopper-stabilized techniques to minimize drift.
Measurement errors due to offset or gain drift
When conversions are performed in unipolar can be eliminated at any time by recalibrating
mode or in bipolar mode, the converter uses the the converter.
same calibration factors to compute the digital
output code. The only difference is that in bipo-
lar mode the on-chip microcontroller offsets the
computed output word by a code value of
+1

+1/2
DNL (LSB)

-1/2

-1
0 32,768 65,535
Codes
Figure 7. CS5505 Differential Nonlinearity plot.

DS59F4 17
 CS5505/6/7/8

Analog Input Impedance Considerations Vmax occurs the instant the sample capacitor is
switched from the buffer output to the AIN pin.
The analog input of the CS5505/6/7/8 can be Prior to switching, AIN has an error estimated as
modeled as illustrated in Figure 8 (the model ig- being less than or equal to Ve. Vmax is equal to
nores the multiplexer switch resistance). the prior error (Ve) plus the additional error
Capacitors (15 pF each) are used to dynamically from the buffer offset. The estimate for Vmax is:
sample each of the inputs (AIN+ and AIN-).
Every half XIN cycle the switch alternately con- 15pF
Vmax = Ve + 100mV
nects the capacitor to the output of the buffer (15pF + CEXT )
and then directly to the AIN pin. Whenever the
sample capacitor is switched from the output of Where CEXT is the combination of any external
the buffer to the AIN pin, a small packet of or stray capacitance.
charge (a dynamic demand of current) is re-
quired from the input source to settle the voltage From the settling time equation, an equation for
of the sample capacitor to its final value. The the maximum acceptable source resistance is de-
voltage on the output of the buffer may differ up rived.
to 100 mV from the actual input voltage due to
the offset voltage of the buffer. Timing allows −1
one half of a XIN clock cycle for the voltage on Rsmax =
 Ve 
2XIN (15pF + CEXT ) ln  
 Ve + 15pF(100mv) 
the sample capacitor to settle to its final value.
The equation which defines the settling time is:  (15pF + CEXT ) 


Ve = Vmax e ⁄RC
−t

This equation assumes that the offset voltage of

Where Ve is the final settled value, Vmax is the the buffer is 100 mV, which is the worst case.
maximum error voltage value of the input signal, The value of Ve is the maximum error voltage
R is the value of the input source resistance, C is which is acceptable.
the 15 pF sample capacitor plus the value of any
stray or additional capacitance at the input pin. For a maximum error voltage (Ve) of 10 µV in
The value of t is equal to 1/(2XIN). the CS5505 (1/4LSB at 16-bits) and 600 nV in
the CS5506 (1/4LSB at 20-bits), the above equa-
tion indicates that when operating from a
32.768 kHz XIN, source resistances up to
CS5505/6/7/8
AIN+ 110 kΩ in the CS5505 or 84 kΩ in the CS5506
15 pF are acceptable in the absence of external capaci-
Vos < 100 mV + Internal
- tance (CEXT = 0). If higher input source
Bias
Voltage
resistances are desired the master clock rate can
AIN- 15 pF be reduced to yield a longer settling time.
Vos < 100 mV +
- The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input imped-
ance applies to the voltage reference inputs as
well.
Figure 8. Analog Input Model

18 DS59F4
 CS5505/6/7/8

Digital Filter Characteristics Figure 9 illustrates the filter attenuation from dc

to 260 Hz. At exactly 50, 60, 100, and 120 Hz
The digital filter in the CS5505/6/7/8 is the com- the filter provides over 120 dB of rejection. Ta-
bination of a comb filter and a low pass filter. ble 3 indicates the filter attenuation for each of
The comb filter has zeros in its transfer function the potential line interference frequencies when
which are optimally placed to reject line interfer- the converter is operating with a 32.768 kHz
ence frequencies (50 and 60 Hz and their clock. The converter yields excellent attenuation
multiples) when the CS5505/6/7/8 is clocked at of these interference frequencies even if the fun-
32.768 kHz. Figures 9, 10 and 11 illustrate the damental line frequency should vary ±1% from
magnitude and phase characteristics of the filter. its specified frequency. The -3 dB corner fre-
quency of the filter when operating from a
0 32.768 kHz clock is 17 Hz. Figure 11 illustrates
X1 = 32.768kHz
that the phase characteristics of the filter are pre-
-20
X2 = 163.00kHz cisely linear phase.
-40
Attenuation (dB)

Frequency Notch Frequency Minimum

-60 (Hz) Depth (Hz) Attenuation
(dB) (dB)
-80
50 125.6 50±1% 55.5
-100 60 126.7 60±1% 58.4
100 145.7 100±1% 62.2
-120
120 136.0 120±1% 68.4
-140 150 118.4 150±1% 74.9
XIN = 32.768 kHz 180 132.9 87.9
180±1%
-160
200 102.5 200±1% 94.0
X1 0 40 80 120 160 200 240
X2 0 198.97 397.95 596.92 795.10 993.87 1193.85
240 108.4 240±1% 104.4
Frequency (Hz)

Figure 9. Filter Magnitude Plot to 260 Hz Table 3. Filter Notch Attenuation (XIN = 32.768 kHz)

0 180

-20 Flatness 135

Frequency dB
1 -0.010 90
-40 2 -0.041
Phase (Degrees)
Attenuation (dB)

3 -0.093
45
4 -0.166
-60
5 -0.259
0
6 -0.374
-80 7 -0.510
8 -0.667 -45
-100 9 -0.846
10 -1.047 -90
XIN = 32.768 kHz
17 -3.093 XIN = 32.768 kHz
-120 -135

-140 -180
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
Frequency (Hz) Frequency (Hz)

Figure 10. Filter Magnitude Plot to 50 Hz Figure 11. Filter Phase Plot to 50 Hz

DS59F4 19
 CS5505/6/7/8

If the CS5505/6/7/8 is operated at a clock rate ponents should be removed by means of low-
other than 32.768 kHz, the filter characteristics, pass filtering prior to the A/D input to prevent
including the comb filter zeros, will scale with aliasing. Spectral components greater than one
the operating clock frequency. Therefore, opti- half the output word rate on the VREF inputs
mum rejection of line frequency interference will (VREF+ and VREF-) may also be aliased. Fil-
occur with the CS5505/6/7/8 running at tering of the reference voltage to remove these
32.768 kHz. The CS5505/6/7/8 can be used with spectral components from the reference voltage
external clock rates from 30 kHz to 163 kHz. is desirable.

Anti-Alias Considerations for Spectral Crystal Oscillator

Measurement Applications
The CS5505/6/7/8 is designed to be operated us-
Input frequencies greater than one half the out- ing a 32.768 kHz "tuning fork" type crystal. One
put word rate (CONV = 1) may be aliased by end of the crystal should be connected to the
the converter. To prevent this, input signals XIN input. The other end should be attached to
should be limited in frequency to no greater than XOUT. Short lead lengths should be used to
one half the output word rate of the converter minimize stray capacitance. Figure 12 illustrates
(when CONV =1). Frequencies close to the the gate oscillator, and a simplified version of
modulator sample rate (XIN/2) and multiples the control logic used on the chip.
thereof may also be aliased. If the signal source
includes spectral components above one half the Over the industrial temperature range (-40 to
output word rate (when CONV = 1) these com- +85 °C) the on-chip gate oscillator will oscillate

CS5505/6
Channel A0 A1
A0 D Q
1 0 0
CLK Input 2 0 1
Mux
3 1 0
Decoder
A1 D Q 4 1 1
CLK

CONV S Q Start
D Q
Conversion
CLK
R R

S Q D Q Start
CAL Calibration
CLK
10 MΩ R
Modulator
Q
Sample
T Clock
22.5 pF 15 pF
gm ~
~ 19 umho

XOUT XIN

XTL=32.768 kHz

Figure 12. Gate Oscillator and Control Logic

20 DS59F4
 CS5505/6/7/8

with other crystals in the range of 30 kHz to When new data is put into the port DRDY will
53 kHz. Over the military temperature range (- go low.
55 to +125 °C) the on-chip gate oscillator is
designed to work only with a 32.768 kHz crys- Data can be read from the serial port in either of
tal. The chip will operate with external clock two modes. The M/SLP pin determines which
frequencies from 30 kHz to 163 kHz over all serial mode is selected. Serial port mode selec-
temperature ranges. The 32.768 kHz crystal is tion is as follows:
normally specified as a time-keeping crystal with
tight specifications for both initial frequency and SSC (Synchronous Self-Clocking) mode;
for drift over temperature. To maintain excellent M/SLP = VD+, or SEC (Synchronous External
frequency stability, these crystals are specified Clocking) mode; M/SLP = DGND. Timing dia-
only over limited operating temperature ranges grams which illustrate the SSC and SEC timing
(i.e. -10 to +60 °C) by the manufacturers. Appli- are in the tables section of this data sheet.
cations of these crystals with the CS5505/6/7/8
do not require tight initial tolerance or low Synchronous Self-Clocking Mode
tempco drift. Therefore, a lower cost crystal with
looser initial tolerance and tempco will generally The serial port operates in the SSC mode when
be adequate for use with the CS5505/6/7/8 con- the M/SLP pin is connected to the VD+ pin on
verters. Also check with the manufacturer about the part. In SSC mode the CS5505/6/7/8 fur-
wide temperature range application of their nishes both the serial output data (SDATA) and
standard crystals. Generally, even those crystals the serial clock (SCLK). When the serial port is
specified for limited temperature range will op- updated at the end of a conversion, DRDY falls.
erate over much larger ranges if frequency If CS is low, the SDATA and SCLK pins will
stability over temperature is not a requirement. come out of the high impedance state two XIN
The frequency stability can be as bad as ±3000 clock cycles after DRDY falls. The MSB data
ppm over the operating temperature range and bit will be presented for two cycles of XIN
still be typically better than the line frequency clock. The SCLK signal will rise in the middle
(50 or 60 Hz) stability over cycle to cycle during of the MSB data bit. When SCLK then returns
the course of a day. There are crystals available low the (MSB - 1) bit will appear. Subsequent
for operation over the military temperature range data bits will be output on each falling edge of
(-55 to +125 °C). See the Appendix for suppliers SCLK until the LSB data bit is output. After the
of 32.768 kHz crystals. LSB data bit is output, the SCLK will fall at
which time both the SDATA and SCLK outputs
Serial Interface Logic will return to the high impedance output state.
DRDY will return high at this time.
The digital filter in the CS5505/6/7/8 takes 1624
clock cycles to compute an output word once a If CS is taken low after DRDY falls, the MSB
conversion begins. At the end of the conversion data bit will appear within two XIN clock cycles
cycle, the filter will attempt to update the serial after CS is taken low. CS need not be held low
port. Two clock cycles prior to the update for the entire data output. If CS is returned high
DRDY will go high. When DRDY goes high during a data bit the port will complete the out-
just prior to a port update it checks to see if the put of that bit and then go into the Hi-Z state.
port is either empty or unselected (CS = 1). If The port can be reselected any time prior to the
the port is empty or unselected, the digital filter completion of the next conversion (DRDY fall-
will update the port with a new output word. ing) to allow the remaining data bits to be
output.
DS59F4 21
 CS5505/6/7/8

Synchronous External-Clocking Mode converter must go through a wake-up sequence

prior to conversions being initiated. This wake-
The serial port operates in the SEC mode when up sequence includes the 10 msec. (typ.)
the M/SLP pin is connected to the DGND pin. power-on-reset delay, the start-up of the oscilla-
SDATA is the output pin for the serial data. tor (unless an external clock is used), and the
When CS goes low after new data becomes 1800 clock cycle wake-up delay after the clock
available (DRDY goes low), the SDATA pin begins. When coming out of the sleep condi-
comes out of Hi-Z with the MSB data bit pre- tion, the converter will latch the A0 and A1
sent. SCLK is the input pin for the serial clock inputs.
in the SEC mode. If the MSB data bit is on the
SDATA pin, the first rising edge of SCLK en- Figure 13 illustrates how to use a gate and resis-
ables the shifting mechanism. This allows the tors to bias the M/SLP pin into the SLEEP
falling edges of SCLK to shift subsequent data threshold region when using the converter in the
bits out of the port. Note that if the MSB data SSC mode. To use the SEC mode return resistor
bit is output and the SCLK signal is high, the R1 to DGND instead of the supply. When in
first falling edge of SCLK will be ignored be- the SEC mode configuration the CS5505/6/7/8
cause the shifting mechanism has not become will enter the SLEEP threshold when the logic
activated. After the first rising edge of SCLK, control input is a logic 1 (VD+). Note that large
each subsequent falling edge will shift out the resistors can be used to conserve power while in
serial data. Once the LSB is present, the falling sleep. The input leakage of the pin is typically
edge of SCLK will cause the SDATA output to less than 1 µA even at 125 °C, although the
go to Hi-Z and DRDY to return high. The serial worst case specification tables indicate a leakage
port register will be updated with a new data
word upon the completion of another conversion VD+ *
if the serial port has been emptied, or if the CS
is inactive (high). 1% R1**
CS5505/6/7/8
CS can be operated asynchronously to the R2
DRDY signal. The DRDY signal need not be Control
M/SLP
Input
monitored as long as the CS signal is taken low 499k 0.01µF
for at least two XIN clock cycles plus 200 ns ’1’ = SSC Mode 1%
prior to SCLK being toggled. This ensures that ’0’ = SLEEP
CS has gained control over the serial port. * Tie R to DGND for SEC mode; control input
1
logic inverts.
Sleep Mode
** R = 499k, V + = 5V; R = 590k, V + = 3.3V
1 D 1 D

The CS5505/6/7/8 devices offer two methods of Figure 13. Sleep Threshold Control
putting the device into a SLEEP condition to
conserve power. Calibration words will be re- of 10 µA maximum.
tained in SRAM during either sleep condition.
The M/SLP pin can be put into the SLEEP Power Supplies and Grounding
threshold to lower the operating power used by
the device to about 1% of nominal. Alternately, The analog and digital supply pins to the
the clock into the XIN pin can be stopped. This CS5505/6/7/8 are brought out on separate pins to
will lower the power consumed by the converter minimize noise coupling between the analog and
to about 30% of nominal. In both cases, the digital sections of the chip. Note that there is no
22 DS59F4
 CS5505/6/7/8

analog ground pin. No analog ground pin is re- VD+ or DGND pins; VD+ must remain more
quired because the inputs for measurement and positive than the DGND pin.
for the voltage reference are differential and re-
quire no ground. In the digital section of the The following power supply options are possi-
chip the supply current flows into the VD+ pin ble:
and out of the DGND pin. As a CMOS device,
the CS5505/6/7/8 requires that the supply volt- VA+ = +5V to +10V, VA- = 0V, VD+ = +5V
age on the VA+ pin always be more positive VA+ = +5V, VA- = -5V, VD+ = +5V
VA+ = +5V, VA- = 0V to -5V, VD+ = +3.3V
than the voltage on any other pin of the device.
If this requirement is not met, the device can
The CS5505/6/7/8 cannot be operated with a
latch-up or be damaged. In all circumstances the
3.3V digital supply if VA+ is greater than
VA+ voltage must remain more positive than the
+5.5V.
10Ω

+5V 0.1 µF 0.1 µF

Analog
17 20
Supply
VA+ VD+
Optional
5
XIN Clock
4 Source
Calibration 6
CAL
Control XOUT 32.768 kHz
Bipolar/
8 7 Sleep Mode
Unipolar BP/UP M/SLP
Input Select Control
and
CS5505/6 Output Mode
9 Select
AIN1+
Analog* 10
AIN2+ 21
Signal 12 SCLK Serial
AIN3+ Data
Sources 13
AIN4+ 22
SDATA Interface
Signal 11
AIN- 23
Ground *Unused analog inputs DRDY
should be tied to AIN- 2
14 CS
+ 1 Control
Voltage VREF+ A0 24 Logic
Reference 15 A1
- VREF- 3
CONV
16 19
VREFOUT DGND
VA- Unused Logic
inputs must be
18
connected to
VD+ or DGND.

Note: To use the internal 2.5 volt reference see Figure 6.

Figure 14. CS5505/6 System Connection Diagram Using External Reference, Single Supply

DS59F4 23
 CS5505/6/7/8

Figure 14 illustrates the System Connection Dia- Figure 16 illustrates the CS5505/6 using dual
gram for the CS5505/6 using a single +5V supplies of +10V analog and +5V digital.
supply. Note that all supply pins are bypassed
with 0.1 µF capacitors and that the VD+ digital When using separate supplies for VA+ and
supply is derived from the VA+ supply. VD+, VA+ must be established first. VD+
should never become more positive than VA+
Figure 15 illustrates the CS5505/6 using dual under any operating condition. Remember to in-
supplies of +5 and -5V. vestigate transient power-up conditions, when
one power supply may have a faster rise time.

10Ω

+5V 0.1 µF 0.1 µF

Analog
17 20
Supply
VA+ VD+
Optional
5
XIN Clock
4 Source
Calibration 6
CAL
Control XOUT 32.768 kHz
Bipolar/
8 7 Sleep Mode
Unipolar BP/UP M/SLP
Input Select Control
and
CS5505/6 Output Mode
9 Select
AIN1+
Analog* 10
AIN2+ 21
Signal 12 SCLK Serial
AIN3+ Data
Sources 13
AIN4+ 22
SDATA Interface
Signal 11
AIN- 23
Ground *Unused analog inputs DRDY
should be tied to AIN- 2
14 CS
+ 1 Control
Voltage VREF+ A0 24 Logic
Reference 15 A1
- VREF- 3
CONV
16 19
VREFOUT DGND
0.1 µF VA- Unused Logic
-5V
inputs must be
Analog 18
connected to
Supply
VD+ or DGND.

Note: To use the internal 2.5 volt reference see Figure 6.

Figure 15. CS5505/6 System Connection Diagram Using External Reference, Dual Supplies

24 DS59F4
 CS5505/6/7/8

+10V 0.1 µF 0.1 µF +5V

Analog Analog
17 (2) 20
Supply Supply
VA+ VD+
5 Optional
XIN Clock
Calibration 4 6 Source
CAL
Control XOUT
32.768 kHz
Bipolar/
8 7 Sleep Mode
Unipolar BP/UP M/SLP
Input Select Control
and
CS5505/6 Output Mode
9 Select
AIN1+
Analog* 10
AIN2+ 21
Signal 12 SCLK Serial
AIN3+ Data
Sources 13
AIN4+ 22
SDATA Interface
Signal 11
AIN- 23
Ground *Unused analog inputs DRDY
should be tied to AIN- 2
14 CS
+ 1 Control
Voltage VREF+ A0
(1) 24 Logic
Reference 15 A1
- VREF- 3
CONV
16 19
VREFOUT DGND
VA- Unused Logic
inputs must be
18
connected to
VD+ or DGND.

Note: (1) To use the internal 2.5 volt reference see Figure 6.
(2) VD+ must never exceed VA+. Examine power-up conditions.

Figure 16. CS5505/6 System Connection Diagram Using External Reference,

Dual Supply, +10V Analog, +5V Digital

Schematic & Layout Review Service

Confirm Optimum
Schematic & Layout
Before Building Your Board.

For Our Free Review Service

Call Applications Engineering.

C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2

DS59F4 25
 CS5505/6/7/8

PIN CONNECTIONS*
CS5505/6

MULTIPLEXER SELECTION INPUT A0 1 24 A1 MULTIPLEXER SELECTION INPUT

CHIP SELECT CS 2 23 DRDY DATA READY
CONVERT CONV 3 22 SDATA SERIAL DATA OUTPUT
CALIBRATE CAL 4 21 SCLK SERIAL CLOCK INPUT/OUTPUT
CRYSTAL IN XIN 5 20 VD+ POSITIVE DIGITAL POWER
CRYSTAL OUT XOUT 6 19 DGND DIGITAL GROUND
SERIAL MODE/ SLEEP M/SLP 7 18 VA- NEGATIVE ANALOG POWER
BIPOLAR/UNIPOLAR BP/UP 8 17 VA+ POSITIVE ANALOG POWER
DIFFERENTIAL ANALOG INPUT AIN1+ 9 16 VREFOUT VOLTAGE REFERENCE OUTPUT
DIFFERENTIAL ANALOG INPUT AIN2+ 10 15 VREF- VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG RETURN AIN- 11 14 VREF+ VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT AIN3+ 12 13 AIN4+ DIFFERENTIAL ANALOG INPUT

CS5507/8

1 20
CHIP SELECT CS DRDY DATA READY
CONVERT CONV 2 19 SDATA SERIAL DATA OUTPUT
CALIBRATE CAL 3 18 SCLK SERIAL CLOCK INPUT/OUTPUT
CRYSTAL IN XIN 4 17 VD+ POSITIVE DIGITAL POWER
CRYSTAL OUT XOUT 5 16 DGND DIGITAL GROUND
SERIAL MODE/ SLEEP M/SLP 6 15 VA- NEGATIVE ANALOG POWER
BIPOLAR/UNIPOLAR BP/UP 7 14 VA+ POSITIVE ANALOG POWER
DIFFERENTIAL ANALOG INPUT AIN+ 8 13 VREFOUT VOLTAGE REFERENCE OUTPUT
NO CONNECTION NC 9 12 VREF- VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT AIN- 10 11 VREF+ VOLTAGE REFERENCE INPUT

*Pinout applies to both DIP and SOIC

26 DS59F4
 CS5505/6/7/8

PIN DESCRIPTIONS

Pin numbers for four channel devices are in parentheses.

Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6).
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).

Serial Output I/O

M/SLP - Serial Interface Mode Select/ Sleep, Pin 6 (7).
Dual function pin which selects the operating mode of the serial port and provides a very low
power sleep function. When M/SLP is tied to the VD+ pin the serial port will operate in the
Synchronous Self-Clocking (SSC) mode. When M/SLP is tied to the DGND pin the serial port
will operate in the Synchronous External Clocking (SEC) mode. When the M/SLP pin is tied
half way between VD+ and DGND the chip will enter into a very low powered sleep mode in
which its calibration data will be maintained.

CS - Chip Select, Pin 1 (2).

This input allows an external device to access the serial port.

DRDY - Data Ready, Pin 20 (23)

Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).

SDATA - Serial Data Output, Pin 19 (22).

SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK and in a format determined by the M/SLP pin. Data is output MSB first
and advances to the next data bit on the falling edges of SCLK. SDATA will be in a high
impedance state when not transmitting data.

SCLK - Serial Clock Input/Output, Pin 18 (21).

A clock signal on this pin determines the output rate of the data from the SDATA pin. The
M/SLP pin determines whether SCLK is an input or and output. When used as an input, it must
not be allowed to float.

DS59F4 27
 CS5505/6/7/8

Control Input Pins

CAL - Calibrate, Pin 3 (4).
When taken high the same time that the CONV pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.

CONV - Convert, Pin 2 (3).

The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. CONV
latches the multiplexer selection when it transitions from low to high on the multiple channel
devices. If CONV is held high (CAL low) the converter will do continuous conversions.

A0, A1 - Multiplexer Selection Inputs, Pins (1, 24).

A0 and A1 select the input channel for conversion on the multi-channel input devices. A0 and
A1 are latched when CONV transitions from low to high. These two inputs have pull-down
resistors internal to the chip.

BP/UP - Bipolar/Unipolar, Pin 7 (8).

The BP/UP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.

Measurement and Reference Inputs

AIN+, AIN-, (AIN1+, AIN2+, AIN3+, AIN4+, AIN-) - Differential Analog Inputs, Pins 8, 10 (9,
10, 12, 13, 11).
AIN- in the CS5505/6 is a common measurement node for AIN1+, AIN2+, AIN3+ and AIN4+.

VREF+, VREF- - Differential Voltage Reference Inputs, Pins 11, 12 (14, 15).
A differential voltage reference on these pins operates as the voltage reference for the
converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts.

Voltage Reference
VREFOUT - Voltage Reference Output, Pin 13 (16).
The on-chip voltage reference is output from this pin. The voltage reference has a nominal
magnitude of 2.5 volts and is referenced to the VA+ pin on the converter.

Power Supply Connections

VA+ - Positive Analog Power, Pin 14 (17).
Positive analog supply voltage. Nominally +5 volts.

VA- - Negative Analog Power, Pin 15 (18).

Negative analog supply voltage. Nominally -5 volts when using dual polarity supplies; or 0
volts (tied to system analog ground) when using single supply operation.

28 DS59F4
 CS5505/6/7/8

VD+ - Positive Digital Power, Pin 17 (20).

Positive digital supply voltage. Nominally +5 volts or 3.3 volts.

DGND - Digital Ground, Pin 16 (19).

Digital Ground.

Other
NC - No Connection, Pin 9.
Pin should be left floating.

SPECIFICATION DEFINITIONS

Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the A/D
Converter transfer function. One endpoint is located 1/2 LSB below the first code transition
and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in
percent of full-scale.

Differential Nonlinearity
The deviation of a code’s width from the ideal width. Units in LSBs.

Full Scale Error

The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3⁄2 LSB].
Units are in LSBs.

Unipolar Offset
The deviation of the first code transition from the ideal (1⁄2 LSB above the voltage on the AIN-
pin.) when in unipolar mode (BP/UP low). Units are in LSBs.

Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1⁄2 LSB below
the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs

DS59F4 29
 CS5505/6/7/8

Ordering Guide
Model # of Resolution Linearity Temperature Package Type
Number Channels Error Range (°C)

CS5505-AP 4 16-Bits 0.0030% -40 to +85 24-pin 0.3" Plastic DIP

CS5505-AS 4 16-Bits 0.0030% -40 to +85 24-pin 0.3" SOIC

CS5506-BP 4 20-Bits 0.0015% -40 to +85 24-pin 0.3" Plastic DIP

CS5506-BS 4 20-Bits 0.0015% -40 to +85 24-pin 0.3" SOIC

CS5507-AP 1 16-Bits 0.0030% -40 to +85 20-pin 0.3" Plastic DIP

CS5507-AS 1 16-Bits 0.0030% -40 to +85 20-pin 0.3" SOIC
CS5507-SD 1 16-Bits 0.0030% -55 to +125 20-pin 0.3" CerDIP

CS5508-BP 1 20-Bits 0.0015% -40 to +85 20-pin 0.3" Plastic DIP

CS5508-BS 1 20-Bits 0.0015% -40 to +85 20-pin 0.3" SOIC
CS5508-SD 1 20-Bits 0.0030% -55 to +125 20-pin 0.3" CerDIP

30 DS59F4
 CS5505/6/7/8

APPENDIX

The following companies provide 32.768 kHz crystals in many package varieties and temperature
ranges.

Fox Electronics Taiwan X’tal Corp.

5570 Enterprise Parkway 5F. No. 16, Sec 2, Chung Yang S. RD.
Fort Meyers, FL 33905 Reitou, Taipei, Taiwan R. O. C.
(813) 693-0099 Tel: 02-894-1202
Fax: 02-895-6207
Micro Crystal Division / SMH
702 West Algonquin Road Interquip Limited
Arlington Heights, IL 60005 24/F Million Fortune Industrial Centre
(708) 806-1485 34-36 Chai Wan Kok Street, Tsuen Wan N T
Tel: 4135515
SaRonix Fax: 4137053
4010 Transport Street
Palo Alto, California 94303 S& T Enterprises, Ltd.
(415) 856-6900 Rm 404 Blk B
Sea View Estate
Statek North Point, Hong Kong
512 North Main Tel: 5784921
Orange, California 92668 Fax: 8073126
(714) 639-7810
Mr. Darren Mcleod
IQD Ltd. Hy-Q International Pty. Ltd.
North Street 12 Rosella Road,
Crewkerne FRANKSON, 3199
Somerset TA18 7AK Victoria, Australia
England Tel: 61-3-783 9611
01460 77155 Fax: 61-3-783 9703

Mr. Pierre Hersberger

Microcrystal/DIV. ETA S.A.
Schild-Rust-Strasse 17
Grenchen CH-2540
Switzerland
065 53 05 57

DS59F4 31
• Notes •
 CDB5505/6/7/8

Evaluation Board for CS5505/6/7/8 Series of ADC’s

Features Description
l Operation with on-board 32.768 kHz crystal The CDB5505/5506/5507/5508 is a circuit board de-
or off-board clock source signed to provide quick evaluation of the CS5505/6/7/8
l Jumper selectable: series of A/D converters. The board can be configured to
evaluate the CS5505/6/7/8 in either SSC (Synchronous
- SSC mode; SEC mode; Sleep Self-Clocking) or SEC (Synchronous External-Clocking)
l DIP Switch Selectable: serial port mode.
- BP/UP mode; A0, & A1 channel selection The board allows access to all of the digital interface pins
l On-board precision voltage reference of the CS5505/6/7/8 chip.
l Access to all digital control pins ORDERING INFORMATION
l On-board patch area CDB5505 Evaluation Board
CDB5506 Evaluation Board
CDB5507 Evaluation Board
CDB5508 Evaluation Board
I

AIN4+
B
CS5505/6/7/8 H
U
AIN3+ E
F
A
F
D
E
AIN2+ E
R
R
S
AIN1+

AIN- CLKIN

VREF

+5V GND -5V

Cirrus Logic, Inc.

Crystal Semiconductor Products Division Copyright  Cirrus Logic, Inc. 1998 MAR ‘95
P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
DS59DB2
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com 33
 CS5505/6/7/8

Introduction

The CDB5505/6/7/8 evaluation board provides a off-board reference if the connections (2A and
quick means of testing the CS5505/6/7/8 series 2B) to the bandgap IC are cut.
A/D converters. The CS5505/6/7/8 converters
require a minimal amount of external circuitry. Note that the pin-out of the CS5505/6/7/8 series
The evaluation board comes configured with the chips allows the 20-pin single channel devices to
A/D converter chip operating from a 32.768 kHz be plugged into the 24-pin, four channel foot-
crystal and with an off-chip precision 2.5 volt print. See Figure 2 which illustrates the footprint
reference. The board provides access to all of compatibility.
the digital interface pins of the CS5505/6/7/8
chip. Prior to powering up the board, select the serial
port operating mode with the appropriate jumper
The board is configured for operation from +5 on the M/SLP header. The device can be oper-
and -5 volt power supplies, but can be operated ated in either the SSC (Synchronous
from a single +5 volt supply if the -5V binding Self-Clocking) or the SEC (Synchronous Exter-
post is shorted to the GND binding post. nal Clocking) mode. See the device data sheet
for an explanation of these modes.

Evaluation Board Overview All of the control pins of the CS5505/6/7/8 are
available at the J1 header connector. Buffer ICs
The board provides a complete means of making U2 and U3 are used to buffer the converter for
the CS5505/6/7/8 A/D converter chip function. interface to off-board circuits. The buffers are
The user must provide a means of taking the used on the evaluation board only because the
output data from the board in serial format and exact loading and off-board circuitry is un-
using it in his system. known. Most applications will not require the
buffer ICs for proper operation.
Figure 1 illustrates the schematic for the board.
The board comes configured for the A/D con- To put the board in operation, select either bipo-
verter chip to operate from the 32.768 kHz lar or unipolar mode with DIP switch S2. Then
watch crystal. A BNC connector for an external press the CAL pushbutton after the board is
clock is provided on the board. To connect the powered up. This initiates calibration of the con-
external BNC source to the converter chip, a cir- verter which is required before measurements
cuit trace must be cut. Then a jumper must be can be taken.
inserted in the proper holes to connect the XIN
pin of the converter to the input line from the To select an input channel on the four channel
BNC. The BNC input is terminated with a 50Ω devices, use DIP switch S2 to select the inputs
resistor. Remove this resistor if driving from a
logic gate. See the schematic in Figure 1. A1 A0 Channel addressed
0 0 AIN1
The board comes with the A/D converter 0 1 AIN2
VREF+ and VREF- pins hard-wired to the 1 0 AIN3
2.5 volt bandgap voltage reference IC on the
1 1 AIN4
board. The VREF+ and VREF- pins can be con-
nected to either the on chip reference or an
Table 1. Multiplexer Truth Table

34 DS59DB2
DS59DB2

R22 +5
+5
10 + C16 +5
10 µF
CAL DRDY
R9 VD+
+5 SCLK
+5V +5 C7 C10
0.1 µF 10 C11 R11 SDATA
C2 C5 0.1 µF 0.01 µF 100k
D1 + AGND
17 20 J2
6.8V 10 µF 0.1 µF R10 20k
GND DGND VA+ VD+ CAL
C6
+ C3 C4 CAL 4
0.1 µF 16 C17 VD+ R17
D2 10 µF 0.1 µF VREFOUT
R27 TP10 VD+ CONV
6.8V 0.1 µF 1 3 47k
-5V -5 1A 1K 14 CONV 3 U2A
C19 VREF+ 2
R26 TP9 CS
10nF
1B 1K 15
VREF- CS 2 4
U2B
5
C20 VD+ R18
10nF TP8 R19 A0
2 6 2A
+5 LT1019 A0 1 6 7 100k 47k
U2C
C9 -2.5 V 5 R8 C8 0.1 µF U1 VD+
25k 2B TP7 R20 A1
0.1 µF 4 CS5505
CS5506 A1 24 10
U2D
9 100k
3A
+ CS5507 TP11 DRDY
External
VREF _ OR DRDY 23 11
U2E
12
3B
CS5508 R23
TP12 100k SDATA
TP3
402 13 SDATA 22 14
U2F
15
AIN4+ AIN4+
R24 8 SCLKO
R28 R7 TP13 100k
TP4
100k 402 SCLK 21 5 U3B 6
12 AIN3+ VD+ 0.1 µF
AIN3+ R25 4
R6 100k VD+ SCLKI
R29 14
100k TP5 2 C18
402 10 U3A
3 R1
AIN2+ AIN2+ R16 100k BP/UP
R5 TP14 1
R30 11 100k
TP6 BP/UP 8 12
100k 402 U3D
9
AIN1+ AIN1+ 13 J1
R31 R4
TP15 R15 R21 7 VD+ U2 74HC4050
100k 402 C12 C13 C14 C15 7
11 M/SLP VD+ U3C U3 74HC125
AIN- AIN- 100k 47k 8 9 S2
R13 R14
0.01 µF 0.01 µF 0.01 µF 0.01 µF 100k 10 A1
R12 100k
A0
VA- XIN XOUT DGND
R3 SLEEP CONV
50 18 5 6 19
-5 SSC BP/UP
CLKIN Y1 SEC
C1

CS5505/6/7/8
R2 0.1 µF 32.768
200 kHz

Figure 1. ADC Connections

35
 CS5505/6/7/8

A0 1 CS5505/6 24 A1
CS 2/1 20/23 DRDY
CS5507/8
CONV 3/2 19/22 SDATA
CAL 4/3 18/21 SCLK
XIN 5/4 17/20 VD+
XOUT 6/5 16/19 DGND
M/SLP 7/6 15/18 VA-
BU/UP 8/7 14/17 VA+
AIN1+ 9/8 13/16 VREFOUT
AIN2+/NC 10/9 12/15 VREF-
AIN- 11/10 11/14 VREF+
AIN3+ 12 13 AIN4+

Figure 2. CS5505/6 and CS5507/8 Pin Layouts

for A0 and A1 (see Table 1). Once A0 and A1

are selected, the CONV switch (S2-3) must be
switched on (closed) and then open to cause the
CONV signal to transition low to high. This
latches the A0 and A1 channel selection into the
converter. With CONV high (S2-3 open) the
converter will convert continuously.

Figures 3 and 4 illustrate the evaluation board

layout while Figure 5 illustrates the component
placement (silkscreen) of the evaluation board.

36 DS59DB2
 CS5505/6/7/8

Figure 3. Top Ground Plane Layer (NOT TO SCALE)

DS59DB2 37
 CS5505/6/7/8

Figure 4. Bottom Trace Layer (NOT TO SCALE)

38 DS59DB2
 CS5505/6/7/8

Figure 5. Silk Screen Layer (NOT TO SCALE)

DS59DB2 39