DPSD - 2
DPSD - 2
DPSD - 2
INTRODUCTION:
The digital system consists of two types of circuits, namely
(i) Combinational circuits
(ii) Sequential circuits
Sequential logic circuit comprises both logic gates and the state of storage
elements such as flip-flops. As a consequence, the output of a sequential circuit depends
not only on present value of inputs but also on the past state of inputs.
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In the previous chapter, we have discussed binary numbers, codes, Boolean
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algebra and simplification of Boolean function and logic gates. In this chapter,
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formulation and analysis of various systematic designs of combinational circuits will be
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discussed.
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variables. The logic gates accept signals from inputs and output signals are generated
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according to the logic circuits employed in it. Binary information from the given data
transforms to desired output data in this process. Both input and output are obviously
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the binary signals, i.e., both the input and output signals are of two possible states, logic
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1 and logic 0.
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The following guidelines should be followed while choosing the preferred form for
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hardware implementation:
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1. The implementation should have the minimum number of gates, with the gates
used having the minimum number of inputs. S.
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2. There should be a minimum number of interconnections.
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In this section, we will discuss those combinational logic building blocks that can
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Half-Adder:
A half-adder is a combinational circuit that can be used to add two binary bits. It
has two inputs that represent the two bits to be added and two outputs, with one
producing the SUM output and the other producing the CARRY.
Inputs Outputs
A B Carry (C) Sum (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Truth table of half-adder
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K-map simplification for carry and sum:
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The Boolean expressions for the SUM and CARRY outputs are given by the
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equations,
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Block schematic of full-adder
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The full adder circuit overcomes the limitation of the half-adder, which can be
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used to add two bits only. As there are three input variables, eight different input
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Truth Table:
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Inputs Outputs
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0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
To derive the simplified Boolean expression from the truth table, the Karnaugh map
method is adopted as,
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C
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The logic diagram of the full adder can also be implemented with two half-
adders and one OR gate. The S output from the second half adder is the exclusive-OR of
Cin and the output of the first half-adder, giving
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C
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Implementation of full adder with two half-adders and an OR gate
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C
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Half -Subtractor:
A half-subtractor is a combinational circuit that can be used to subtract one binary
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digit from another to produce a DIFFERENCE output and a BORROW output. The
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BORROW output here specifies whether a ‗1‘ has been borrowed to perform the
subtraction.
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The truth table of half-subtractor, showing all possible input combinations and
the corresponding outputs are shown below.
Input Output
A B Difference (D) Borrow (Bout)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
The Boolean expressions for the DIFFERENCE and BORROW outputs are given
by the equations,
Difference, D = A’B+ AB’= A B
Borrow, Bout = A’ . B
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gate, the expression for the BORROW output (Bout) is that of an AND gate with input A
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complemented before it is fed to the gate.
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The logic diagram of the half adder is, S.
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K-map simplification for full-subtractor:
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EN
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The Boolean expressions for the DIFFERENCE and BORROW outputs are given
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by the equations,
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The logic diagram of the full-subtractor can also be implemented with two half-
subtractors and one OR gate. The difference,D output from the second half subtractor is
the exclusive-OR of Bin and the output of the first half-subtractor, giving
Difference,D= Bin (A B) [x y = x‘y+ xy‘]
= Bin (A‘B+AB‘)
= B‘in (A‘B+AB‘) + Bin (A‘B+AB‘)‘ [(x‘y+xy‘)‘= (xy+x‘y‘)]
= B‘in (A‘B+AB‘) + Bin (AB+A‘B‘)
= A‘BB‘in + AB‘B‘in + ABBin + A‘B‘Bin .
and the borrow output is,
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= A‘B+ ABBin+ A‘B‘Bin
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= A‘B (Bin+1) + ABBin+ A‘B‘Bin [Cin+1= 1]
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= A‘BBin+ A‘B+ ABBin+ A‘B‘Bin S.
= A‘B+ BBin (A+A‘) + A‘B‘Bin [A+A‘= 1]
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Therefore,
we can implement full-subtractor using two half-subtractors and OR gate as,
Since all the bits of augend and addend are fed into the adder circuits
simultaneously and the additions in each position are taking place at the same time, this
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circuit is known as parallel adder.
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Let the 4-bit words to be added be represented by,
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A3A2A1A0= 1111 and B3B2B1B0= 0011.
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EN
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The bits are added with full adders, starting from the least significant position, to
form the sum it and carry bit. The input carry C0 in the least significant position must be
0. The carry output of the lower order stage is connected to the carry input of the next
higher order stage. Hence this type of adder is called ripple-carry adder.
In the least significant stage, A0, B0 and C0 (which is 0) are added resulting in
sum S0 and carry C1. This carry C1 becomes the carry input to the second stage.
Similarly in the second stage, A1, B1 and C1 are added resulting in sum S1 and carry C2,
in the third stage, A2, B2 and C2 are added resulting in sum S2 and carry C3, in the third
stage, A3, B3 and C3 are added resulting in sum S3 and C4, which is the output carry.
Thus the circuit results in a sum (S3S2S1S0) and a carry output (Cout).
Though the parallel binary adder is said to generate its output immediately after
the inputs are applied, its speed of operation is limited by the carry propagation delay
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correct result until LSB carry has propagated through the intermediate full-adders. This
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represents a time delay that depends on the propagation delay produced in an each
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full-adder. For example, if each full adder is considered to have a propagation delay of
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30nsec, then S3 will not react its correct value until 90 nsec after LSB is generated.
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Consider the circuit of the full-adder shown above. Here we define two
functions: carry generate (Gi) and carry propagate (Pi) as,
Carry generate, Gi = Ai Bi
Carry propagate, Pi = Ai Bi
the output sum and carry can be expressed as,
Si = Pi Ci
Ci+1 = Gi PiCi
Gi (carry generate), it produces a carry 1 when both Ai and Bi are 1, regardless of the
input carry Ci.
Pi (carry propagate) because it is the term associated with the propagation of the carry
from Ci to Ci+1.
The Boolean functions for the carry outputs of each stage and substitute for each
Ci its value from the previous equation:
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C0= input carry
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C1= G0 + P0C0
C2= G1 + P1C1 = G1 + P1 (G0 + P0C0)
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= G1 + P1G0 + P1P0C0
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Since the Boolean function for each output carry is expressed in sum of products,
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each function can be implemented with one level of AND gates followed by an OR gate.
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The three Boolean functions for C1, C2 and C3 are implemented in the carry look-ahead
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generator as shown below. Note that C3 does not have to wait for C2 and C1 to
propagate; in fact C3 is propagated at the same time as C1 and C2.
Logic diagram of Carry Look-ahead Generator
Using a Look-ahead Generator we can easily construct a 4-bit parallel adder with
a Look-ahead carry scheme. Each sum output requires two exclusive-OR gates. The
output of the first exclusive-OR gate generates the Pi variable, and the AND gate
generates the Gi variable. The carries are propagated through the carry look-ahead
generator and applied as inputs to the second exclusive-OR gate. All output carries are
generated after a delay through two levels of gates. Thus, outputs S 1 through S3 have
equal propagation delay times.
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4-bit Parallel Subtractor
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Parallel Adder/ Subtractor:
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The addition and subtraction operation can be combined into one circuit with
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one common binary adder. This is done by including an exclusive-OR gate with each
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The mode input M controls the operation. When M= 0, the circuit is an adder and
when M=1, the circuit becomes a Subtractor. Each exclusive-OR gate receives input M
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columns under the binary sum list the binary values that appear in the outputs of the 4-
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bit binary adder. The output sum of the two decimal digits must be represented in BCD.
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Binary Sum BCD Sum
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Decimal
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K Z8 Z4 Z2 Z1 C S8 S4 S2 S1
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0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 1 0 0 0 0 1 1
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0 0 0 1 0 0 0 0 1 0 2
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0 0 0 1 1 0 0 0 1 1 3
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0 0 1 0 0 0 0 1 0 0 4
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0 0 1 0 1 0 0 1 0 1 5
0 0 1 1 0 0 0 1 1 0 6
0 0 1 1 1 0 0 1 1 1 7
0 1 0 0 0 0 1 0 0 0 8
0 1 0 0 1 0 1 0 0 1 9
In examining the contents of the table, it is apparent that when the binary sum is
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equal to or less than 1001, the corresponding BCD number is identical, and therefore no
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conversion is needed. When the binary sum is greater than 9 (1001), we obtain a non-
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valid BCD representation. The addition of binary 6 (0110) to the binary sum converts it
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to the correct BCD representation and also produces an output carry as required.
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The logic circuit to detect sum greater than 9 can be determined by simplifying
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The two decimal digits, together with the input carry, are first added in the top4-
bit binary adder to provide the binary sum. When the output carry is equal to zero,
nothing is added to the binary sum. When it is equal to one, binary 0110 is added to
the binary sum through the bottom 4-bit adder. The output carry generated from the
bottom adder can be ignored, since it supplies information already available at the
output carry terminal. The output carry from one stage must be connected to the
input carry of the next higher-order stage.
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Binary Multiplier:
Multiplication of binary numbers is performed in the same way as in decimal
numbers. The multiplicand is multiplied by each bit of the multiplier starting from the
least significant bit. Each such multiplication forms a partial product. Such partial
The second partial product is formed by multiplying A1 by B1B0 and shifted one
position to the left. The two partial products are added with two half adder (HA)
circuits.
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Usually there are more bits in the partial products and it is necessary to use full
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adders to produce the sum of the partial products. The least significant bit of the
product does not have to go through an adder since it is formed by the output of the
first AND gate.
A combinational circuit binary multiplier with more bits can be constructed in a
similar fashion. A bit of the multiplier is ANDed with each bit of the multiplicand in as
many levels as there are bits in the multiplier. The binary output in each level of AND
gates are added with the partial product of the previous level to form a new partial
product. The last level produces the product. For J multiplier bits and K multiplicand
bits we need (J x K) AND gates and (J-1) k-bit adders to produce a product of J+K bits.
Consider a multiplier circuit that multiplies a binary number of four bits by a
number of three bits. Let the multiplicand be represented by B3, B2, B1, B0 and the
multiplier by A2, A1, and A0. Since K= 4 and J= 3, we need 12 AND gates and two 4-bit
adders to produce a product of seven bits. The logic diagram of the multiplier is shown
below.
Parity Generator:
A parity generator is a combination logic system to generate the parity bit at the
transmitting side. A table illustrates even parity as well as odd parity for a message
consisting of three bits.
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0 1 1 1 0
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1 0 0 0 1
1 0 1 1 S. 0
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1 1 0 1 0
C
1 1 1 0 1
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If the message bit combination is designated as A, B, C and Pe, Po are the even
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and odd parity respectively, then it is obvious from table that the boolean expressions
of even parity and odd parity are
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Pe = ABC) and
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Po = (ABC)′.
K-map Simplification:
Parity Checker:
The message bits with the parity bit are transmitted to their destination, where
they are applied to a parity checker circuit. The circuit that checks the parity at the
receiver side is called the parity checker. The parity checker circuit produces a check bit
and is very similar to the parity generator circuit. If the check bit is 1, then it is assumed
that the received data is incorrect. The check bit will be 0 if the received data is correct.
The table shows the truth table for the even parity checker.
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4-Bit Received Parity Error
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A B C D Check (PEC)
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0 0 0 0 S. 0
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0 0 0 1 1
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0 0 1 0 1
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0 0 1 1 0
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0 1 0 0 1
0 1 0 1 0
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0 1 1 0 0
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0 1 1 1 1
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1 0 0 0 1
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1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
PEC= A’B’ (C’D+ CD’) + A’B (C’D’+ CD) + AB (C’D+ CD’) + AB’ (C’D’+ CD)
= A’B’ (CD) + A’B (CD)’ + AB (CD) + AB’ (CD)’
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= (A’B’+ AB) (CD) + (A’B+ AB’) (CD)’
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= (AB)’ (CD) + (AB) (CD)’
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= (AB) (CD)
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Logic Diagram:
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EN
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MAGNITUDE COMPARATOR:
Inputs Outputs
A3 A2 A1 A0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
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0 1 0 1 0 1 0
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0 1 1 0 0 0 1
0 1 1 1 S. 0 0 1
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1 0 0 0 1 0 0
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1 0 0 1 1 0 0
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1 0 1 0 0 1 0
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1 0 1 1 0 0 1
1 1 0 0 1 0 0
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1 1 0 1 1 0 0
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1 1 1 0 1 0 0
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1 1 1 1 0 1 0
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K-map Simplification:
Logic Diagram:
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A = A3A2A1A0
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B = B3 B2 B1 B0,
Each subscripted letter represents one of the digits in the number. It is observed from
the bit contents of two numbers that A = B when A3 = B3, A2 = B2, A1 = B1 and A0 = B0.
When the numbers are binary they possess the value of either 1 or 0, the equality
relation of each pair can be expressed logically by the equivalence function as
Xi = AiBi + Ai′Bi′ for i = 1, 2, 3, 4.
Or, Xi = (A B)′. or, Xi ′ = A B
Or, Xi = (AiBi′ + Ai′Bi)′.
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functions,
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(A>B) = A3B3′ +X3A2B2′ +X3X2A1B1′ +X3X2X1A0B0′
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(A<B) = A3′B3 +X3A2′B2 +X3X2A1′B1 +X3X2X1A0′B0
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The symbols (A>B) and (A<B) are binary output variables that are equal to 1 when A>B
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or A<B, respectively.
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The gate implementation of the three output variables just derived is simpler
than it seems because it involves a certain amount of repetition. The unequal outputs
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can use the same gates that are needed to generate the equal output. The logic diagram
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The four x outputs are generated with exclusive-NOR circuits and applied to an
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AND gate to give the binary output variable (A=B). The other two outputs use the x
variables to generate the Boolean functions listed above. This is a multilevel
implementation and has a regular pattern.
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The gray code is often used in digital systems because it has the advantage that
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only one bit in the numerical representation changes between successive numbers. The
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truth table for the binary-to-gray code converter is shown below,
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Truth table:
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B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
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1 0 0 0 1 0 0 0 1
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2 0 0 1 0 0 0 1 1
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3 0 0 1 1 0 0 1 0
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4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
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EN
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Now, the above expressions can be implemented using EX-OR gates as,
Truth table:
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Gray code Binary code
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G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0S. 0 0 0
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0 0 0 1 0 0 0 1
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0 0 1 0 0 0 1 1
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0 0 1 1 0 0 1 0
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0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
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0 1 1 0 0 1 0 0
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0 1 1 1 0 1 0 1
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1 0 0 0 1 1 1 1
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1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
From the truth table, the logic expression for the binary code outputs can be written as,
G3= ∑m (8, 9, 10, 11, 12, 13, 14, 15)
G2= ∑m (4, 5, 6, 7, 8, 9, 10, 11)
G1= ∑m (2, 3, 4, 5, 8, 9, 14, 15)
G0= ∑m (1, 2, 4, 7, 8, 11, 13, 14)
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B3= G3
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from the natural BCD code by adding 3 to each coded number.
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For example, decimal 12 can be represented in BCD as 0001 0010. Now adding 3 to each
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digit we get excess-3 code as 0100 0101 (12 in decimal). With this information the truth
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table for BCD to Excess-3 code converter can be determined as,
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Truth Table:
BCD code Excess-3 code
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Decimal
B3 B2 B1 B0 E3 E2 E1 E0
EN
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
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2 0 0 1 0 0 1 0 1
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3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
From the truth table, the logic expression for the Excess-3 code outputs can be written
as,
E3= ∑m (5, 6, 7, 8, 9) + ∑d (10, 11, 12, 13, 14, 15)
E2= ∑m (1, 2, 3, 4, 9) + ∑d (10, 11, 12, 13, 14, 15)
E1= ∑m (0, 3, 4, 7, 8) + ∑d (10, 11, 12, 13, 14, 15)
E0= ∑m (0, 2, 4, 6, 8) + ∑d (10, 11, 12, 13, 14, 15)
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Truth table:
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E3 E2 E1 E0 B3 B2 B1 B0
3 0 0 1 1 0 0 0 0
4 0 1 0 0 0 0 0 1
5 0 1 0 1 0 0 1 0
6 0 1 1 0 0 0 1 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 0 1 0 1
9 1 0 0 1 0 1 1 0
10 1 0 1 0 0 1 1 1
11 1 0 1 1 1 0 0 0
12 1 1 0 0 1 0 0 1
K-map Simplification:
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EN
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Now, the above expressions the logic diagram can be implemented as,
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EN
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The left-most four-bit group represents 10 and right-most four-bit group represents 9.
The binary representation for decimal 19 is 1910 = 110012.
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1 0 0 1 1 0 1 1 0 1
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1 0 1 0 0 0 1 1 1 0
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1 0 1 0 1 0 1 1 1 1
1 0 1 1 0 1
S. 0 0 0 0
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1 0 1 1 1 1 0 0 0 1
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1 1 0 0 0 1 0 0 1 0
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1 1 0 0 1 1 0 0 1 1
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EN
K-map Simplification:
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A= B0
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B= B1B4‘+ B1’B4
= B1B4
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E= B4B3 + B4B2B1
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Now, from the above expressions the logic diagram can be implemented as,
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Logic Diagram:
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10 1 0 1 0 1 0 0 0 0
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11 1 0 1 1 1 0 0 0 1
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12 1 1 0 0 1
S. 0 0 1 0
13 1 1 0 1 1 0 0 1 1
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14 1 1 1 0 1 0 1 0 0
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15 1 1 1 1 1 0 1 0 1
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From the truth table, the logic expression for the BCD code outputs can be written as,
B0= ∑m (1, 3, 5, 7, 9, 11, 13, 15)
EN
B3= ∑m (8, 9)
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K-map Simplification:
From the above K-map, the logical expression can be obtained as,
EN
B0 = A
D
B2= D’C+ CB
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B3= DC’B’
B4= DC+ DB
Now, from the above expressions the logic diagram can be implemented as,
Logic Diagram:
The truth table for gray to BCD converter can be written as,
Truth Table:
Gray Code BCD Code
G3 G2 G1 G0 B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1
0 0 1 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 1 1 0 0 0 1 0 0
0 1 1 1 0 0 1 0 1
0 1 0 1 0 0 1 1 0
0 1 0 0 0 0 1 1 1
1 1 0 0 0 1 0 0 0
K-map Simplification:
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B4= G3G’2+ G3G1
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Now, from the above expressions the logic diagram can be implemented as,
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Logic Diagram:
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EN
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K-map Simplification:
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C
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EN
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Now, from the above expressions the logic diagram can be implemented as,
Logic Diagram:
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Truth Table:
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Gray Code S. BCD Code
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D C B A B4 B3 B2 B1 B0
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0 0 0 0 0 0 0 0 0
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0 1 1 1 0 0 0 0 1
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0 1 1 0 0 0 0 1 0
0 1 0 1 0 0 0 1 1
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0 1 0 0 0 0 1 0 0
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1 0 1 1 0 0 1 0 1
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1 0 1 0 0 0 1 1 0
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1 0 0 1 0 0 1 1 1
1 0 0 0 0 1 0 0 0
1 1 1 1 0 1 0 0 1
1 1 1 0 1 0 0 0 0
1 1 0 1 1 0 0 0 1
1 1 0 0 1 0 0 1 0
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C
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EN
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From the above K-map, the logical expression can be obtained as,
Logic Diagram:
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EN
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enable inputs to activate decoded output based on data inputs. When any one enable
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input is unasserted, all outputs of decoder are disabled.
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Binary Decoder (2 to 4 decoder):
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A binary decoder has ‗n‘ bit binary input and a one activated output out of 2n
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Here the 2 inputs are decoded into 4 outputs, each output representing one of the
minterms of the two input variables.
Inputs Outputs
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
As shown in the truth table, if enable input is 1 (EN= 1) only one of the outputs
(Y0 – Y3), is active for a given input.
The output Y0 is active, ie., Y0= 1 when inputs A= B= 0,
Y1 is active when inputs, A= 0 and B= 1,
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Y2 is active, when input A= 1 and B= 0,
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Y3 is active, when inputs A= B= 1.
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A 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y 0- Y7). Based
on the 3 inputs one of the eight outputs is selected.
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The three inputs are decoded into eight outputs, each output representing one of
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the minterms of the 3-input variables. This decoder is used for binary-to-octal
conversion. The input variables may represent a binary number and the outputs will
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represent the eight digits in the octal number system. The output variables are mutually
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exclusive because only one output can be equal to 1 at any one time. The output line
whose value is equal to 1 represents the minterm equivalent of the binary number
presently available in the input lines.
Inputs Outputs
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
0 a, b, c, d, e, f
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C
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1 b, c
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C
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2 a, b, d, e, g
EN
D
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3 a, b, c, d, g
4 b, c, f, g
5 a, c, d, f, g
7 a, b, c
8 a, b, c, d, e, f, g
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9 a, b, c, d, f, g
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C
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Truth table:
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Digit A B C D a b c d e f g
EN
0 0 0 0 0 1 1 1 1 1 1 0
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1 0 0 0 1 0 1 1 0 0 0 0
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2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
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O
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S.
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C
FO
TS
EN
D
U
ST
M
O
C
S.
U
C
FO
TS
EN
D
U
ST
Applications of decoders:
1. Decoders are used in counter system.
2. They are used in analog to digital converter.
3. Decoder outputs can be used to drive a display system.
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It has 2n input lines, only one which 1 is active at any time and ‗n‘ output lines. It
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encodes one of the active inputs to a coded binary output with ‗n‘ bits. In an encoder,
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the number of outputs is less than the number of inputs.
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Octal-to-Binary Encoder:
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It has eight inputs (one for each of the octal digits) and the three outputs that
generate the corresponding binary number. It is assumed that only one input has a
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Inputs Outputs
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D0 D1 D2 D3 D4 D5 D6 D7 A B C
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1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
The encoder can be implemented with OR gates whose inputs are determined
directly from the truth table. Output z is equal to 1, when the input octal digit is 1 or 3
or 5 or 7. Output y is 1 for octal digits 2, 3, 6, or 7 and the output is 1 for digits 4, 5, 6 or
7. These conditions can be expressed by the following output Boolean functions:
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FO
TS
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Octal-to-Binary Encoder
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Another problem in the octal-to-binary encoder is that an output with all 0‘s is
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generated when all the inputs are 0; this output is same as when D0 is equal to 1. The
discrepancy can be resolved by providing one more output to indicate that atleast one
input is equal to 1.
Priority Encoder:
A priority encoder is an encoder circuit that includes the priority function. In
priority encoder, if two or more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence.
In addition to the two outputs x and y, the circuit has a third output, V (valid bit
indicator). It is set to 1 when one or more inputs are equal to 1. If all inputs are 0, there
is no valid input and V is equal to 0.
Truth table:
Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
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x x x 1 1 1 1
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Although the above table has only five rows, when each don‘t care condition is
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S.
replaced first by 0 and then by 1, we obtain all 16 possible input combinations. For
example, the third row in the table with X100 represents minterms 0100 and 1100. The
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Inputs Outputs
EN
D0 D1 D2 D3 x y V
D
0 0 0 0 x x 0
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1 0 0 0 0 0 1
ST
0 1 0 0
0 1 1
1 1 0 0
0 0 1 0
0 1 1 0
1 0 1
1 0 1 0
1 1 1 0
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
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C
FO
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EN
A multiplexer or MUX, is a combinational circuit with more than one input line,
one output line and more than one selection line. A multiplexer selects binary
information present from one of many input lines, depending upon the logic status of
the selection inputs, and routes it to the output line. Normally, there are 2 n input lines
and n selection lines whose bit combinations determine which input is selected. The
multiplexer is often labeled as MUX in block diagrams.
A multiplexer is also called a data selector, since it selects one of many inputs
and steers the binary information to the output line.
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The circuit has two data input lines, one output line and one selection line, S.
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When S= 0, the upper AND gate is enabled and I0 has a path to the output.
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When S=1, the lower AND gate is enabled and I1 has a path to the output.
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Logic diagram
The multiplexer acts like an electronic switch that selects one of the two sources.
Truth table:
S Y
0 I0
1 I1
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EN
D
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4-to-1-Line Multiplexer
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Function table:
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
To demonstrate the circuit operation, consider the case when S1S0= 10. The AND
gate associated with input I2 has two of its inputs equal to 1 and the third input
connected to I2. The other three AND gates have atleast one input equal to 0, which
makes their outputs equal to 0. The OR output is now equal to the value of I2, providing
a path from the selected input to the output.
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FO
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EN
D
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Application:
The multiplexer is a very useful MSI function and has various ranges of
applications in data communication. Signal routing and data communication are the
important applications of a multiplexer. It is used for connecting two or more sources to
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guide to a single destination among computer units and it is useful for constructing a
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common bus system. One of the general properties of a multiplexer is that Boolean
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functions can be implemented by this device.
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Implementation of Boolean Function using MUX:
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be connected to the select lines of the multiplexer. The remaining single variable along
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with constants 1 and 0 is used as the input of the multiplexer. For example, if C is the
single variable, then the inputs of the multiplexers are C, C‘, 1 and 0. By this method
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Implementation table:
Apply variables A and B to the select lines. The procedures for implementing the
function are:
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C
FO
TS
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Multiplexer Implementation:
D
U
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Multiplexer Implementation:
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C
FO
TS
EN
D
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3. F ( A, B, C) = ∑m (1, 2, 4, 5)
Solution:
Variables, n= 3 (A, B, C)
Select lines= n-1 = 2 (S1, S0)
2n-1 to MUX i.e., 22 to 1 = 4 to 1 MUX
Input lines= 2n-1 = 22 = 4 (D0, D1, D2, D3)
Implementation table:
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4. F( P, Q, R, S)= ∑m (0, 1, 3, 4, 8, 9, 15)
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Solution:
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Variables, n= 4 (P, Q, R, S)
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Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
EN
Implementation table:
D
U
ST
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C
FO
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5. Implement the Boolean function using 8: 1 and also using 4:1 multiplexer
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Solution:
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Variables, n= 4 (A, B, C, D)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation table:
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Using 4: 1 MUX:
C
FO
TS
EN
D
U
ST
Implementation table:
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Multiplexer Implementation:
C
S.
U
C
FO
TS
EN
D
U
ST
Implementation table:
Multiplexer Implementation:
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C
S.
U
C
FO
TS
EN
D
U
ST
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Multiplexer Implementation:
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C
S.
U
C
FO
TS
EN
D
U
ST
9. Implement the Boolean function using 8: 1 and also using 4:1 multiplexer
F (w, x, y, z) = ∑m (1, 2, 3, 6, 7, 8, 11, 12, 14)
Solution:
Variables, n= 4 (w, x, y, z)
Select lines= n-1 = 3 (S2, S1, S0)
Implementation table:
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C
FO
TS
EN
D
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Solution:
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Variables, n= 4 (A, B, C, D)
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Implementation table:
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C
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Solution:
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Variables, n= 4 (A, B, C, D)
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
Implementation Table:
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12. An 8×1 multiplexer has inputs A, B and C connected to the selection inputs S2, S1,
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Multiplexer Implementation:
D
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DEMULTIPLEXER:
Demultiplex means one into many. Demultiplexing is the process of taking
information from one input and transmitting the same over one of several outputs.
A demultiplexer is a combinational logic circuit that receives information on a
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single input and transmits the same information over one of several (2n) output lines.
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C
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EN
D
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Logic Symbol
The input variable Din has a path to all four outputs, but the input information is
directed to only one of the output lines. The truth table of the 1-to-4 demultiplexer is
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shown below.
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Enable S1 S0 Din S. Y0 Y1 Y2 Y3
0 x x x 0 0 0 0
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1 0 0 0 0 0 0 0
FO
1 0 0 1 1 0 0 0
1 0 1 0 0 0 0 0
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1 0 1 1 0 1 0 0
EN
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 0
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1 1 1 0 0 0 0 0
ST
1 1 1 1 0 0 0 1
From the truth table, it is clear that the data input, Din is connected to the output
Y0, when S1= 0 and S0= 0 and the data input is connected to output Y1 when S1= 0 and
S0= 1. Similarly, the data input is connected to output Y2 and Y3 when S1= 1 and S0= 0
and when S1= 1 and S0= 1, respectively. Also, from the truth table, the expression for
outputs can be written as follows,
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connected to all the AND gates. The two select lines S1, S0 enable only one gate at a time
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and the data that appears on the input line passes through the selected gate to the
associated output line.
1-to-8 Demultiplexer:
A 1-to-8 demultiplexer has a single input, Din, eight outputs (Y0 to Y7) and three
select inputs (S2, S1 and S0). It distributes one input line to eight output lines based on
the select inputs. The truth table of 1-to-8 demultiplexer is shown below.
Din S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
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gates, but only one of the eight AND gates will be enabled by the select input lines. For
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example, if S2S1S0= 000, then only AND gate-0 will be enabled and thereby the data
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input, Din will appear at Y0. Similarly, the different combinations of the select inputs, the
input Din will appear at the respective output.
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FO
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EN
D
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Inputs Outputs
A B Bin Difference(D) Borrow(Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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S.
U
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FO
TS
EN
D
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ST