Electronic System Level Power and Performance

Analysis for Multi-Processor-System-on-Chip

Muhammad Mudussir Ayub Habibullah Ahmadzay, Josef Eckmüller Franz Kreupl
Electrical Engineering Department Intel Deutschland GmbH Electrical Engineering Department
Technische Universität München Munich, Germany Technische Universität München
Munich, Germany {philipp.a.hartmann,josef.eckmueller}@intel.com Munich, Germany
mudussir.ayub@tum.de franz.kreupl@tum.de

Abstract—Electronic System Level (ESL) is the highest level such as power and performance. A top-level view of POEM
of abstraction to represent embedded systems for Design Space is presented in Fig. 1.
Exploration (DSE). This work is the first step towards a In POEM, an application or a system-level use-case is mod-
comprehensive methodology development to address the DSE
for extra-functional properties such as power and performance. eled as a task graph using Intel SystemC library (ISCTLM), (a
The principle of separation of concerns is exercised in its true productivity layer) on top of Accellera [9] standard SystemC.
spirit and enhanced for power evaluation by proposing a specific ISCTLM is compliant to SystemC standards and includes
mapping step between power and performance models. generic bus sockets, component base classes, power trace
Index Terms—electronics system level, design space explo- infrastructure, register modeling tools, and many other con-
ration, performance models, power modeling, task graphs, low-
power, separation-of-concerns venience modeling tools for SystemC TLM modeling.
All the architectural elements like processors, memories,
buses are modeled at Transaction Level with Approximately-
I. I NTRODUCTION AND R ELATED WORK
Timed (AT) coding style using the same ISCTLM library, for
In order to perform an effective power/performance trade- power and performance simulations and analysis. At the end
off analysis in early design phases, the following key ingredi- of the simulation, stimuli for power model is generated, which
ents are required: contains the functional states and timing information, together
• Abstract performance model of the hardware architecture known as the state-residency of a processing element.
candidate(s) The behavior of the SystemC simulation can be controlled
• High-level description of the use cases under analysis using attributes based configuration mechanism. Both, the task
• Power model for the relevant hardware components graph and the architecture models are configured dynamically
using these attributes.
In the recent past, a significant amount of research has been
As power models are developed in a different environment,
carried out to develop ESL methodologies using Transaction
a mapping step and an interface between the SystemC simu-
Level Modeling (TLM) with the help of SystemC. Early
lation and power models are required to drive them using the
system-level power models are typically modeled by experts in
SystemC simulation for dynamic power estimation.
custom Excel sheets or dedicated frameworks like Intel® Do-
cea™ (Docea) [1]. In order to integrate these models with III. I NTERFACE AND M APPING
system-level simulations, two approaches have been proposed:
There are two main ways to build an interface between
co-simulation [2] or explicit annotation [3]–[7] using e.g. C++
performance (SystemC simulation) and power model, i.e.,
APIs for integration into SystemC TLM-2.0 Virtual Platform
using an API or VCD file.
(VP) simulations. The drawbacks of an explicit C++ API are
The number of components in performance and power
the manual rewrite of the power model into C++, limiting
models are not equal most of the time as they are created
reuse and increasing turnaround times for changes.
independently at different abstraction levels and granularities.
The main contribution of this work is a novel Power The performance model could be fine-grained, whereas the
Optimization and Exploration Methodology (POEM), which power model can be coarse-grained and vice versa. Hence, the
addresses such distributed project set-up by using the concept connection of such models is a non-trivial task and requires
of Separation of Concerns [8]. It first separates functionality an explicit mapping definition.
from architecture, and second the way power database is
Suppose the system has a total M number of components in
developed and attached.
the performance model, and each component ci ∈ {1, 2, .., M }
can take Kci discrete functional states, Sci ∈ {1, 2, ..Kci } at a
II. M ETHODOLOGY
given time of point. Given N number of time stamps tj in total
As stated earlier, the essence of POEM is an enhancement simulation time T , the functional states of the components in
of Separation of Concerns for extra-functional requirements, the performance model can be defined as M × N matrix:

978-1-7281-1957-1/19/$31.00 ©2019 IEEE

Authorized licensed use limited to: University of Management & Technology Lahore. Downloaded on July 16,2020 at 19:55:57 UTC from IEEE Xplore. Restrictions apply.
 Design specifications

Application Model
Performance Model
T5 T6
CPU CPU CPU
T4
T3 Performance Application
Mem CPU T1 Model Models
Mapping (SystemC Simulation) T2

Mapping
System Level Mapping
(SystemC
Simulation)

Mapping Power Model

Power State
database Residencies
State Residencies/ Docea Power
High Level Activites

Mapping
System Level

Power and
Performance
Evaluation
Results

ti
time

Fig. 1. Abstract representation of how POEM fits to the SoC design flow

⎡ ⎤ POEM is a novel methodology for power and performance

Sc1 ,t1 Sc1 ,tj+1 ··· Sc1 ,tN estimation for complex systems, like for instance mobile
⎢Sci+1 ,t1 Sci+1 ,tj+1 ··· Sci+1 ,tN ⎥
⎢ ⎥ platforms. The key advantage over the state-of-the-art is the
W=⎢ . .. .. .. ⎥ (1)
⎣ .. . . . ⎦ explicit mapping methodology between performance models
ScM ,t1 ScM ,tj+1 ··· ScM ,tN and the power models (defined by state-of-the-art EDA frame-
works like Docea) along the modeling of system level use-
Similarly, the power states of the components in the power case with task graphs at first place. This enables model co-
model can be shown in a Q × N matrix Y : development, team collaboration, and maximizes the reuse of
⎡ ⎤ existing models for a power/performance integrated analysis.
Pr1 ,t1 Pr1 ,tj+1 · · · Pr1 ,tN .
⎢Pri+1 ,t1 Pri+1 ,tj+1 · · · Pri+1 ,tN ⎥
⎢ ⎥
Y=⎢ . .. .. .. ⎥ (2) R EFERENCES
⎣ .. . . . ⎦
[1] “Intel® Docea™,” https://www.intel.com/content/www/us/en/system-
PrQ ,t1 PrQ ,tj+1 ··· PrQ ,tN modeling-and-simulation/docea/overview.html, accessed: 2019-02-23.
[2] T. Bouhadiba, M. Moy, F. Maraninchi, J. Cornet, L. Maillet-Contoz,
Assuming that Q is the number of components in the power and I. Materic, “Co-simulation of functional systemc tlm models with
model, that each component ri ∈ {1, 2, .., Q} can have Lri power/thermal solvers,” in Parallel and Distributed Processing Sympo-
discrete power states, and Pri ∈ {1, 2, .., Lri } at a given time sium Workshops & PhD Forum (IPDPSW). IEEE, 2013, pp. 2176–2181.
[3] S. K. Rethinagiri, O. Palomar, J. A. Moreno, O. Unsal, and A. Cristal,
stamp. “Vppet: Virtual platform power and energy estimation tool for hetero-
The operation of extracting power states from corresponding geneous mpsoc based fpga platforms,” in 24th Intl. Workshop on Power
and Timing Modeling, Optimization and Simulation (PATMOS), 2014.
functional states is performed by the mapping function F (·), [4] M. Moy, C. Helmstetter, T. Bouhadiba, and F. Maraninchi, “Modeling
associating a set of power modes Pri ,t from the history of Power Consumption and Temperature in TLM Models,” Leibniz Trans-
functional states Sci ,t , t ∈ {0 . . . t − 1} for each time stamp. actions on Embedded Systems, vol. 3, no. 1, pp. 03–1, 2016.
[5] A. B. Ameur, D. Martinot, P. Guitton-Ouhamou, V. Frascolla, F. Verdier,
Y = F (W) (3) and M. Auguin, “Power and performance aware electronic system level
design,” in Industrial Embedded Systems (SIES). IEEE, 2017, pp. 1–4.
[6] K. Grüttner, P. A. Hartmann, T. Fandrey, K. Hylla, D. Lorenz, S. Stattel-
The mapping function F (·) is written manually for every mann, B. Sander, O. Bringmann, W. Nebel, and W. Rosenstiel, “An ESL
new component and added into the database of the availbe timing & power estimation and simulation framework for heterogeneous
components for later re-use. SoCs,” in (SAMOS XIV), Jul. 2014, pp. 181–190.
[7] D. Lorenz, P. A. Hartmann, K. Grüttner, and W. Nebel, “Non-invasive
IV. C OMPARISON AND C ONCLUSION power simulation at system-level with systemc,” in Integrated Circuit
and System Design. Power and Timing Modeling, Optimization and
A comparison for network processor between the Platform Simulation. Springer Berlin Heidelberg, 2013, pp. 21–31.
[8] K. Keutzer, A. R. Newton, J. M. Rabaey, and A. Sangiovanni-Vincentelli,
Architect MCO (PA) by Synopsys [10] and POEM is made “System-level design: orthogonalization of concerns and platform-based
for two reasons. First, to verify the accuracy of what POEM design,” IEEE transactions on computer-aided design of integrated
produces. Second, the methodology of PA is very similar to circuits and systems, vol. 19, no. 12, pp. 1523–1543, 2000.
[9] A. S. Initiative et al., “Ieee 1666 standard: Systemc language reference
the POEM. The results show up-to 3 and 7 percent deviation manual., 2011,” URL: http://www. accellera. org.
in throughput and power consumption estimation of the core [10] “PlatformArchitect by Synopsys®,” https://www.synopsys.com/verification/virtual-
and memories, respectively. prototyping/platform-architect.html, accessed: 2018-02-23.

Authorized licensed use limited to: University of Management & Technology Lahore. Downloaded on July 16,2020 at 19:55:57 UTC from IEEE Xplore. Restrictions apply.