SEMINAR REPORT

CARBON NANOTUBE FIELD-EFFECT TRANSISTOR (CNTFET)

Bachelor of Technology In

Electronics and Communication Engineering

6th Semester

Department of Electronics and Communication Engineering

Jamia Millia Islamia

New Delhi

Submitted By :

Amena Tarique (16BEC027)

Under the Guidance of :

Dr. M. Nizamuddin
 CONTENTS

1 Preview of MOSFET

1.1 Nanotechnology With Time

2 Introduction to CNTFET

3 Types of CNTFET

3.1 Geometry Type

3.2 Operation Type

4 Mechanism of CNTFET

5 Modelling of CNTFET Device

6 CNTFET over CMOS

6.1 Quasi ballistic transportation of electrons and holes

6.2 High Drive current/ Trans-conductance

6.3 High Temperature resilience/ Covalent Bond

7 Conclusion

8 Future Work

References
 CHAPTER

1
Preview of MOSFET

The Metal oxide-semiconductor FET (MOSFET) has

led to the second electronics revolution within the
1970s and 1980s. during which the microprocessor
has created possible powerful desktop computers
and complex hand-held calculators. The MOSFET
can be made in minimum size, so high-density VLSI
circuits and high-density memories are possible.

The scaling of MOSFET has been the driving force

towards technological advancement, But
Continuous scaling includes short channel effects,
high leakage current, excessive process variation ,
and reliability issues.

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1.1 Nanotechnology With Time

Moore’s Law states that the number of transistors

per integrated circuit doubles every 24 months, and
it has been the guiding principle for the
semiconductor industry for over 30 years.

In order to sustain Moore’s Law, the physical gate

length (Lg) of the transistor has been scaled by
~30% every generation, as shown in Fig 1.

The current 90 nm generation technology node

produces CMOS devices with Lg of ~50 nm.

It is projected that the Lg of the transistor will reach

~10 nm in 2011.

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Through silicon technology innovations and
breakthroughs like metal-gate/high-K stacks,
uniaxially strained Si channels, biaxially strained Si
and SiGe channels, and also the non-planar
fully-depleted tri-gate CMOS transistor architecture,
CMOS transistor scaling and Moore’s Law can
continue at least through the early coming decade.

Recently, tremendous progress has been made in

the research of novel nanoelectronic devices such
as carbon nanotube FETs, Si-nanowire FETs, and
III-V compound semiconductor FETs.

These devices represent both challenges and

opportunities for future nanoelectronics applications.
By combining Silicon innovations with the
nanotechnologies onto the same Silicon platform, it
is expected that circuit functionality could have
greatly enhanced and Moore’s Law will be extended
well into the coming decades.

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 CHAPTER

2
Introduction to CNTFET

A Carbon Nanotube, discovered by S. Iijima in 1991,

it is a sheet of hexagonally organized carbon atoms
rolled up in a tube of a few nanometers in diameter,
which might be many microns long. Graphene is a
single sheet of carbon atoms arranged within the
well-known honeycomb structure. This lattice is
shown in Fig 2. Carbon has four valence electrons,
three of them are used for the sp2 bonds. In
sp2-hybridization an electron is promoted from the
2s-orbital to a p-orbital, then two electrons from
different 2p-orbitals combine with the single electron
left in the 2s-orbital to operate three equivalent
sp2-orbitals. These orbitals are planar with 120
between the major lobes, and the remaining
p-orbital is perpendicular to this plane. The
remaining p-orbital is perpendicular to the graphene,

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and electrons in this orbital bond to other carbon
atoms through weak π-bonds. The electrons in the
p-orbitals are thus loosely bound and responsible for
the conductance of graphite. Since the CNTFET is
made up of one or more sheets of graphene rolled
up in a tubular structure, the binding in the CNTFET
is nearly identical to that of graphite. The differences
in binding are due to the larger inter-shell distance in
CNTFET compared to the inter-layer distance of
graphite, and the curvature of the graphene sheets.
Fig 2. shows the construction of a graphene sheet,
in which carbon atoms are located at each crossing
and the lines indicate the chemical bonds, which are
derived from sp2-orbitals. Ch is the chiral vector,
While T is the tube axis; and φ is the chiral angle.

Figure 2. Lattice of graphene.

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The chiral vector, Ch, is the vector perpendicular to
tube axis T, which is given by:

being n and m a pair of integers, and a1 and a2 the

lattice vectors, which can be written as:

Where, a0 is the inner-atomic distance between

each carbon atom and nearby atoms, equals to 1.42
Å.

The pz atomic-orbitals are perpendicular to the plane

and movement is rotational symmetric around the
z-axis.

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 CHAPTER

3
Types of CNTFET

Geometry dependent CNTFET

Based on the geometry of gate, CNTFETs are

classified as Bottom gate, Top gate and Coaxial
CNTFETs.

a. Bottom Gate

The single-wall carbon nanotube (SW-CNT) may be

a promising candidate as a building block for future
nanoelectronic devices. These devices generally
use a gate electrode to manage the carrier density
of a semiconducting (SW-CNT). The best
configuration of a CNTFET is that the bottom-gate
FET, as shown in fig.3, in which, (SW-CNT) is
spread or directly grown on a SiO2/Si substrate,

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source-drain contacts shaped at the ends of the
CNT and its transport properties controlled by
applying a substrate voltage.

Figure 3. Bottom gate CNTFET.

b. Top Gate

To get better performance in CNT, They proposed

the first Top-gate CNTFET in 2003. Top-gate
CNTFETs is the gate electrode and gate insulator
are located on top of the (SW-CNT). To improve the
device performance further, a thinner gate insulator
with a higher dielectric constant may be used.
Recently, high k materials, like TiO2, ZrO2 and HfO2.

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 Figure 4. Top gate CNTFET.

c. Coaxial Gate

CNT is coaxially gated, thus the characteristics of

cylindrical coordinates of the potential have been
created, and therefore the charge is constantly
around the nanotube. In this structure, coaxial-gate
covers all-around channels thus are defined as one
of the channel parameters.

Operation dependent CNTFET

Based on the type of operations used in CNTFET is

classified into two categories.

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I. Schottky-barrier (SB) CNTFET

In order to find more about the operation of

SB-CNTFET, Is to examine the energy band
diagram for the structure is necessary. At the
intersection between the metal contacts and also
the semiconductor CNT, Schottky barriers are
created.

Their conductivity is controlled by the bulk of carriers

tunneling through the Schottky Barrier at the top
contacts. Their performance and therefore the ON
current is determined not by the channel
conductance, however by the contact resistance
due to tunneling barriers at drain and source contact.
They exhibit am-bipolar behavior.

II. MOS-like CNTFET (C-CNTFET)

In the case of MOS-like CNTFET the source and

drain are basically semiconductors of p-type or
n-type that are heavily doped. These devices,
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additionally denoted as conventional C-CNTFET,
show the fine performances in terms of “on-off” ratio
currents and subthreshold swing. And In Fig. 5
shows that whose conduction behavior is similar to a
common MOSFET.

Figure 5. 3D representation of C-CNTFET.

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 CHAPTER

4
Mechanism of CNTFET

The CNTFET is a three-terminal device, By using

SW-CNT because the channel between two
electrodes that work as the source and drain
contacts of FET, a coaxial-CNTFET may be fictitious.
Heavily doped semiconductors because of the
ability to create an Ohmic contact may be used as
ideal electrodes however they suffer from high
parasitic resistance. The existence of the potential
barriers at the metal-CNT interface, changes the
device to a CNTFET resembling to Schottky barrier
MOSFETs. However, heavily doped CNT contacts
may be used to get to a behavior like conventional
MOSFETs.

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CNTFET uses semiconductor carbon nanotube as
the channel, as The semiconducting channel
between the 2 contacts known as drain and source.

The channel switches ON or OFF electrostatically

through the third contact gate (G).

To Calculate the PMOS or NMOS ratio for CMOS,

the transistor width is changed. It demonstrates the
idealistic of PMOS to NMOS width proportion for
CMOS circuits. (W/L) ratio is connected to the
trans-conductance and the current capability, with
the multiplicity factor (m). The higher (W/L) ratio,
increasing of the current gain including
subsequently a higher the current for a given Vg. A
similar is for a higher (m) that defines (m·W/L).

The number of CNTs is changed due to a CNTFET

uses CNTs for the conducting channel between
Source (S) and Drain (D).

The layout of CNTFET is shown in Figure 6. The

area of the channel is known as the width (W) of the
source and drain contacts and therefore the length
(L) of the nanotube.

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 Figure 6. Top View of CNTFET Device

Efforts are created in recent years on modeling and

simulating CNT connected devices such as
CNTFET to estimate the potential performance at
the device level. Varied optimized schemes are
suggested and demonstrated to attenuate the
impact of parasitic capacitance and therefore
improves the speed of CNT ICs. CNTFET width
increases when the number of CNTs increases
same as the the width change in MOSFET.

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 CHAPTER

5
Modelling of CNTFET Device

In CNTFET modelling device, The simulations

perform a consistent resolution between Poisson’s
equation and therefore the nonequilibrium Green’s
operate equations.

Which two-dimensional Poisson equation is

resolved within the cylindrical coordinates for
coaxially gated CNTFETs. The permittivity varies
solely in the radial direction.

In the Schottky-barrier CNTFETs, Dirichlet boundary

conditions the source, drain, and gate are used.

Von Neumann boundary conditions are strictly used

on the exposed surface of the dielectric. There, the
radial part of the electric field is about to zero.

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Also in zero-field precondition is applied at the
source (S) and drain (D) ends with doped reservoirs.
There, the axial component of the electric field is
fixed to zero. The CNTs in CNTFET are modeled
using a tight-binding -bond model with one orbital
per carbon atom.

The recursive Green function algorithm is used to

resolve the non-equilibrium Green’s function
equations for the mean-field charge density and
current. The surface Green’s function is calculated
using the decimation method.

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 CHAPTER

6
CNTFET over CMOS

The CNTFET is one of the foremost promising

candidates to become the successor of Si-CMOS
within the close to future due to its best
electrostatics and higher mobility.

According to the scaling of devices in nanometer

regime speed and power-related problems rises in
digital circuits. CNTFET has been used in the
present work as an occasional power circuit
component. The plus point of CNTFET is low power
and energy consumption as compared to standard
CMOS.

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6.1 Quasi ballistic transportation of
electrons and holes

The electrons in the carbon nanotube are restricted

to the atomic plane of the graphene. Since the
structure of the CNT is quasi 1-D, the electrons
within the tube are affected. The electrons can only
move on the axis of the tube.

Only forward and backward scattering is feasible for

the electron and holes within the carbon nanotube.

Experimentally determined mean-free-path is of the

order of 1μm implies that carbon nanotubes have
ballistic transport capability.

6.2 High Drive current/

Trans-conductance

For the p-CNTFET, the on-current per unit (~1500

μA/μm) at a gate overdrive of (0.6V). This value is

20
considerably higher than the (~500 μA/μm) for a
p-MOSFET at a gate overdrive of (0.6V).

The maximum transconductance [dl/dVg] is

observed to be (20 μA/V) at (-0.9 Vg). This, as
compared to typical MOSFET, is a significantly
better current generation by the device.

6.3 High Temperature resilience/

Covalent Bond

The atoms at intervals a carbon nanotube molecule

bond covalently in hexagonal rings, and this
graphite-like structure has significant strength and
stability.

Electrically, this helps in considerably reducing

electromigration, thereby accessing high current
operation.

Carbon nanotubes conduct heat nearly further as

Diamond, therefore extremely high device-packing
densities should not be impossible.

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CNTFET has low intrinsic capacitance and
near-ideal sub-threshold slope.

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 CHAPTER

7
Conclusion

We have Determined that CNTFET has capability to

use a nanoscale transistor in coming decades. It has
the most attractive feature is its ballistic transport
mechanism which results in high intrinsic
performance. As well as CNTFET over MOSFET in
I-V Characteristics have shown that there is no
specific process technology is available unless its
simulated. The present day, latest scale
manufacturing is at 32nm node. In Addition, we
found the advantage of CNTFET over CMOS and
how CNTFET is taking over the manufacturing
industry to improve lifestyle. Prediction through
modeling forms the Idea of engineering pattern. The
machine power at the fingertips of the professional
developer is increasing rapidly and techniques for
computer simulation are changing enormously.

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 CHAPTER

8
Future Work

Future of Carbon Nanotube has a hope, All

Experiments are needed to be done to guarantee
the capitulate of CNTs growth and better production
technique for big quantity of pure nanotube that
have to be found in near future.

Unfortunately, Some amazing ideas are not fully

accomplished due to a lack of materials which
needed the most.

To replace the conventional transistor with Carbon

nanotube transistor, The major obstacles need to be
controlled. such as, the chirality, before VLSI chips
with carbon nanotube are developed.

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Reference

[1] An Chen, James Hutchby, Victor Zhirnov, George Bourianoff,

(2015) ''Emerging Nanoelectronic Devices'', John Wiley & Sons.

[2] A. Rahman, J. Guo, S. Datta, M. Lundstrom (2003) "Theory of

Ballistic Nanotransistors", IEEE on Electron Devices.

[3] Robert Chau, M. Doczy, B. Doyle, Suman Datta (2004)

''Advanced CMOS Transistors in the Nanotechnology Era for
High-Performance, Low-Power Logic Applications'', Components
Research, Logic Technology Development, Intel Corporation.

[4] Ale Imran, Mohd. Hasan, A. Islam, SA Abbasi (2012)

''Optimized design of a 32-nm CNFET-based low-power
ultrawideband CCII'', IEEE Transactions on Nanotechnology.

[5] P. L. McEuen, M. S. Fuhrer, P. Hongkun (2002) ''Single-walled

carbon nanotube electronics'', IEEE Transactions on
Nanotechnology.

[6] Leonardo de Camargo e Castro (2006) ''Modelling of Carbon

Nanotube Field-Effect Transistor'', University of British Colombia.

[7] A. Javey, J. Guo, D.B. Farmer, Q. Wang, E. Yenilmez, R. G.

Gordon, M. Lundstorm, H. Dai (2004) '' Self-aligned ballistic
molecular transistors and electrically parallel nanotube array'',
Nano Lett, Vol.4, pg.7.

[8] S. Thompson (2001), IEDM. Digest, pg.257

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