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 Jameco Part Number 203730

M27C512

512 Kbit (64Kb x8) UV EPROM and OTP EPROM

■ 5V ± 10% SUPPLY VOLTAGE in READ

OPERATION
■ ACCESS TIME: 45ns
■ LOW POWER “CMOS” CONSUMPTION:
28
– Active Current 30mA 28

– Standby Current 100µA

1
PROGRAMMING VOLTAGE: 12.75V ± 0.25V
1
■
FDIP28W (F) PDIP28 (B)
■ PROGRAMMING TIMES of AROUND 6sec.
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 3Dh

DESCRIPTION
The M27C512 is a 512 Kbit EPROM offered in the PLCC32 (C) TSOP28 (N)
two ranges UV (ultra violet erase) and OTP (one 8 x 13.4 mm
time programmable). It is ideally suited for applica-
tions where fast turn-around and pattern experi-
mentation are important requirements and is
Figure 1. Logic Diagram
organized as 65,536 by 8 bits.
The FDIP28W (window ceramic frit-seal package)
has transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure. VCC
For applications where the content is programmed
only one time and erasure is not required, the
M27C512 is offered in PDIP28, PLCC32 and 16 8
TSOP28 (8 x 13.4 mm) packages. A0-A15 Q0-Q7

E M27C512

GVPP

VSS
AI00761B

April 2001 1/18

M27C512

Figure 2A. DIP Connections Figure 2B. LCC Connections

VCC
A12
A15

A14
A13
A15 1 28 VCC

DU
A7
A12 2 27 A14
A7 3 26 A13 1 32
A6 A8
A6 4 25 A8
A5 5 24 A9 A5 A9
A4 6 23 A11 A4 A11
A3 NC
A3 7 22 GVPP
M27C512 A2 9 M27C512 25 GVPP
A2 8 21 A10
A1 A10
A1 9 20 E
A0 10 19 Q7 A0 E
NC Q7
Q0 11 18 Q6
Q1 12 17 Q5 Q0 Q6
17
Q2 13 16 Q4

Q1
Q2
VSS

Q3
Q4
Q5
DU
VSS 14 15 Q3
AI00762
AI00763

Figure 2C. TSOP Connections Table 1. Signal Names

A0-A15 Address Inputs

Q0-Q7 Data Outputs

E Chip Enable

GVPP 22 21 A10 GVPP Output Enable / Program Supply

A11 E
A9 Q7 VCC Supply Voltage
A8 Q6
VSS Ground
A13 Q5
A14 Q4 NC Not Connected Internally
VCC 28 15 Q3
M27C512 DU Don’t Use
A15 1 14 VSS
A12 Q2
A7 Q1
A6 Q0
A5 A0
A4 A1
A3 7 8 A2
AI00764B

2/18
 M27C512

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit

TA Ambient Operating Temperature (3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage (except A9) –2 to 7 V

VCC Supply Voltage –2 to 7 V

VA9 (2) A9 Voltage –2 to 13.5 V

VPP Program Supply Voltage –2 to 14 V

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.

Table 3. Operating Modes

Mode E GV PP A9 Q7-Q0

Read VIL V IL X Data Out

Output Disable VIL VIH X Hi-Z

Program VIL Pulse VPP X Data In

Program Inhibit V IH VPP X Hi-Z

Standby V IH X X Hi-Z

Electronic Signature VIL V IL VID Codes

Note: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h

Device Code VIH 0 0 1 1 1 1 0 1 3Dh

3/18
M27C512

Table 5. AC Measurement Conditions

High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns

Input Pulse Voltages 0 to 3V 0.4V to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. Testing Input Output Waveform Figure 4. AC Testing Load Circuit

1.3V
High Speed

3V 1N914

1.5V

0V 3.3kΩ

DEVICE
Standard UNDER OUT
TEST
2.4V CL
2.0V

0.8V
0.4V
CL = 30pF for High Speed
AI01822
CL = 100pF for Standard
CL includes JIG capacitance AI01823B

Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)

Symbol Parameter Test Condit ion Min Max Unit
C IN Input Capacitance VIN = 0V 6 pF

COUT Output Capacitance VOUT = 0V 12 pF

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION dresses are stable, the address access time

The modes of operations of the M27C512 are list- (tAVQV) is equal to the delay from E to output
ed in the Operating Modes table. A single power (tELQV). Data is available at the output after a delay
supply is required in the read mode. All inputs are of t GLQV from the falling edge of G, assuming that
TTL levels except for GVPP and 12V on A9 for E has been low and the addresses have been sta-
Electronic Signature. ble for at least tAVQV-tGLQV.
Read Mode Standby Mode
The M27C512 has two control functions, both of The M27C512 has a standby mode which reduces
which must be logically active in order to obtain the active current from 30mA to 100µA The
data at the outputs. Chip Enable (E) is the power M27C512 is placed in the standby mode by apply-
control and should be used for device selection. ing a CMOS high signal to the E input. When in the
Output Enable (G) is the output control and should standby mode, the outputs are in a high imped-
be used to gate data to the output pins, indepen- ance state, independent of the GVPP input.
dent of device selection. Assuming that the ad-

4/18
 M27C512

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA

E = VIL, G = V IL,
ICC Supply Current 30 mA
IOUT = 0mA, f = 5MHz

ICC1 Supply Current (Standby) TTL E = VIH 1 mA

ICC2 Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA

IPP Program Current VPP = VCC 10 µA

VIL Input Low Voltage –0.3 0.8 V

VIH (2) Input High Voltage 2 VCC + 1 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

Output High Voltage TTL IOH = –1mA 3.6 V

VOH
Output High Voltage CMOS IOH = –100µA VCC – 0.7V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Maximum DC voltage on Output is VCC +0.5V.

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C512

Symbol Alt Parameter Test Conditi on -45 (3) -60 -70 -80 Unit

Min Max Min Max Min Max Min Max

Address Valid to
tAVQV tACC E = VIL, G = VIL 45 60 70 80 ns
Output Valid
Chip Enable Low to
tELQV tCE G = VIL 45 60 70 80 ns
Output Valid
Output Enable Low
tGLQV t OE E = VIL 25 30 35 40 ns
to Output Valid
Chip Enable High to
tEHQZ (2) tDF G = VIL 0 25 0 25 0 30 0 30 ns
Output Hi-Z
Output Enable High
tGHQZ (2) tDF E = VIL 0 25 0 25 0 30 0 30 ns
to Output Hi-Z
Address Transition to
tAXQX tOH E = VIL, G = VIL 0 0 0 0 ns
Output Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.

5/18
M27C512

Table 8B. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C512

Symbol Alt Parameter Test Conditi on -90 -10 -12 -15/-20/-25 Unit

Min Max Min Max Min Max Min Max

Address Valid to
tAVQV tACC E = VIL, G = VIL 90 100 120 150 ns
Output Valid
Chip Enable Low to
tELQV tCE G = VIL 90 100 120 150 ns
Output Valid
Output Enable Low
tGLQV t OE E = VIL 40 40 50 60 ns
to Output Valid
Chip Enable High to
tEHQZ (2) tDF G = VIL 0 30 0 30 0 40 0 50 ns
Output Hi-Z
Output Enable High
tGHQZ (2) tDF E = VIL 0 30 0 30 0 40 0 50 ns
to Output Hi-Z
Address Transition to
tAXQX tOH E = VIL, G = VIL 0 0 0 0 ns
Output Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

A0-A15 VALID VALID

tAVQV tAXQX

tEHQZ
tGLQV

tELQV tGHQZ

Hi-Z
Q0-Q7

AI00735B

6/18
 M27C512

Table 9. Programming Mode DC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current VIL ≤ VIN ≤ VIH ±10 µA

I CC Supply Current 50 mA

IPP Program Current E = VIL 50 mA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –1mA 3.6 V

VID A9 Voltage 11.5 12.5 V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.

Two Line Output Control System Considerations

Because EPROMs are usually used in larger The power switching characteristics of Advanced
memory arrays, the product features a 2 line con- CMOS EPROMs require careful decoupling of the
trol function which accommodates the use of mul- devices. The supply current, ICC, has three seg-
tiple memory connection. The two line control ments that are of interest to the system designer:
function allows: the standby current level, the active current level,
a. the lowest possible memory power dissipation, and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
b. complete assurance that output bus contention the transient current peaks is dependent on the
will not occur.
capacitive and inductive loading of the device at
For the most efficient use of these two control the output. The associated transient voltage peaks
lines, E should be decoded and used as the prima- can be suppressed by complying with the two line
ry device selecting function, while G should be output control and by properly selected decoupling
made a common connection to all devices in the capacitors. It is recommended that a 0.1µF ceram-
array and connected to the READ line from the ic capacitor be used on every device between VCC
system control bus. This ensures that all deselect- and VSS. This should be a high frequency capaci-
ed memory devices are in their low power standby tor of low inherent inductance and should be
mode and that the output pins are only active placed as close to the device as possible. In addi-
when data is required from a particular memory tion, a 4.7µF bulk electrolytic capacitor should be
device. used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.

7/18
M27C512

Table 10. MARGIN MODE AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tA9HVPH t AS9 VA9 High to VPP High 2 µs

tVPHEL tVPS VPP High to Chip Enable Low 2 µs

tA10HEH tAS10 VA10 High to Chip Enable High (Set) 1 µs

tA10LEH tAS10 VA10 Low to Chip Enable High (Reset) 1 µs

tEXA10X tAH10 Chip Enable Transition to VA10 Transition 1 µs

t EXVPX tVPH Chip Enable Transition to VPP Transition 2 µs

tVPXA9X tAH9 VPP Transition to VA9 Transition 2 µs

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.

Figure 6. MARGIN MODE AC Waveforms

VCC

A8

A9

tA9HVPH tVPXA9X

GVPP

tVPHEL tEXVPX

tA10HEH tEXA10X

A10 Set

A10 Reset

tA10LEH

AI00736B

Note: A8 High level = 5V; A9 High level = 12V.

8/18
 M27C512

Table 11. Programming Mode AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tAVEL tAS Address Valid to Chip Enable Low 2 µs

tQVEL tDS Input Valid to Chip Enable Low 2 µs

t VCHEL tVCS VCC High to Chip Enable Low 2 µs

tVPHEL tOES VPP High to Chip Enable Low 2 µs

tVPLVPH tPRT VPP Rise Time 50 ns

tELEH tPW Chip Enable Program Pulse Width (Initial) 95 105 µs

tEHQX tDH Chip Enable High to Input Transition 2 µs

tEHVPX tOEH Chip Enable High to VPP Transition 2 µs

tVPLEL tVR VPP Low to Chip Enable Low 2 µs

tELQV tDV Chip Enable Low to Output Valid 1 µs

tEHQZ (2) tDFP Chip Enable High to Output Hi-Z 0 130 ns

t EHAX tAH Chip Enable High to Address Transition 0 ns

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.

Programming E is pulsed to V IL. The data to be programmed is

When delivered (and after each erasure for UV applied to 8 bits in parallel to the data output pins.
EPROM), all bits of the M27C512 are in the ’1’ The levels required for the address and data in-
state. Data is introduced by selectively program- puts are TTL. VCC is specified to be 6.25V ±
ming ’0’s into the desired bit locations. Although 0.25V. The M27C512 can use PRESTO IIB Pro-
only ’0’s will be programmed, both ’1’s and ’0’s can gramming Algorithm that drastically reduces the
be present in the data word. The only way to programming time (typically less than 6 seconds).
change a ’0’ to a ’1’ is by die exposure to ultraviolet Nevertheless to achieve compatibility with all pro-
light (UV EPROM). The M27C512 is in the pro- gramming equipments, PRESTO Programming
gramming mode when VPP input is at 12.75V and Algorithm can be used as well.

9/18
M27C512

Figure 7. Programming and Verify Modes AC Waveforms

A0-A15 VALID

tAVEL tEHAX

Q0-Q7 DATA IN DATA OUT

tQVEL tEHQX tEHQZ

VCC tELQV

tVCHEL tEHVPX
GVPP

tVPHEL tVPLEL

E
tELEH

PROGRAM VERIFY

AI00737

Figure 8. Programming Flowchart PRESTO IIB Programming Algorithm

PRESTO IIB Programming Algorithm allows the
whole array to be programmed with a guaranteed
VCC = 6.25V, VPP = 12.75V margin, in a typical time of 6.5 seconds. This can
be achieved with STMicroelectronics M27C512
SET MARGIN MODE due to several design innovations described in the
M27C512 datasheet to improve programming effi-
ciency and to provide adequate margin for reliabil-
n=0 ity. Before starting the programming the internal
MARGIN MODE circuit is set in order to guarantee
that each cell is programmed with enough margin.
E = 100µs Pulse
Then a sequence of 100µs program pulses are ap-
NO plied to each byte until a correct verify occurs. No
overprogram pulses are applied since the verify in
++n NO
VERIFY ++ Addr MARGIN MODE provides the necessary margin.
= 25
Program Inhibit
YES YES
Programming of multiple M27C512s in parallel
with different data is also easily accomplished. Ex-
Last NO cept for E, all like inputs including GVPP of the par-
FAIL Addr allel M27C512 may be common. A TTL low level
YES pulse applied to a M27C512’s E input, with VPP at
12.75V, will program that M27C512. A high level E
RESET MARGIN MODE input inhibits the other M27C512s from being pro-
grammed.
CHECK ALL BYTES Program Verify
1st: VCC = 6V A verify (read) should be performed on the pro-
2nd: VCC = 4.2V
grammed bits to determine that they were correct-
AI00738B ly programmed. The verify is accomplished with G
at V IL. Data should be verified with tELQV after the
falling edge of E.

10/18
 M27C512

Electronic Signature ERASURE OPERATION (applies for UV EPROM)

The Electronic Signature (ES) mode allows the The erasure characteristics of the M27C512 is
reading out of a binary code from an EPROM that such that erasure begins when the cells are ex-
will identify its manufacturer and type. This mode posed to light with wavelengths shorter than ap-
is intended for use by programming equipment to proximately 4000 Å. It should be noted that
automatically match the device to be programmed sunlight and some type of fluorescent lamps have
with its corresponding programming algorithm. wavelengths in the 3000-4000 Å range.
The ES mode is functional in the 25°C ± 5°C am- Research shows that constant exposure to room
bient temperature range that is required when pro- level fluorescent lighting could erase a typical
gramming the M27C512. To activate the ES M27C512 in about 3 years, while it would take ap-
mode, the programming equipment must force proximately 1 week to cause erasure when ex-
11.5V to 12.5V on address line A9 of the posed to direct sunlight. If the M27C512 is to be
M27C512. Two identifier bytes may then be se- exposed to these types of lighting conditions for
quenced from the device outputs by toggling ad- extended periods of time, it is suggested that
dress line A0 from VIL to VIH. All other address opaque labels be put over the M27C512 window to
lines must be held at VIL during Electronic Signa- prevent unintentional erasure. The recommended
ture mode. Byte 0 (A0 = VIL) represents the man- erasure procedure for the M27C512 is exposure to
ufacturer code and byte 1 (A0 = VIH) the device short wave ultraviolet light which has wavelength
identifier code. For the STMicroelectronics 2537 Å. The integrated dose (i.e. UV intensity x
M27C512, these two identifier bytes are given in exposure time) for erasure should be a minimum
Table 4 and can be read-out on outputs Q7 to Q0. of 15 W-sec/cm2. The erasure time with this dos-
age is approximately 15 to 20 minutes using an ul-
traviolet lamp with 12000 µW/cm2 power rating.
The M27C512 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.

11/18
M27C512

Table 12. Ordering Information Scheme

Example: M27C512 -70 X C 1 TR

Device Type
M27

Supply Voltage
C = 5V

Device Function
512 = 512 Kbit (64Kb x8)

Speed
-45 (1)= 45 ns
-60 = 60 ns
-70 = 70 ns
-80 = 80 ns
-90 = 90 ns
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-20 = 200 ns
-25 = 250 ns

V CC Tolerance
blank = ± 10%
X = ± 5%

Package
F = FDIP28W
B = PDIP28
C = PLCC32
N = TSOP28: 8 x 13.4 mm

Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C

Optio ns
X = Additional Burn-in
TR = Tape & Reel Packing

Note: 1. High Speed, see AC Characteristics section for further information.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.

12/18
 M27C512

Table 13. Revision History

Date Revision Details
November 1998 First Issue

09/25/00 AN620 Reference removed

04/02/01 FDIP28W mechanical dimensions changed (Table 14)

13/18
M27C512

Table 14. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 36.50 37.34 1.437 1.470
D2 33.02 – – 1.300 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 4.10 0.125 0.161
S 1.52 2.49 0.060 0.098
∅ 7.11 – – 0.280 – –
α 4° 11° 4° 11°
N 28 28

Figure 9. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline

A2 A3 A

A1 L α
B1 B e C
eA
D2
eB
D
S
N

∅ E1 E

1
FDIPW-a

Drawing is not to scale.

14/18
 M27C512

Table 15. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max

A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 36.83 37.34 1.450 1.470

D2 33.02 – – 1.300 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.08 0.070 0.082
α 0° 10° 0° 10°

N 28 28

Figure 10. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline

A2 A

A1 L α
B1 B e1 C
eA
D2 eB

D
S
N

E1 E

1
PDIP

Drawing is not to scale.

15/18
M27C512

Table 16. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 0.38 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
e 1.27 0.050
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
F 0.00 0.25 0.000 0.010
R 0.89 0.035
N 32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004

Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline

D A1
D1 A2

1 N
B1

e
Ne E1 E F D2/E2
B
0.51 (.020)

1.14 (.045)

Nd A

R CP
PLCC

Drawing is not to scale.

16/18
 M27C512

Table 17. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max

A 1.25 0.049
A1 0.20 0.008
A2 0.95 1.15 0.037 0.045
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469

E 7.90 8.10 0.311 0.319

e 0.55 – – 0.022 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N 28 28
CP 0.10 0.004

Figure 12. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Outline
A2

22 21
e

28
1 E

B
7 8

D1 A
D CP

DIE

TSOP-c A1 α L
Drawing is not to scale

17/18
M27C512

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners

 2001 STMicroelectronics - All Rights Reserved

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