Q1
Q1
Q1
Q1 .(a) Analyse the data dependencies among the following statements in a given program:
Note that (Ri) means that the content of register Ri and Memory(10) contains 64 initially.
(d) What do you mean by control flow and Data flow computers? State advantage and disadvantage of
data flow computing?
(e) Answers the following questions for the k-ary n-cube network.
Q2. (a) Consider n level hierarchical memory, let ‘hi ‘ be hit ratio at level Mi . Show that access
frequency to ‘Mi’ is given by
(b) Compare and contrast static interconnection network and dynamic interconnection network?
Q3 (a) Explain the Flynn’s classification for Computer Architectures based on the nature of the
(b) What does an array processor mean? What are the different SIMD computer organizations?
Q4. (a) A hierarchical cache main memory subsystem has following specifications:
(i) Cache access time of 50 n sec
(ii) Main storage access time of 500 n sec
(iii) 80% of request are for read
(iv) Hit ratio of 0.9 for read access and for write through scheme is used,
Determine:
a) Average access time of the system considering only memory read cycle
b) Average access time of the system both for read and write requests
c) Hit ratio taking into considerations the write cycle
(a) 100 n sec
(b) 180 n sec
(c) 0.72
(b) . What are the different hazards that occur in instruction pipeline and how these are
resolved?
Q5. (a) Consider the following reservation table for a four stage pipeline with a clock cycle ι=20ns.
1 2 3 4
S X X
1
S X
2
S X
3
a. What are the forbidden latencies and initial collision vector?
b. Draw the state transition diagram for scheduling the pipeline.
c. List all the simple cycle and greedy cycle.
d. Determine the optimal constant latency and minimal average latency (MAL)?
e. Determine the throughput of this pipeline. Lower bound on the MAL for this pipeline.
(b) What are the properties of the Vector Processors? Explain each component of Vector-