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    anshubankofindia
    The document contains 6 questions related to computer architecture. Question 1 asks about data dependencies in a program, memory hierarchies, and types of interconnection networks. Question 2 discusses memory hierarchy analysis and static vs dynamic interconnection networks. Question 3 covers Flynn's taxonomy of computer architectures and array processors. Question 4 calculates cache performance metrics and describes pipeline hazards. Question 5 analyzes a reservation table for a 4-stage pipeline and defines properties of vector processors. Question 6 provides short notes on parallel vs distributed systems, multiprocessing, pipelines, systolic arrays, and proves Amdahl's Law.

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    Q1

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    anshubankofindia
    26 views3 pages
    The document contains 6 questions related to computer architecture. Question 1 asks about data dependencies in a program, memory hierarchies, and types of interconnection networks. Question 2 discusses memory hierarchy analysis and static vs dynamic interconnection networks. Question 3 covers Flynn's taxonomy of computer architectures and array processors. Question 4 calculates cache performance metrics and describes pipeline hazards. Question 5 analyzes a reservation table for a 4-stage pipeline and defines properties of vector processors. Question 6 provides short notes on parallel vs distributed systems, multiprocessing, pipelines, systolic arrays, and proves Amdahl's Law.

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    The document contains 6 questions related to computer architecture. Question 1 asks about data dependencies in a program, memory hierarchies, and types of interconnection networks. Question 2 discusses memory hierarchy analysis and static vs dynamic interconnection networks. Question 3 covers Flynn's taxonomy of computer architectures and array processors. Question 4 calculates cache performance metrics and describes pipeline hazards. Question 5 analyzes a reservation table for a 4-stage pipeline and defines properties of vector processors. Question 6 provides short notes on parallel vs distributed systems, multiprocessing, pipelines, systolic arrays, and proves Amdahl's Law.

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    Download as docx, pdf, or txt
    26 views3 pages

    Q1

    Uploaded by

    anshubankofindia
    The document contains 6 questions related to computer architecture. Question 1 asks about data dependencies in a program, memory hierarchies, and types of interconnection networks. Question 2 discusses memory hierarchy analysis and static vs dynamic interconnection networks. Question 3 covers Flynn's taxonomy of computer architectures and array processors. Question 4 calculates cache performance metrics and describes pipeline hazards. Question 5 analyzes a reservation table for a 4-stage pipeline and defines properties of vector processors. Question 6 provides short notes on parallel vs distributed systems, multiprocessing, pipelines, systolic arrays, and proves Amdahl's Law.

    Copyright:

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    of 3

    SET-1

    Q1 .(a) Analyse the data dependencies among the following statements in a given program:

    S1: Load R1, 1024                       / R1 ß1024 /

    S2: Load R2, M(10)                      / R2 ßMemory(10) /

    S3: Add R1, R2                           / R1 ßR1) + (R2) /

    S4: Store M(1024), R1                 / Memory(1024) ß(R1) /

    S5: Store M(R2), 1024                 / Memory(64) ß1024 /

    Note that (Ri) means that the content of register Ri and Memory(10) contains 64 initially.

    1. Draw a dependence graph to show all the dependencies.


    2. Are there any resource dependencies if only one copy of each functional unit is available in
    the CPU?

    (b) Explain the types of system performance factors in a parallel architecture.

    (c) Draw a 16 bit omega network using 2 x 2 switches as building block.

    (d) What do you mean by control flow and Data flow computers? State advantage and disadvantage of
    data flow computing?

    (e) Answers the following questions for the k-ary n-cube network.

    1. How many nodes are there?


    2. What is the network diameter?
    3. What is bisection bandwidth?
    4. What is node degree?

    Q2. (a) Consider n level hierarchical memory, let ‘hi ‘ be hit ratio at level Mi . Show that access
    frequency to ‘Mi’ is given by

    fi = (1-h1) (1-h2) (1-hi-1).hi

    Further show that effective access time


    Teff = ∑ fi ti
    here ‘tI’ are measured with respect to CPU

    (b) Compare and contrast static interconnection network and dynamic interconnection network?

    Q3 (a) Explain the Flynn’s classification for Computer Architectures based on the nature of the

    instruction flow executed by the computer with diagram

    (b) What does an array processor mean? What are the different SIMD computer organizations?

    Q4. (a) A hierarchical cache main memory subsystem has following specifications:
    (i) Cache access time of 50 n sec
    (ii) Main storage access time of 500 n sec
    (iii) 80% of request are for read
    (iv) Hit ratio of 0.9 for read access and for write through scheme is used,
    Determine:
    a) Average access time of the system considering only memory read cycle
    b) Average access time of the system both for read and write requests
    c) Hit ratio taking into considerations the write cycle
    (a) 100 n sec
    (b) 180 n sec
    (c) 0.72

    (b) .       What are the different hazards that occur in instruction pipeline and how these are
    resolved?

    Q5. (a) Consider the following reservation table for a four stage pipeline with a clock cycle ι=20ns.

      1 2 3 4
    S X     X
    1
    S   X    
    2
    S     X  
    3

    a.       What are the forbidden latencies and initial collision vector?

    b.       Draw the state transition diagram for scheduling the pipeline.
    c.       List all the simple cycle and greedy cycle.

    d.       Determine the optimal constant latency and minimal average latency (MAL)?

    e.       Determine the throughput of this pipeline. Lower bound on the MAL for this pipeline.

    (b) What are the properties of the Vector Processors? Explain each component of Vector-

    Register Processors with diagram.

    Q6. (a) Write a short notes:

    1. Differentiate between parallel processing and distributed processing.


    2. Multiprocessing and Time sharing system.
    3. Fixed point addition pipeline
    4. Systolic Array
    5. Floating point multiplication pipeline

    (b) State and prove Amdahl’s Law.

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